jagdishkapadnis.files.wordpress.com · Web view2016. 1. 8. · programmable control word register (CWR), using which user can program the configuration of 8255 according to requirements.

PVG’s College of Engineering,Nashik

Microprocessor Interfacing Laboratory Second Year Computer Engineering

Assignment 8:

8255 PPI

Problem Definition:(a) Write 8086 ALP to interface DAC and generate following waveforms on oscilloscope,

(i) Square wave - Variable Duty Cycle and Frequency.

(ii) Ramp wave - Variable direction, (iii) Trapezoidal wave, (iv) Stair case wave

Theory:• The 82C55 is a popular interfacing component, that can interface any TTL-compatible

I/O device to a microprocessor.

• It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of

an integrated chipset).

• Requires insertion of wait states if used with a microprocessor using higher that an 8

MHz clock.

• PPI has 24 pins for I/O that are programmable in groups of 12 pins and has three distinct

modes of operation.



Block diagram of 8255:



Operating Modes Of 8255:It has two basic operating modes:

1. BSR Mode (Bit Set- Reset Mode)

2. I/O Modes (Input/Output Modes )

1. Mode 0 – Basic Input/Output Mode

2. Mode 1 – StrobedInput/Output Mode

3. Mode 2 – Bi-directional Bus Mode

To control the operations of 8255, it has provided programmable control word register

(CWR), using which user can program the configuration of 8255 according to requirements.

BSR Mode of 8255 Control Word



I/O Modes of 8255 Control Word

Connections for waveform generation:Connect 8255 to DAC PIO-card through FRC and connect OUT of DAC-PIO-card to CRO

and observe the output waveforms on CRO.

Connections for stepper motor rotation:Connect 8255 to STP PIO-card through FRC and connect STP-PIO-card to stepper motor

and observe the rotation of shaft rotation.

Conclusion:



Assignment 9:

8253 PIT

Problem Definition:

Write 8086 ALP to program 8253 in Mode 0, modify the program for hardware retrigger able

Hardware Triggered and software triggered strobe mode. Observe the waveform at GATE Mono

shot mode. Generate a square wave with a pulse of 1 ms. Comment on the difference between &

out pin of 1C 8254 on CRO.

Theory:Features:

• Three Independent 16-Bit Counters,

• Clock input upto 10 MHz,

• Status Read-Back Command,

• Six Programmable Counter Modes,

• Binary or BCD Counting,

• Single +5V Supply,

• 8254 is superset of PIT-8253.



Block Diagram Of 8253:

Control Word Format:



Modes Of 8254:

1. Mode 0: Interrupt On Terminal Count

2. Mode 1: Hardware Retriggerable One-shot

3. Mode 2: Rate Generator

4. Mode 3: Square Wave Mode

5. Mode 4: Software Triggered Strobe

6. Mode 5: Hardware Triggered Strobe (Retriggerable)

Mode 0: Interrupt On Terminal CountSet Output Bit when timer done.The output will start off zero. The count is loaded and

the timer will start to count down. When the count has reached zero the output will be set

high, and remain high until the next count has been reloaded.

Mode 1: Hardware Retriggerable One-shotProgrammable One-Shot. The output will go low following the rising edge of the gate

input. The counter will count and the output will go high once the counter has reached zero.

Mode 2: Rate GeneratorThe counter will continually count down, when the count reaches zero, the output will pulse low

and the counter will be reloaded.

Mode 3: Square Wave ModeThis mode is similar to Mode 2 except the output remains low for half of the timer period

and high for the other half of the period.

Mode 4: Software Triggered StrobeThe output will remain high untill the timer has counted to zero, at which point the output

will pulse low and then go high again.

Mode 5: Hardware Triggered Strobe (Retriggerable)



The counter will start counting once the gate input goes high, when the counter reaches

zero the output will pulse low and then go high again.

Connections And Execution Steps:

• Mode 0: Interrupt On Terminal Count1. Connect clk0 to pulser key0

2. Connect GATE to Vcc.

3. Give counter value+2 clicks.

4. Connect OUT0 to RST 7.5.

5. See output Dynalog-86.

• Mode 1: Hardware Retriggerable One-shot1. Connect clk0 to pulser key0

2. Connect GATE to ground.

3. Give counter value clicks.


5. Give 1 click.

6. Connect GATE to ground.

7. Give 1 click.

8. Give counter value clicks.

Mode 3: Square Wave Mode1. Connect clk0 to pulser key0


3. Give Counter value clicks.

4. For half clicks OUT will glow and for remaining half clicks OUT will be off.

Conclusion:



Assignment 10:

8251 USART

Problem Definition:Perform an experiment to establish communication between two 8251 systems A and B. Program

8251 system A in asynchronous transmitter mode and 8251 system B in asynchronous receiver

mode. Write an ALP to transmit the data from system A and receive the data at system B. The

requirements are as follows:

Transmission:

• message is stored as ASCII characters in the memory.

• message specifies the number of characters to be transmitted as the first byte.

Reception:

• Message is retrieved and stored in the memory.

• Successful reception should be indicated

Theory:Features:

• Synchronous and Asynchronous operation

• Synchronous 5 – 8 bit character; Internal & External Character Synchronization;

Automatic Sync insertion.

• Asynchronous 5 – 8 bit character; clock rate 1, 16 or 64 times baud rate; Break character

generation; 1, 1.5 or 2 stop bits; False start bit detection; Automatic break Detect and

handling.

• Synchronous Baud Rate: DC to 64K Baud

• Asynchronous Baud Rate: DC to 19.2K Baud

• Full duplex, double-buffered transmitter and receiver



• Error detection- Parity, overrun and framing

• Compatible with an extended range of Intel microprocessors

• 28 pin DIP package

• TTL Compatible

• Available in EXPRESS and Military versions.

Block diagram:



Mode instruction format

Command instruction format:

Status word format:



Connections:1. Connect DSRA# to ground.

2. Connect CTSA# to ground.

3. Connect RTSB# to ground.

4. Connect DTRB# to ground.

5. Connect TXDA# to RXDB#.

Conclusion:



Assignment 11:

8279 Keyboard and Display controller

Problem Definition:Write 8086 ALP to initialize 8279 and to display characters in right entry mode.

Provide also the facility to display

• Character in left entry mode.

• Rolling display.

• Flashing display

TheoryFeatures:

• Simultaneous Keyboard Display Operations

• Scanned Keyboard Mode

• Scanned Sensor Mode

• Strobed Input Entry Mode

• 8-Character Keyboard FIFO

• 2-Key Lockout or N-key Rollover with Contact Debounce

• Dual 8- or 16-Numerical Display

• Single 16-Character Display

• Right or Left Entry 16-Byte Display RAM

• Mode Programmable from CPU

• Programmable Scan Timing

• Interrupt output on Key Entry



Block diagram of 8279:

Keyboard/Display Mode Set:

• D D

0 0 : Eight 8-bit character display – left entry

0 1 : Sixteen 8-bit character display – left entry

1 0 : Eight 8-bit character display – right entry

1 1 : Sixteen 8-bit character display – right entry.



• K KK

000: Encoded Scan Keyboard- 2 Key Lock-out

001: Decoded Scan Keyboard- 2 Key Lock-out

010: Encoded Scan Keyboard- N Key Roll=over

011: Decoded Scan Keyboard- N Key Roll=over

100: Encoded Scan Sensor Matrix

101: Decoded Scan Sensor Matrix

110: Strobed Input, Encoded Display Scan

111: Strobed Input, Encoded Display Scan

Connections:Connect SL0-SL3 to BSL0-BSL3.I/O address selection 1-ON,other off

Conclusion:



Assignment 12:

Terminate-but-Stay-Resident Programs

Problem Definition:Write TSR program to change the color of screen of DOS shell of c after some interval of time.

Theory:

Most MS-DOS applications are transient. They load into memory, execute, terminate, and DOS

uses the memory allocated to the application for the next program the user executes. Resident

programs follow these same rules, except for the last. A resident program, upon termination,

does not return all memory back to DOS. Instead, a portion of the program remains Resident,

ready to be reactivated by some other program at a future time. Resident programs also known as

terminate and stay resident programs or TSRs, provide a tiny amount of multitasking to an

otherwise single tasking operating system. Until Microsoft Windows became popular, resident

programs were the most popular way to allow multiple applications to coexist in memory at one

time. Although Windows has diminished the need for TSRs for background processing, TSRs

are still valuable for writing device drivers, antiviral tools, and program patches. This chapter

will discuss the issues you must deal with when writing resident programs.

MS-DOS maintains a pointer to the beginning of unused memory. Programs load into memory at

this position and terminate execution by returning control to MS-DOS. Normally, the pointer

remains unchanged, allowing MS-DOS to reuse the same memory when loading other programs.

A terminating program can, however, prevent other programs from loading on top of it. These

programs exit to MS-DOS through the terminate-and-stay-resident function, which resets the

free-memory pointer to a higher position. This leaves the program resident in a protected block

of memory, even though it is no longer running.

The terminate-and-stay-resident function (Function 31h) is one of the MS-DOS services invoked

through Interrupt 21h.



Algorithm:

1. Start

2. Declare interrupt handler function.

3. Declare for type of pointer variable for screen and pass graphic mode address.

4. Define integer data type ticks for counting time delay.

5. Declare chara. Data type for color.

6. Get vector address of TSR.

7. Set vector address of TSR.

8. Keep program resident.

9. Stop.

Conclusion:

Assignment 13:



Problem Definition:Study of i5 motherboard

Basic Features Of Intel I5 Processor:As i5 processors are more advanced as compared to the i3 or all the previous versions of the

processors. It has lot of features that deals the advanced technologies in a very respectable way.

Some of the basic key Intel i5 features are as follows:

1. Basically i5 processors are introduces to do the intelligent networking and enhance the

performance of the working for the sake of different purposes such as for gaming, faster

procession, reliable data transmission etc.

2. One of the important feature of the i5 processors is that it automatically manages the power

supply where needed and does not break the speed and the performance of the system.

3. i5 processors also allow the user to enjoy the heavy applications with the higher rate such as

HD video composing, composing a music and many more.

4. i5 also provide the opportunity to the users to use the system with multi tasking.

5. i5 processor are also able to increase the memory of the system and help users to work with

the high bandwidth and great performance.

6. A big feature of the i5 processors is that they have ability to run two multitasking processors

together that are generally called as dual processors and can increase the working performance of

the system efficiently.

7. Turbo boost technology of i5 processors is the key beneficial feature of the i5 processors that

allow the users to do their regular and important working with the help of heavy applications

8. An i5 processor also consists of Hyper Threading technology that enables the users for

multitasking and improves their business or working by working on the two different tasks at the

same time.

Technical Specifications Of I5 Processors:



i5 processors basically introduced to mange the different strategies between the low and the

advanced working. Some of the technical specifications of the i5 processors that deal with the

performing or working capacity and the technicalities of operation of the i5 processors in the

computer system are listed below.

1. i5 processors have ability to work with integrated memory and can enhance the performance

of the applications. The increase the memory up to 1333 MHz.

2. As i5 processors have high speed performing rate so they are able to perform at the maximum

CPU rate of 3.6 GHz

3. Turbo technology is present in the device that boost up the working speed of the

computational systems.

4. It also provides the 64 bit architecture for the users for the reliable and much more faster

working.

5. Micro architecture for the i5 processors was presented by the Nehalem and these processors

have a cache rate up to 8 MB.

More Advantages Of I5 Processors:There are many more benefits of the i5 processors because they are advanced form of the

processing units. Some more important benefits of the i5 processors are given below

1. Providing high quality visualization for advanced applications

2. High performance with the help of dual processor technology

3. HD graphics enhance the video graphing and applications related to the same architecture

Block Diagram Of Intel Core I5 Motherboard With Intel P55 Express



Chipset:

Conclusion:

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