page 1 CSEM, E. Vittoz, 2003 Weak inversion • Behaviour and model of MOS transistors in weak inversion [1,2,3]. • Examples of analog circuits. • Exploratory analysis of weak inversion logic [4,5]. Eric A.Vittoz CSEM, Centre Suisse d'Electronique et de Microtechnique SA Jaquet-Droz 1, CH 2007 Neuchâtel, Switzerland [email protected]WEAK INVERSION IN ANALOG AND DIGITAL CIRCUITS CCCD Workshop 2003, Lund, Oct. 2-3
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page 1
CSEM, E. Vittoz, 2003
Weak inversion
• Behaviour and model of MOS transistors in weak inversion [1,2,3].
• Examples of analog circuits.
• Exploratory analysis of weak inversion logic [4,5].
Eric A.VittozCSEM, Centre Suisse d'Electronique et de Microtechnique SA
• Only 3 parameters: VT0, n (inside VP) and IS (or β) to model the currentfrom weak to strong inversion.
[9]
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CSEM, E. Vittoz, 2003
Weak inversion
• Definition: Inversion coefficient: IC = the larger of IF/IS and IR/IS
2VDSsat
2UTstrong inversion: IC = » 1
weak inversion: IC « 1
moderate inversion: IC ≅ 1
1
b
a
weak
strong102
10-2
10-4-20 20 40 600
voltage
IF,RIS
curr
ent
VP -VS,DUT
CONTINUOUS MODELS WEAK-STRONG INVERSION
with:
VP =(VG-VT0)/n
ID = IF - IR
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CSEM, E. Vittoz, 2003
Weak inversion
strong inv.0.01 0.1 1 10
0.20
0.40.6
0.81.0
a
b
weak moderate
strong inv.asymptote:
TRANCONDUCTANCE FROM WEAK TO STRONG INVERSION
• Transonductance gm from gate in saturation
gmID
nUT
model
model
IC=ID/IS
gm= 2βID/n
weak inversion asymptote: gm=ID/(nUT)
100
• gm/ID decreases with increasing inversion coefficient IC.• gm/ID is maximum in weak inversion.
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CSEM, E. Vittoz, 2003
Weak inversion
+ exponential :
+ min. VDSsat
+ min. gate voltage
+ min. gate capacitance
+ max. gm/ID :
+ gm(ID) linear
+ gm independent of β
SUMMARY OF FEATURES OF WEAK INVERSION
µUT2πL2
VDUT
-VSUT
-VG-VT0
nUTID = IS e ( e - e )• Large-signal DC model:
+ max. intrinsic voltage gain+ min. input noise density for given ID+ max. bandwidth for given kT/C and ID+ min. input offset voltage– max. output noise current for given ID– max. current mismatch :
dominated by VT -mismatch:
⇒
+ max. Ion/Ioff for given voltage swing+ translinear circuits and log domain filters
– intermodulation in RF front ends⇒
–
– Low speed: fT≅
∆IDID
∆VT0nUT
=
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CSEM, E. Vittoz, 2003
Weak inversion
• Weak inversion approached for constant temperature T.
VDSsat2UT
2 IC = decreased by k2
EVOLUTION OF IC WITH SCALED-DOWN PROCESSES
• Scaling-down of process:
• dimension scaling by factor k
• all voltages decreased by k, except UT:
- analog circuits: VDSsat must be decreased by k, thus
- digital circuits: VB decreased by k, thus
VB -VT02nUT
2ICon = decreased by k2
• Transition frequency: fT = increased by kµVDSsat
2πL2
- weak inversion with L=100nm : fT >4 GHz
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CSEM, E. Vittoz, 2003
Weak inversion
T1
T2 T3 T4
T5
II
VRVDS1
VD2
VDS2
substrate
VDS1 = UT ln [ P (1+ 2M)]
for P = M = 8 : VDS1=5UT,
LOW-VOLTAGE CASCODE IN WEAK INVERSION
• Model in weak inversion yields:
VDSsat = 4 to 6UT per transistor
thus VD2 = 10UT sufficient to saturate T1 and T2
= P and =Mβ2β3
β4β5
All transistors in weak inversion with:
[2]
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CSEM, E. Vittoz, 2003
Weak inversion
EXTRACTION OF UT AND CURRENT REFERENCE
VR = RI2 =UT lnK
I2
I1Q (unstable)
P(stable)
mirror T1-T2
mirr
or T3
-T 4
slop
e K
T1
T2≡KT1T5
T4≡T3
T3T6
source
sink
I1 I2
R VR
V+
V-
• For T1 and T2 in weak inversion:
• Self-starting if leakage of T2 larger than that of T1.
[1]
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CSEM, E. Vittoz, 2003
Weak inversion
T4
V-
T1
T3
T5
T6V+
T7
T9
II
I
T2
I
VR
T8
CURRENT GENERATION WITHOUT RESISTOR
• Resistor replaced by transistor T8 in conduction [10]:
• T2 and T1 in weak inversion with β2 = Kβ1
• T6 =T3 =T4 =T7 and T5 = T1
• T8 and T9 in strong inversion with β8 =Aβ9 (A»1 to have T8 in conduction)
I = 2nβ8UT.Aln2K = IS8.Aln2K2yields:
• Reference current I proportional to specific current IS8
• Useful to bias transistors at inversion coef.IC independently of process.
• If mobility ~ T -2, then compensation by UT : I ~ IS independent of T 2
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CSEM, E. Vittoz, 2003
Weak inversion
MOS TRANSISTOR OPERATED AS A PSEUDO-RESISTOR
Consequence of basic property ID = F(VS) - F(VD):
• Networks of transistors with same gate voltage are
• linear with respect to currents• thus equiv. for currents to a resistive prototype, with Gi=1/Ri~ISi• ground in res. prototype correspond to saturated transistors.• example of application: current-mode linear attenuator (e.g. R-2R).
• In weak inversion:• linearity of currents even for different gate voltages
• VBopt and Pmin increase for decreasing α• At Pmin : Pdyn»Pstat
• Increasing I0 does not allow to reduce VB significantly for Td const.
1
• For α > 5%, power reduction by >20 compared to Pdyn at 1V.
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CSEM, E. Vittoz, 2003
Weak inversion
MAXIMUM SPEED
• Since Td ≅ and Ionmax ≅ ICon IS (inv. coeff* spec. current), thus: CVBIon
Tdmin ≅ CIS
VBICon
Tdmin(weak) ≅ VB CIS
process• Limit of weak inversion: ICon ≅1, thus
• Higher speed can only be obtained by entering moderate or strong inv.
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CSEM, E. Vittoz, 2003
Weak inversion
10
103
105
10210110-1 1 1030
20
40
60
"on" inv. coeff. ICon
param.Ion/Ioff
∆VGSnUT
VG
S s
win
g
EFFECT OF ENTERING MODERATE AND STRONG INVERSION
• More voltage swing neededto obtain Ion/Ioff
• from continuous current model:
• Degeneration of logic states:
• reduction of logic swing• large increase of static current Istat• loss of bistability• more supply voltage needed.
0 ICon
vH
2 40
1
3
4
3
vL
1
2logicswing
n=1.6vB=4
IstatIS
(using continuous model of ID)
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CSEM, E. Vittoz, 2003
Weak inversion
NUMERICAL RESULTS
• Simple inverter replaced by 3-input NAND-gate:• approx. equivalent to inverter with
L = 3-time that of n-ch transistor
C = 6-time that of min. inverter(includes Cinterconnect=C/2).
VBC
parameter process A process B unit
min. channel length Lmin 500 180 nmequiv. spec. current IS 200 400 nAequiv. load capac. C 20 4 fFspecific energy C(nUT)2 28 4.2 aJP/f for α=1 VB=4UT 228 44 aJ(P/f)min for α=0.01 and VBopt=6nUT 1.46 0.22 fJPdyn/f at VB=1V 20 4 fJfmax1 for α=1 and VB=4UT 50 500 MHzfmax2 for α=0.01 and VB=VBopt 0.22 2.56 MHzPmin at fmax2 32.5 56.3 nW
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CSEM, E. Vittoz, 2003
Weak inversion
PRACTICAL CONSIDERATIONS AND LIMITATIONS
• Low-voltage power source• should be proportional to UT (PTAT)• need for power-efficient adapter from higher supply voltage.
• Asymmetry• p/n asymmetry may result in speed reduction.
• Mismatch• dominated by threshold mismatch δVT• may result in speed reduction proportional to δVT /VB.
• Short channel effects: should not drastically degrade the results.
• Gate leakage current : should be alleviated by very low VB.
• Adjustment of I0 orTd to required value
• control by VS with charge pump in loop [18]; n>1 needed (no SOI!)
• corresponds to threshold adjustment unavoidable at very low VB.
• System architectures and applications.
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CSEM, E. Vittoz, 2003
Weak inversion
SYSTEM ARCHITECTURE AND APPLICATIONS
• Duty factor α must be maximized to reach minimum P/f,
(where f is the average transition frequency), thus
• avoid idling gates (contrary to traditional CMOS culture)
• new architectures needed:
- maximally active gates of minimum speed (max. delay time Td)
- particular problem with RAMs (short Td but sparse activity)
- how? new constraints should result in novel solutions.
• partition the system in blocks of comparable α and Td
- optimum VB and I0 for each block (separate I0 control).
• Maximum frequency much lower than for strong inversion:
• best applicable when no high local speed is required
• m-parallelize: mTd but same power if same α (m units with P/m)
- digital image processing ?
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CSEM, E. Vittoz, 2003
Weak inversion
CONCLUSION
• Weak inversion permits very low supply voltage VB
• approached with scaled-down VB: IC ~ VB• limit for scaled-down VB.
• Analog: • VB>10UT = 250 mV• provides maximum gm/ID• bipolar-like behaviour can be exploited in new schemes.
• Digital: • VB> 4UT = 100mV• transistor not a switch but a current modulator (Ion/Ioff)• new architectural approaches for max. duty factor α.• ultimum (asymptotic) limit for low power*delay.
• Low speed, but keeps increasing with 1/L2 in scaled down processes.
2
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CSEM, E. Vittoz, 2003
Weak inversion
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