WAFER-BOND MICRO-VOID PHYSICAL ANALYSIS C. Cassidy 1 , H. Plank 2 , T. Ganner 2 , L.G.W. Tvedt 3 , C. Gspan 2 , M. Dienstleder 2 , J. Wagner 2 , M. Krause 4 , C. Patzig 4 , S. Brand 4 , B. Böttge 4 , J. Siegert 1 1 austriamicrosystems AG 2 FELMI-ZFE (Graz, Austria) 3 SINTEF ICT, Microsystems and Nanotechnology (Oslo, Norway) 4 Fraunhofer-IWM (Halle, Germany)
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WAFER-BOND MICRO-VOID PHYSICAL ANALYSIS...32 Conclusions •Micro-void origin –Micro-voids are caused by nm-scale local topography on the backside of the polished bond surface, perhaps
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WAFER-BOND MICRO-VOID
PHYSICAL ANALYSIS
C. Cassidy1, H. Plank2, T. Ganner2, L.G.W. Tvedt3, C. Gspan2, M.
Dienstleder2, J. Wagner2, M. Krause4, C. Patzig4, S. Brand4, B. Böttge4,
J. Siegert1
1austriamicrosystems AG 2FELMI-ZFE (Graz, Austria)
3SINTEF ICT, Microsystems and Nanotechnology (Oslo, Norway) 4Fraunhofer-IWM (Halle, Germany)
2
Purpose
• Share a 3D-integration
analysis problem
• Highlight real-life practical
problems & difficulties
• Get feedback & ideas…
3
Outline
1. Introduction to bonding & “micro-voids”
2. PFA Successes
3. PFA challenges & problems
4. Summary, current status
5. Workshop question
Technology overview
4
Solder balls
TSVs
- CMOS processing
- Wafer bonding
- TSV (unfilled “via last”)
- Finish CMOS/bumping
Wafer bond
interface
Wachmann et al., ICMAT 2011
Wafer Bonding
• Bond process: – Plasma-activation
– Direct bonding (Si/SiO2)
– Low temperature anneal
– CSAM
• Bond surfaces – 1) Polished Si wafer
– 2) Deposited oxide layer, CMP finish (lower)
5
Pre-bonding
Post-bonding
Kraft et al., ECTC 2011
EVG
Gemini
toolset
What is a “micro-void”?
6
Wafer-level CSAM detects circular features in the bond
interface.
Specific size distribution (diameter ~100µm)
Micro-void TSVs
Wafer-level Scanning
acoustic microscopy
CSAM
“upper
wafer”
Bond oxide
“lower”
wafer
“Micro-void”
TSV
Bond
Interface
Micro-void questions
7
– What is the root cause?
– Reliability risk or cosmetic defect?
– Do they move or grow?
– Interrupted TSV connection?
– Fracture/delam initiation point?
Fig. B
Fig. A
Fig. C
TSVs
CSAM
Micro-void physical analysis
8
Physical analysis
9
Accessing the bond interface
Bond
interface
The interface is
not easy to
access
Sample preparation approach
10
1. Si Etch removal, oxide
underside as etch stop
“upper
wafer”
Bond
interface
Optical
microscopy
Lower wafer
selectively
etched away
Lower Si removed using
wet/dry etch
Bond oxide
PRO: Defect is visible and
accessible to PFA techniques
CON: Defect might be
changed by etch/release
process
Optical microscopy (after Si etch
removal)
11
Delamination/ voids/
bond defects
“upper
wafer”
Optical
microscopy
Bond oxide
11
1 2 3
Optical microscopy; 3 distinct
zones can be discerned
CSAM
Cross-section & in situ
optical microscopy
12 12
1. Defect is undisturbed
2. Outer delaminated
region is disturbed.
Trapped gas escapes,
unbonded oxide at the
polishing front fractures
off, following the
contour of the ring
3. As 2. Polishing front
is now right “in” the ring
region, but has not
compromised it yet.
4. The ring is “opened”
by the polishing front,
allowing the gas inside
to escape.
5. None of the oxide at
the polishing front in
the vicinity of the defect
is now bonded, and
fractures and rips off
easily during polishing
1. 2. 3. 4. 5.
Defects appear to consist of…
- A. outer debonded area
- B. sealing ring (bonded/ contaminant)
- C. internal debonded area A
B C
13
Defect 1
Is there a foreign contaminant?
- ToF-SIMS depth profile (F-IWM), through bond interface
- No foreign elements/compounds could be detected
Before ToF
depth profile
After ToF
depth profile
Void collapse example (OM)
14
Pre-collapse Post-collapse
- Voids collapse after e.g. ultrasonic cleaning, mechanical,
pressure, vacuum exposure (SEM/FIB), time…
- Complicates PFA attempts
What topograpy is associated with
the defect?
15
Post-collapse (defocus) 8nm ridge
10nm recess
AFM on the oxide surface (ZFE), after collapse
Ultrasonic
agitation to
collapse the
void
TEM & analysis (bond oxide still in place)
16
Successful micro-
void TEM lamella
preparation
What are the recess and
ridge composed of?
Si substrate
Bond oxide
TEM
17
5 n m 5 n m
Reference
area
Defect area
EFTEM shows Pt
EFTEM shows Si and O
EFTEM shows Si and O
2.8 nm
5 n m5 n m Si
Si Si
Bond oxide Bond oxide
Sample prep Pt
Thick (5-8nm)
oxide layer?
Typically 1-2nm native oxide expected.
e.g. Suni et al, J. ECS, 2002
Sample preparation approach
18
2. (Assisted) Debonding
PRO: Bond interface
is exposed for surface
analysis
CON: Unreliable
debonding, possible
material transfer,
defect navigation,
contamination
A
B
C
White light interferometry
(debonded Si surface)
19
WLI (Sintef) identified a slight recess (~-10nm, blue in the
image below), with an enclosing raised ring (~+15nm, red in
the image below).
AFM (debonded surfaces, ZFE)
Polished backside Si surface Polished oxide surface AFM
artifact
Problem stems from
topography on polished
Si surface.
Topographical surface analysis on both surfaces…
No significant
topography
Polished oxide
surface is OK!
Summary of useful PFA results
• Micro-voids are caused by existing surface topography.
• This topography is uniquely associated with the polished Si wafer.
• ToF-SIMS indicates that no foreign species are present.
• TEM identifies a suspiciously thick oxide layer (5-8nm) in the defect region