W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California The CMOS Inverter: Current Flow during Switching V IN V OUT V DD.

W. G. OldhamEECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California

The CMOS Inverter: Current Flow during Switching

VIN

VOUT

VDD

VDD00

N: offP: lin

N: linP: off

N: linP: sat

N: satP: lin

N: satP: sat

A B D E

C

ii

i

S

D

G

GS

D

VDD

VOUTVIN


Power Dissipation due to Direct-Path Current

VDD-VT

VT

time

vIN:

i:

Ipeak

VDD

0

0

i

S

D

G

GS

D

VDD

vOUTvIN

peakDDscdp IVtE Energy consumed per switching period:

tsc


An NMOSFET is a closed switch when the input is high

N-Channel MOSFET Operation

NMOSFETs pass a “strong” 0 but a “weak” 1

Y = X if A and B

Y = X if A or B

BA

XB

A

XY Y


A PMOSFET is a closed switch when the input is low

P-Channel MOSFET Operation

PMOSFETs pass a “strong” 1 but a “weak” 0

Y = X if A and B = (A + B) Y = X if A or B

= (AB)

BA

XB

A

XY Y


Pull-Down and Pull-Up Devices• In CMOS logic gates, NMOSFETs are used to connect the

output to GND, whereas PMOSFETs are used to connect the output to VDD.– An NMOSFET functions as a pull-down device when it is

turned on (gate voltage = VDD)– A PMOSFET functions as a pull-up device when it is turned on

(gate voltage = GND)

F(A1, A2, …, AN)

PMOSFETs only

NMOSFETs only…

…

Pull-upnetwork

Pull-downnetwork

VDD

A1

A2

AN

A1

A2

AN

input signals


CMOS NAND Gate

A B F0 0 10 1 11 0 11 1 0

A

F

B

A B

VDD


CMOS NOR Gate

A

F

B

A

B

VDD A B F0 0 10 1 01 0 01 1 0


CMOS Pass Gate

A

X Y

A

Y = X if A


Logic Gates – From Week 9b

A

BF=A·BAND F =

A

BNAND BA

NORA

BBA

NOTA A

ORA

BF=A+B

EXCLUSIVE OR

A

BBAF

F =


Logic Gates – How are they used?

A

BC=A·BAND

First of all we must agree on what is high (logical 1) or low (logical 0). Suppose 1.5 V is 1 and 0V is logical 0.

C would have the value of 1.5 V (logical 1).

But it would have the value of 0V (logical 0) if either one of the inputs were held at zero V.

AND1.5V

+

-1.5V

+

-


What are the most basic gates in Digital Electronics?

A B AB AB0 00 11 01 1

0001

1110

Not-AND = NAND

A

BAB

A B A+B BA 0 00 11 01 1

0111

1000

Not-OR = NOR

A

BBA

Typically use one or the other: “NAND logic” or “NOR logic”


How to Combine Gate to Produce a Desired Logic Function?(This is called Logical Synthesis)

Not-AND = NAND

A

BAB

A

B NOTAB

AND

Logically just an AND plus a NOT gate:

Example

A

BAB

AND

Shorthand for NOT


How to Combine Gate to Produce a Desired Logic Function?(More basic Logical Synthesis)

AAB

Example F= A B.

B

A

BA B.

Again a little shorthand is useful



Suppose we are given a truth table (all logic statements can be represented by a truth table). How can we implement the function?

Answer: There are lots of ways, but one simple way is implementation from “sum of products” formulation.

How to do this: 1) Write sum of products expression from truth table and 2) Implement using standard gates.

(Warning this is probably inefficient – we need to minimize, or simplify the expression)



Example:

A B C F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

or

Clearly: F= 1 if

C = 1B A

CAB =1

i.e. F= C +ABB A C



Example:

A B C F

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

F= C +ABB A C

ABC

ABC

F


More Logical Synthesis

Example:

A B F

0 0 0

0 1 1

1 0 0

1 1 1

F=A +ABB

A

B

A

B

F

Clearly

Thus

But it is easy to show that a simpler valid expression for F is F = B , hence:

B F

(ignore A)


What circuit of logic gates could produce these (arbitrarily chosen) outputs F in response to inputs A, B and C?

A B C F0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1


A B C

A

B

C

A B C

F

ABC

ABC

ABC

ABC

Example of general purpose circuit to implement the truth table of Table 22.4. (This solution is NOT minimized.)


Rules of boolean algebra. The two entries in the last row are used frequently and are known as DeMorgan’s theorem.

AND Rules OR Rules

A•A = A A+A = A

A•A = 0 A+A = 1

0•A = 0 0+A = A

1•A = A 1+A = 1

A•B = B•A A+B = B+A

A(BC) = (AB)C A+(B+C) = (A+B)+C

A(B+C) = AB+AC A+BC = (A+B)(A+C)

A•B = A+B A+B = A•B


Logical SynthesisGuided by DeMorgan’s Theorem

Demorgan’s Theorem :

C B A CBA or C BA CBA

Thus, for example:

CDAB CD AB F

A

B

C

D

F

Thus any sum of products expression can be immediately synthesized from NAND gates alone


Karnaugh Maps

• Graphical approach to minimizing the number of terms in a logic expression:

1. Map the truth table into a Karnaugh map (see below)

2. For each 1, circle the biggest block that includes that 1

3. Write the product that corresponds to that block.

4. Sum all of the products

A

B

2-variableKarnaugh Map

0 1

1

0A

1

0

BC00 01 11 10

3-variableKarnaugh Map

4-variable Karnaugh Map

CD00 01 11 10

AB

00

01

11

10


A B C S1 S0

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Input Output

00 01 11 10

0 0 0 1 0

1 0 1 1 1A

BC

BC AC AC AB

S1 = AB + BC + AC

Simplification of expression for S1:

Karnaugh Map Example

By simplifying we can reduce thenumber of gates, transistors, andthe size of the circuits.

W. G. Oldham EECS 40 Fall 2001 Lecture 2 Copyright Regents of University of California The CMOS Inverter: Current Flow during Switching V IN V OUT V DD.

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