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Chng 2
KIN TRC CPU V TP LNH
HBK Tp HCM-Khoa -TBMTGVPT: H Trung MMn hc: Vi X L
Ni dung 2.1 S KHI CPU 8 BIT C BN
2.2 T CHC CC THANH GHI
2.3 T CHC B NH
2.4 GHP NI BUS H THNG
2.5 CHU K BUS, CHU K MY
2.6 CC PHNG PHP NH A CH
2.7 TP LNH
Vi x l C nhiu lai vi x l (VXL) t rt n gin n rt
phc tp
Ph thuc vo rng bus d liu v thanh ghi v ALU, c cc VXL 4 bit , 8
bit , 16bit, 32 bit , 64 bit
Th d Z80 l VXL 8 bit
8086/88 l VXL 16 bit
Tt c cc VXL c Bus a ch
Bus d liu
Cc tn hiu iu khin: RD, WR, CLK , RST, INT, . . .
Bus ni v ngoi Bus ni (Internal bus) l ng dn truyn
d liu gia cc thanh ghi v ALU trong VXL Bus ngoi (External bus)
dng cho bn ngoi
ni n RAM, ROM v I/O rng ca bus ni v ngoi c th khc nhau. Th d
8088: bus ni l 16 bit, bus ngoi l 8 bit 8086: bus ni l 16 bit,
bus ngoi l 16 bit
2.1 S KHI CPU 8 BIT C BN
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S chc nng v gn chn chip Z80 Cc ng tn hiu
C 6 nhm tn hiu: Bus a ch 16 ng (A0 n A15) Bus d liu 8 ng (D0 n
D7) 6 ng iu khin h thng
5 ng iu khin CPU
2 ng iu khin bus CPU ( ) 3 ng dnh cho ngun cp in v xung nhp
(+5V, GND, v CLK)
M t chn Z80A15-A0 :Bus a ch (xut, tch cc cao, 3-state). Dng truy
cp b nh va cc cng I/O
Trong chu k lm ti I c t trn bus ny.
D7-D0 :Bus d liu (nhp/xut, tch cc cao, 3-state). Dng trao i d
liu vi b nh , I/O v ngt.
RD:c (xut, tch cc thp, 3-state) cho bit CPU mun c
d liu t b nh hay I/O
WR:Ghi (xut, tch cc thp, 3-state) cho bit bus d liu CPU gi d liu
hp l s c ct vo b nh hay thit
b I/O.
M t chn Z80MREQMemory Request (output, active Low, 3-state).
Indicates
memory read/write operation. See M1
IORQInput/Output Request(output,active Low,3-state)
Indicates
I/O read/write operation. See M1
M1Machine Cycle One (output, active Low).
Together with MREQ indicates opcode fetch cycle
Together with IORQ indicates an Int Ack cycle
RFSHRefresh (output, active Low).
Together with MREQ indicates refresh cycle.
Lower 7-bits address is refresh address to DRAM
M t chn Z80INT
Interrupt Request (input, active Low).Interrupt Request is
generated by I/O devices. Checked at the end of the current
instruction If flip-flop (IFF) is enabled.
NMI
Non-Maskable Interrupt(Input, negative edge-triggered). Higher
priority than INT. Recognized at the end of the current
InstructionIndependent of the status of IFFForces the CPU to
restart at location 0066H.
M t chn Z80BUSREQ
Bus Request (input, active Low).higher priority than NMI
recognized at the end of the current machine cycle.forces the CPU
address bus, databus, and MREQ, IORQ, RD, and WR to high-imp.
BUSACKBus Acknowledge (output, active,Low)indicates to the
requesting device that address, data, and control signalsMREQ,
IORQ, RD, and WR have entered their high-impedance states.
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M t chn Z80
RESET
Reset (input, active Low). RESET initializes the CPU as
follows:Resets the IFFClears the PC and registers I and RSets the
interrupt status to Mode 0.During reset time, the address and
databus go to a high-impedance state And all control output signals
go to the inactivestate. must be active for a minimum of three full
clock cycles before the reset operation is complete.
Kin trc h thng
2.2 T CHC CC THANH GHI
Z80 CPU
CONTROLSECTION
k
CONTROL BUS
SEQUENCERCONTROLLER
INTERNAL ADDRESS BUS (16 BIT)
INTERNAL DATA BUS (8 BIT)
16
INTERNAL CONTROL BUS
DECODER
REGISTERINSTRUCTION
RI
k
ALU
TMPA
A'
F
F'
ACT
ADDRESS BUSBUFFER
DATA BUS
BUFFER
BUFFER
13
8
IX
IY
SP
PC
W' Z'
B' C'
D'
H' L'
E'
B
W
D
H
Z
C
E
L
MUXMUX
M hnh lp trnh Z80 Tp thanh ghi A : Accumulator Register
F : Flag register
Two sets of six general-purpose registers
may be used individually as 8-bit A F B C D E H L (A F B C D E H
L)
or in pairs as 16-bit registers AF BC DE HL (AF BC DE HL)
The Alternative registers (A F B C D E H L) not visible to the
programmer but can access via:
EXX (BC)(BC') , (DE)(DE') , (HL)(HL')
EX AF, AF (AF)(AF')
what is this instruction useful for?
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Tp thanh ghi (tt) 4 16-bit registers hold memory address
(pointers)
index registers (IX) and (IY) are 16-bit memory pointers
16 bit stack pointer (SP)
Program counter (PC)
Program counter (PC)
PC points to the next opcode to be fetched from ROM
when the P places an address on the address bus to fetch the
byte from memory, it then increments the program counter by
one to the next location
Special purpose registers
I : Interrupt vector register.
R : memory Refresh register
Thanh ghi c (Flag Register)
S Sign Flag (1:negativ)*Z Zero Flag (1:Zero)H Half Carry Flag
(1: Carry from Bit 3 to Bit 4)**P Parity Flag (1: Even)V Overflow
Flag (1:Overflow)*N Operation Flag (1:previous Operation was
subtraction)**C Carry Flag (1: Carry from Bit n-1 to Bit n,
with n length of operand)
*: 2-complement number representation**: used in DAA-operation
for BCD-arithmetic
7 6 5 4 3 2 1 0
XS Z H X P N CV
DAA - Decimal Adjust Accumulator
before DAA after DAA
Op N C Bits 4-7 H Bits 0-3 A=A+.. C
ADD
ADC
0 0 0-9 0 0-9 00 00 0 0-8 0 A-F 06 00 0 0-9 1 0-3 06 00 0 A-F 0
0-9 60 10 0 9-F 0 A-F 66 10 0 A-F 1 0-3 66 10 1 0-2 0 0-9 60 10 1
0-2 0 A-F 66 10 1 0-3 1 0-3 66 1
SUB
SBCNEG
1 0 0-9 0 0-9 00 01 0 0-8 1 6-F FA 01 1 7-F 0 0-9 A0 11 1 6-F 1
6-F 9A 1
Adjusts the content of the Accumulator A for BCD addition and
subtractionoperations such as ADD, ADC, SUB, SBC, and NEG according
to the table:
Stack Pointer (SP) Dng lm con tr ch n
stack b nh ngoi
Khi a d liu vo
stack (PUSH), SP gim i 2 (ton hng 2 byte).
Khi ly d liu ra khi stack (POP), SP tng thm 2 (ton hng 2
byte).
V Z80 theo little endian nn
byte thp ca d liu s a ch thp Ch
iu
tng
sta
ck Chi
u t
ng a
ch
b
nh
Data15 0
2.3 T CHC B NH
T chc b nh
T chc b nh ty theo ng dng khc nhau ta c cc t chc khc nhau v ty
theo ROM, SRAM, DRAM m ta c cc kt ni tn hiu iu khin khc nhau.
Vi a ch 16 ng (A0 n A15), Z80 c th lm vic n ti a 64KB b nh.
Tm ng a ch thp (A0 n A7) cng c dng truy cp ti 256 cng I/O.
minh ho phn ny ta s kho st mt s th d.
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Giao tip ROM 1KB v 2 RAM 256 x 4
Ta mun Z80 kt ni vi cc b nh (vi cc chip ROM 1K x 8 v RAM 256 x
4) theo bng b nh sau
ROM 1 KB : 0000H03FFH
RAM 256 bytes : 0400H04FFH
A9..A0 A7..A0 A7..A0
Giao tip vi RAM
Giao tip vi SRAM 1KB Th d giao tip DRAM 8 KB xy dng t cc DRAM
4KB
2.4 GHP NI BUS H THNG
H my tnh Z80 ti thiu
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M rng giao tip cho Z80
c th m rng giao tip cho Z80, hng Zilog pht trin cc chip h tr
sau:
Z80 PIO l b iu khin I/O song song, n lm cho Z80 m rng thm thnh 2
cng I/O song song 8 bit. Chip cn c thm ng to ngt cho Z80 v cho php
ni logic OR cc chn ny li.
Z80 CTC l mch b m-nh th (counter-timer circuit) cho ngi thit k h
thng Z80 s dng n thc hin cc chc nng m v nh th.
Z80 SIO l mch nhp/xut ni tip (Serial Input/Output Circuit), chip
ny cung cp cho h Z80 vi 2 cng ni tip m c th s dng lin lc vi cc thit
b ngoi vi ni tip khc.
Z80 DMA thc hin vic truy cp b nh trc tip vi thit b ngoi.
Th d s phn cng mt kit da trn Z80
2.5 CHU K BUS, CHU K MY
Chu k lnh, chu k my v cc trng thi T
Chu k lnh l thi gian cn hon tt vic thc thi mt lnh.
Chu k my c nh ngha l thi gian cn hon tt mt tc v truy cp b nh,
truy cp I/O,(Vi Z80, chu k my c th ko di t 3 n 6 chu k xung nhp
)
T-state = 1/f (f: tn s Clock ca Z80) f= 4MHZ T-state=0.25 uS
Th d nh th CPU Z80
Ch ; 1 chu k lnh (Instruction Cycle) = 1 6 chu k my (Machine
Cycle) 1 chu k my (Machine Cycle) = 3 6 chu k T (T Cycle) 1 chu k T
= 1/fCLK (fCLK ; tn s ca thch anh gn vo Z80)
chu k my
C 7 chu k my vi Z80:1. Nhn m lnh (chu k M1)
2. c hoc ghi d liu b nh
3. c hoc ghi I/O
4. Yu cu/ghi nhn bus (Bus Request/Acknowledge)
5. Yu cu/ghi nhn INT
6. Yu cu/ghi nhn NMI
7. Thot khi lnh HALT
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Chu k nhn lnh (chu k M1) Thanh ghi R (Refresh)
c tng mi chu k M1. Bit 7 ca n khng bao gi b thay i bi M!;
ch c 7 bit thp tham gia trong php cng. V vy bit 7 gi nguyn tr
c.
Ta ch c th thay i bit 7 bng lnh LD R,A LD A,R v LD R,A truy cp
thanh ghi R sau khi
n c tng R thng c dng lm gi tr ngu nhin
trong chng trnh nhng d nhin n tht s khng ngu nhin.
Thm mt trng thi i vo chu k T1 Chu k c hoc ghi b nh
Thm trng thi i vo bt k chu k b nh no
Chu k nhp hoc xut (Input or Ouput Cycle)
During I/O operations a single wait state is automatically
inserted
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Chu k yu cu bus/ ghi nhnChu k yu cu/ghi nhn ngt
Two wait states are automatically added to this cycle
Chu k yu cu/ghi nhn bus vi NMI Chu k lm ti M1
Takes 4T to 6Ts Z80 includes built in circuitry for
refreshing
DRAM This simplifies the external interfacing
hardware DRAM consists of MOS transistors, which
store Information as capacitive charges; each cell needs to be
periodically refreshed
During T3 and T4 (when Z80 is performing internal ops), the low
order address is used to supply a 7-bit address for refresh
Tn hiu Wait
the Z80 samples the wait signal during T2 if low then Z80 adds
wait
states to extend the machine cycle
used to interface memories with slowresponse time
Slow memory is low cost
Ngt (Interrupt)
There are two types of interrupts: non mask-able (NMI)
Could not be masked Jump to 0066H of memory
mask-able(INT) Has 3 mode Can be set with the IM x Instruction
IM 0 sets Interrupt mode 0 IM 1 sets Interrupt mode 1 IM 2 sets
Interrupt mode 2
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Cc ch ngt Mode 0:
An 8 bit opcode is Fetched from Data BUS and executed The source
interrupt device must put 8 bit opcode at data
bus 8 bit opcode usually is RST p instructions
Mode 1: A jump is made to address 0038h No value is required at
data bus
Mode 2: A jump is made to address (register I 256 + value
from
interrupting device that puts at bus) I is high 8 bit of
interrupt vector Value is low 8 bit of interrupt vector
Chu k thot khi HALTiu kin thot: INT, NMI, RESET
nh th RESET
CPU Reset
2.6 CC PHNG PHP
NH A CH
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nh a ch trong Z80 Phn ln cc lnh Z80 lm vic vi d liu c lu tr
trong
cc thanh ghi CPU, b nh ngoi, hoc trong cc cng I/O. Z80c cch nh a
ch sau:
nh a ch tc thi (hng s 8 bit)
nh a ch tc thi m rng (hng s 16 bit)
nh a ch trc tip (a ch 8 bit)
nh a ch trc tip m rng (a ch 16 bit)
nh a ch trang 0 (c sa i)
nh a ch tng i
nh a ch theo ch s
nh a ch thanh ghi
nh a ch hiu ngm
nh a ch gin tip qua thanh ghi
nh a ch cho bit
nh a ch tc thi Byte theo sau m lnh l ton hng tht.
Th d ca loi lnh ny l np hng s vo thanh ghi tch ly.
Th d: LD A, 10H
nh a ch tc thi m rng
Hai byte theo sau m lnh l ton hng tht.
Th d ca loi lnh ny l np d liu 16 bit vo cp thanh ghi (th d
HL).Th d: LD HL, 8010H
nh a ch trc tip
Cung cp a ch 8 bit ca ton hng ngay sau m lnh
TD: IN A, (20H)
nh a ch [trc tip] m rng
Cung cp a ch 16 bit ca ton hng ngay sau m lnh
nh a ch trang 0 (c sa i)
Z80 c lnh CALL c bit 1 byte nhy n 8 v tr (ch bi nhm bit b5b4b3)
ca trang 0 ca b nh. Lnh ny c thc thi nh khi ng li, n t PC c gi tr a
ch tht trang 0. Gi tr ca lnh ny l cho php dng 1 byte ch a ch 16
bit.
Th d: RST pvi gi tr p c th l 00H, 08H, 10H, 18H, 20H, 28H, 30H,
hoc 38H.
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nh a ch tng i
S dng 1 byte d liu theo sau m lnh ch di so vi a ch lnh k v lnh
nh nhy n. di D ny s c du biu din theo s b 2 v a ch tht c tnh nh sau
(theo di D v a ch lnh hin ti A):
EA = D + A + 2
di D c th c gi tr t -128 n +127.
Th d: JR 10H
nh a ch theo ch s
Byte d liu theo m lnh l di D (s c du b 2) c cng vo vi thanh ghi
ch s (IX hoc IY) ch n nh d liu, ngha l EA = IX (hoc IY) + D. Loi
lnh ny c m lnh di 2 byte v trong m lnh c cc bit ch ra thanh ghi ch
s no c chn IX hoc IY.
Th d: LD A, (IX + 10H)
LD B, (IY + 20H)
nh a ch thanh ghi
Nhiu m lnh Z80 cha cc bit thng tin cho bit thanh ghi CPU no c s
dng trong lnh.
Th d: LD A, B
nh a ch hiu ngm
M lnh cho bit 1 hay nhiu thanh ghi CPU cha ton hng. Th d c mt s
lnh hiu ton hng thanh ghi tch ly.
nh a ch gin tip qua thanh ghi
Loi nh a ch ny cho bit cp thanh ghi 16 bit no (nh HL) c dng lm
con tr ch ti v tr nh.
Th d: LD A, (HL)
LD (HL), 10H
nh a ch cho bit
Z80 c nhiu lnh t bit, xa bit v kim tra bit. Cc lnh ny cho php bt
c v tr b nh no hoc thanh ghi CPU s c s dng cho cc php ton bit qua
mt trong 3 cch nh a ch trc (thanh ghi, gin tip qua thanh ghi v theo
ch s) v 3 bit trong m lnh s cho bit bit no trong 8 bit c x l.
Th d: BIT 3, A
SET 0, (HL)
RES 7, (IX + 10H)
Ch l c nhng lnh kt hp mt s cch a ch chung trong mt lnh.
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2.7 TP LNH
Tp lnh Z80 gm c 158 lnh, trong bao gm 78 lnh ca 8080. Cc lnh c
chia lm cc nhm chnh sau:
Np 8 bit v np 16 bit Hon i, chuyn khi v tm kim S hc v logic 8
bit S hc 16 bit S hc a dng v iu khin CPU Xoay v dch bit X l bit (Cc
php ton trn bit) Nhp v xut Nhy, r nhnh chng trnh Gi chng trnh v
quay v chng trnh gi.
Khi vit chng trnh thun tin thng ta dng hp ng m lnh c dng nh
trong th d sau:
Pseudo Codes
c th vit chng trnh d dng hn cc trnh hp ng thng cho thm cc tc v
gi (pseudo operation) hay cn gi l cc lnh gi nh: EQU, DEFB, DEFW,
DEFS, ORG, END, MACRO.
1. EQU (ngha l equate=bng; dng gn tr) Th d: Ni dung nh SUM = A +
10H
SUM: EQU 1900H ; SUM = 1900H
COUNT: EQU 10H
ADD A, COUNT ; ADD A, 10H
LD (SUM), A
2. DEFB (Define Byte = nh ngha Byte) v DEFW (Define Word =
nhngha Word)
Th d:CONST: EQU 52H
ADRS: EQU 1900H
TABLE: DEFW ADRSDEFB CONST
Khi cc vng nh (gi s a ch TABLE l 1951H) nh sau
3. DEFS (Define Storage = nh ngha vng lu tr)Th d: (Gi s lnh DEFS
10H a ch 1800H)
1800H DEFS 10H ; dnh 16 byte lu tr
1810H LD HL, 10H
1811H LD DE, 20H
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4. ORG (Origin = bt u; nh ngha a ch bt u) v END (kt thc chng
trnh)Th d:
ORG 100H ; Chng trnh bt u t 100H
START: LD A, 1FH ; bt u chng trnh
INC A
OUT (11H), A
END ; kt thc chng trnh
5. MACRO (nh ngha mt on chng trnh m trnh hp ng s t ng chn vo ton
b on chng trnh ny khi c tham chiu tn macro v bt u on macro bng
MACRO v kt thc bng ENDM)
Th d: REF: MACRO
LD H, (IX+1)
LD L, (IY+1)
INC IX
INC IY
ENDM
Th d: in cc s 0 vo cc nh c a ch t 8100H n 817FH.
ORG 8000H
LD HL, 8100H
LD A, 00H
LD C, 80H
LOOP: LD (HL), A
INC HL
DEC C
JP NZ, LOOP
HALT
END
Th d: Nhn 10 ln gi tr c ct trong cp thanh ghi HL.
MULT10: ADD HL, HL ; 2X HL
LD D, H ; (HL)=>(DE)
LD E, L
ADD HL, HL ; 4 x HL
ADD HL, HL ; 8 x HL
ADD HL, DE ; (8+2) x HL
RET
Th d: Chuyn chui d liu 737 byte v tr b nh DATA n v tr b nh
BUFFER, tc v ny c lp trnh nh sau
LD HL, DATA ; Ly a ch bt u ca DATA
LD DE, BUFFER ; Ly a ch bt u ca BUFFER
LD BC, 737 ; Chiu di ca chui k t
LDIR ; Chuyn chuiChuyn b nh ch ; bi HL vo nh c ch bi DE
; tng HL v DE ln 1
;Gim bt BC i 1, cho n khi BC= 0.
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