May-June 2010 May-June 2010 May-June 2010 Volume 14, Number 3 Volume 14, Number 3 Volume 14, Number 3 Defect Inspection Systems Defect Inspection Systems New Realities for TSV Processing New Realities for TSV Processing Advanced Chip-to-Wafer Bonding Advanced Chip-to-Wafer Bonding Die-attach and Flip-chip Bonders / Aligners Die-attach and Flip-chip Bonders / Aligners Defect Inspection Systems Defect Inspection Systems New Realities for TSV Processing New Realities for TSV Processing Advanced Chip-to-Wafer Bonding Advanced Chip-to-Wafer Bonding Die-attach and Flip-chip Bonders / Aligners Die-attach and Flip-chip Bonders / Aligners
44
Embed
Volume 14, Number 3 May-June 2010 - Chip Scale Revie 14, Number 3 May-June 2010 Defect Inspection Systems New Realities for TSV Processing ... Az Tech Direct Az Tech Direct. 4 Chip
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
May-June 2010May-June 2010May-June 2010Volume 14 Number 3Volume 14 Number 3Volume 14 Number 3
Defect Inspection SystemsDefect Inspection SystemsNew Realities for TSV ProcessingNew Realities for TSV ProcessingAdvanced Chip-to-Wafer BondingAdvanced Chip-to-Wafer BondingDie-attach and Flip-chip Bonders AlignersDie-attach and Flip-chip Bonders Aligners
Defect Inspection SystemsDefect Inspection SystemsNew Realities for TSV ProcessingNew Realities for TSV ProcessingAdvanced Chip-to-Wafer BondingAdvanced Chip-to-Wafer BondingDie-attach and Flip-chip Bonders AlignersDie-attach and Flip-chip Bonders Aligners
Copyright copy 2010 by Gene Selven amp Associates IncChip Scale Review (ISSN 1526-1344) is a registered trademark ofGene Selven amp Associates Inc All rights reserved
Subscriptions in the US are available without charge to qualifiedindividuals in the electronics industry Subscriptions outside of theUS (6 issues) by airmail are $85 per year to Canada or $95 peryear to other countries In the US subscriptions by first class mailare $75 per year
Chip Scale Review (ISSN 1526-1344) is published six times ayear with issues in January-February March-April May-June July-August September-October and November-December Periodicalpostage paid at San Jose Calif and additional offices
POSTMASTER Send address changes to Chip Scale Review
magazine PO Box 9522 San Jose CA 95157-0522
Printed in the United States
The International Magazine for Device and Wafer-levelTest Assembly and Packaging Addressing
High-density Interconnection of Microelectronic ICsincluding 3D packages MEMS MOEMS RF
Wireless Optoelectronic and Other Wafer-fabricated Devices for the 21st Century
he seasonal weather cycles of summer fall winter and spring are known
globally and can have significant impacts on business as related to product
purchasing cycles and the bottom line of your company Those of us in the electronics
industry are all too familiar with the impact of cycles on revenue and although not
as predictable as annual weather temperature our industry continues to cycle through
the highs lows (or very low as in 2009) and then back to the high with many
attempting to predict a cycle I can predict the seasons fall - leaves will fall from
the trees spring - flowers will appear to spring up from the ground But the
prediction of electronics cycles well I prefer to leave it to the experts
Interesting as well is a practice here in the US (excluding Hawaii and Arizona
although I am not sure why) of changing the time on a clock back 1 hour (falling
back) in the fall month of November and then ahead for 1 hour (springing ahead) in
the spring month of March to take full advantage of daylight hours termed Daylight
Savings Time The saying I have heard for years spring has sprung has even more
significance this year as I see a dynamic spring rebound and growth in the electronics
industry These are positive industry trends at a very critical time for many companies
that strategized and sacrificed throughout 2009 and are now poised for the opportunity
to expand their industry position and presence
The majority of companies in the electronics industry are now taking aggressive
strategic advantage of the current positive business trends and increases in revenue
to spring ahead There are several indicators that are tracked by the CSR staff showing
the positive continuing momentum The increased number of technical articles
submitted for publication can be linked to available corporate resources and new
product developments Approvals on corporate marketing funds have led the way to
increases in numbers of exhibitors and attendees at recent CSR-sponsored events
The funding has also increased advertising budgets as companies capitalize on
revenue growth with visibility on existing and new products and services
Companies positioned to spring ahead are leading those companies that are
somehow stuck in the cycle of falling behind specifically in the area of new product
development and technical marketing CSR sees the focus to expand the technical
scope of our annual CSRSMTA - IWLPC event with many areas of interest in
assembly and test including bonded wafers chip scale packages stacked die and
through-via technology and flip-chip andor wire-bonded configurations Review
the many updated and expanded supplier directories in CSR They list sources for
the following sockets and connectors subcontract assembly wafer bumping die
attachflip-chip bonders and defect inspection equipment with more to follow
through the year
The key objectives of CSR are to bring our loyal readers the latest in technical
innovations and business trends and to give global visibility to our advertisers
working together to continue to spring ahead in 2010
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Copyright copy 2010 by Gene Selven amp Associates IncChip Scale Review (ISSN 1526-1344) is a registered trademark ofGene Selven amp Associates Inc All rights reserved
Subscriptions in the US are available without charge to qualifiedindividuals in the electronics industry Subscriptions outside of theUS (6 issues) by airmail are $85 per year to Canada or $95 peryear to other countries In the US subscriptions by first class mailare $75 per year
Chip Scale Review (ISSN 1526-1344) is published six times ayear with issues in January-February March-April May-June July-August September-October and November-December Periodicalpostage paid at San Jose Calif and additional offices
POSTMASTER Send address changes to Chip Scale Review
magazine PO Box 9522 San Jose CA 95157-0522
Printed in the United States
The International Magazine for Device and Wafer-levelTest Assembly and Packaging Addressing
High-density Interconnection of Microelectronic ICsincluding 3D packages MEMS MOEMS RF
Wireless Optoelectronic and Other Wafer-fabricated Devices for the 21st Century
he seasonal weather cycles of summer fall winter and spring are known
globally and can have significant impacts on business as related to product
purchasing cycles and the bottom line of your company Those of us in the electronics
industry are all too familiar with the impact of cycles on revenue and although not
as predictable as annual weather temperature our industry continues to cycle through
the highs lows (or very low as in 2009) and then back to the high with many
attempting to predict a cycle I can predict the seasons fall - leaves will fall from
the trees spring - flowers will appear to spring up from the ground But the
prediction of electronics cycles well I prefer to leave it to the experts
Interesting as well is a practice here in the US (excluding Hawaii and Arizona
although I am not sure why) of changing the time on a clock back 1 hour (falling
back) in the fall month of November and then ahead for 1 hour (springing ahead) in
the spring month of March to take full advantage of daylight hours termed Daylight
Savings Time The saying I have heard for years spring has sprung has even more
significance this year as I see a dynamic spring rebound and growth in the electronics
industry These are positive industry trends at a very critical time for many companies
that strategized and sacrificed throughout 2009 and are now poised for the opportunity
to expand their industry position and presence
The majority of companies in the electronics industry are now taking aggressive
strategic advantage of the current positive business trends and increases in revenue
to spring ahead There are several indicators that are tracked by the CSR staff showing
the positive continuing momentum The increased number of technical articles
submitted for publication can be linked to available corporate resources and new
product developments Approvals on corporate marketing funds have led the way to
increases in numbers of exhibitors and attendees at recent CSR-sponsored events
The funding has also increased advertising budgets as companies capitalize on
revenue growth with visibility on existing and new products and services
Companies positioned to spring ahead are leading those companies that are
somehow stuck in the cycle of falling behind specifically in the area of new product
development and technical marketing CSR sees the focus to expand the technical
scope of our annual CSRSMTA - IWLPC event with many areas of interest in
assembly and test including bonded wafers chip scale packages stacked die and
through-via technology and flip-chip andor wire-bonded configurations Review
the many updated and expanded supplier directories in CSR They list sources for
the following sockets and connectors subcontract assembly wafer bumping die
attachflip-chip bonders and defect inspection equipment with more to follow
through the year
The key objectives of CSR are to bring our loyal readers the latest in technical
innovations and business trends and to give global visibility to our advertisers
working together to continue to spring ahead in 2010
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Copyright copy 2010 by Gene Selven amp Associates IncChip Scale Review (ISSN 1526-1344) is a registered trademark ofGene Selven amp Associates Inc All rights reserved
Subscriptions in the US are available without charge to qualifiedindividuals in the electronics industry Subscriptions outside of theUS (6 issues) by airmail are $85 per year to Canada or $95 peryear to other countries In the US subscriptions by first class mailare $75 per year
Chip Scale Review (ISSN 1526-1344) is published six times ayear with issues in January-February March-April May-June July-August September-October and November-December Periodicalpostage paid at San Jose Calif and additional offices
POSTMASTER Send address changes to Chip Scale Review
magazine PO Box 9522 San Jose CA 95157-0522
Printed in the United States
The International Magazine for Device and Wafer-levelTest Assembly and Packaging Addressing
High-density Interconnection of Microelectronic ICsincluding 3D packages MEMS MOEMS RF
Wireless Optoelectronic and Other Wafer-fabricated Devices for the 21st Century
he seasonal weather cycles of summer fall winter and spring are known
globally and can have significant impacts on business as related to product
purchasing cycles and the bottom line of your company Those of us in the electronics
industry are all too familiar with the impact of cycles on revenue and although not
as predictable as annual weather temperature our industry continues to cycle through
the highs lows (or very low as in 2009) and then back to the high with many
attempting to predict a cycle I can predict the seasons fall - leaves will fall from
the trees spring - flowers will appear to spring up from the ground But the
prediction of electronics cycles well I prefer to leave it to the experts
Interesting as well is a practice here in the US (excluding Hawaii and Arizona
although I am not sure why) of changing the time on a clock back 1 hour (falling
back) in the fall month of November and then ahead for 1 hour (springing ahead) in
the spring month of March to take full advantage of daylight hours termed Daylight
Savings Time The saying I have heard for years spring has sprung has even more
significance this year as I see a dynamic spring rebound and growth in the electronics
industry These are positive industry trends at a very critical time for many companies
that strategized and sacrificed throughout 2009 and are now poised for the opportunity
to expand their industry position and presence
The majority of companies in the electronics industry are now taking aggressive
strategic advantage of the current positive business trends and increases in revenue
to spring ahead There are several indicators that are tracked by the CSR staff showing
the positive continuing momentum The increased number of technical articles
submitted for publication can be linked to available corporate resources and new
product developments Approvals on corporate marketing funds have led the way to
increases in numbers of exhibitors and attendees at recent CSR-sponsored events
The funding has also increased advertising budgets as companies capitalize on
revenue growth with visibility on existing and new products and services
Companies positioned to spring ahead are leading those companies that are
somehow stuck in the cycle of falling behind specifically in the area of new product
development and technical marketing CSR sees the focus to expand the technical
scope of our annual CSRSMTA - IWLPC event with many areas of interest in
assembly and test including bonded wafers chip scale packages stacked die and
through-via technology and flip-chip andor wire-bonded configurations Review
the many updated and expanded supplier directories in CSR They list sources for
the following sockets and connectors subcontract assembly wafer bumping die
attachflip-chip bonders and defect inspection equipment with more to follow
through the year
The key objectives of CSR are to bring our loyal readers the latest in technical
innovations and business trends and to give global visibility to our advertisers
working together to continue to spring ahead in 2010
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Copyright copy 2010 by Gene Selven amp Associates IncChip Scale Review (ISSN 1526-1344) is a registered trademark ofGene Selven amp Associates Inc All rights reserved
Subscriptions in the US are available without charge to qualifiedindividuals in the electronics industry Subscriptions outside of theUS (6 issues) by airmail are $85 per year to Canada or $95 peryear to other countries In the US subscriptions by first class mailare $75 per year
Chip Scale Review (ISSN 1526-1344) is published six times ayear with issues in January-February March-April May-June July-August September-October and November-December Periodicalpostage paid at San Jose Calif and additional offices
POSTMASTER Send address changes to Chip Scale Review
magazine PO Box 9522 San Jose CA 95157-0522
Printed in the United States
The International Magazine for Device and Wafer-levelTest Assembly and Packaging Addressing
High-density Interconnection of Microelectronic ICsincluding 3D packages MEMS MOEMS RF
Wireless Optoelectronic and Other Wafer-fabricated Devices for the 21st Century
he seasonal weather cycles of summer fall winter and spring are known
globally and can have significant impacts on business as related to product
purchasing cycles and the bottom line of your company Those of us in the electronics
industry are all too familiar with the impact of cycles on revenue and although not
as predictable as annual weather temperature our industry continues to cycle through
the highs lows (or very low as in 2009) and then back to the high with many
attempting to predict a cycle I can predict the seasons fall - leaves will fall from
the trees spring - flowers will appear to spring up from the ground But the
prediction of electronics cycles well I prefer to leave it to the experts
Interesting as well is a practice here in the US (excluding Hawaii and Arizona
although I am not sure why) of changing the time on a clock back 1 hour (falling
back) in the fall month of November and then ahead for 1 hour (springing ahead) in
the spring month of March to take full advantage of daylight hours termed Daylight
Savings Time The saying I have heard for years spring has sprung has even more
significance this year as I see a dynamic spring rebound and growth in the electronics
industry These are positive industry trends at a very critical time for many companies
that strategized and sacrificed throughout 2009 and are now poised for the opportunity
to expand their industry position and presence
The majority of companies in the electronics industry are now taking aggressive
strategic advantage of the current positive business trends and increases in revenue
to spring ahead There are several indicators that are tracked by the CSR staff showing
the positive continuing momentum The increased number of technical articles
submitted for publication can be linked to available corporate resources and new
product developments Approvals on corporate marketing funds have led the way to
increases in numbers of exhibitors and attendees at recent CSR-sponsored events
The funding has also increased advertising budgets as companies capitalize on
revenue growth with visibility on existing and new products and services
Companies positioned to spring ahead are leading those companies that are
somehow stuck in the cycle of falling behind specifically in the area of new product
development and technical marketing CSR sees the focus to expand the technical
scope of our annual CSRSMTA - IWLPC event with many areas of interest in
assembly and test including bonded wafers chip scale packages stacked die and
through-via technology and flip-chip andor wire-bonded configurations Review
the many updated and expanded supplier directories in CSR They list sources for
the following sockets and connectors subcontract assembly wafer bumping die
attachflip-chip bonders and defect inspection equipment with more to follow
through the year
The key objectives of CSR are to bring our loyal readers the latest in technical
innovations and business trends and to give global visibility to our advertisers
working together to continue to spring ahead in 2010
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Copyright copy 2010 by Gene Selven amp Associates IncChip Scale Review (ISSN 1526-1344) is a registered trademark ofGene Selven amp Associates Inc All rights reserved
Subscriptions in the US are available without charge to qualifiedindividuals in the electronics industry Subscriptions outside of theUS (6 issues) by airmail are $85 per year to Canada or $95 peryear to other countries In the US subscriptions by first class mailare $75 per year
Chip Scale Review (ISSN 1526-1344) is published six times ayear with issues in January-February March-April May-June July-August September-October and November-December Periodicalpostage paid at San Jose Calif and additional offices
POSTMASTER Send address changes to Chip Scale Review
magazine PO Box 9522 San Jose CA 95157-0522
Printed in the United States
The International Magazine for Device and Wafer-levelTest Assembly and Packaging Addressing
High-density Interconnection of Microelectronic ICsincluding 3D packages MEMS MOEMS RF
Wireless Optoelectronic and Other Wafer-fabricated Devices for the 21st Century
he seasonal weather cycles of summer fall winter and spring are known
globally and can have significant impacts on business as related to product
purchasing cycles and the bottom line of your company Those of us in the electronics
industry are all too familiar with the impact of cycles on revenue and although not
as predictable as annual weather temperature our industry continues to cycle through
the highs lows (or very low as in 2009) and then back to the high with many
attempting to predict a cycle I can predict the seasons fall - leaves will fall from
the trees spring - flowers will appear to spring up from the ground But the
prediction of electronics cycles well I prefer to leave it to the experts
Interesting as well is a practice here in the US (excluding Hawaii and Arizona
although I am not sure why) of changing the time on a clock back 1 hour (falling
back) in the fall month of November and then ahead for 1 hour (springing ahead) in
the spring month of March to take full advantage of daylight hours termed Daylight
Savings Time The saying I have heard for years spring has sprung has even more
significance this year as I see a dynamic spring rebound and growth in the electronics
industry These are positive industry trends at a very critical time for many companies
that strategized and sacrificed throughout 2009 and are now poised for the opportunity
to expand their industry position and presence
The majority of companies in the electronics industry are now taking aggressive
strategic advantage of the current positive business trends and increases in revenue
to spring ahead There are several indicators that are tracked by the CSR staff showing
the positive continuing momentum The increased number of technical articles
submitted for publication can be linked to available corporate resources and new
product developments Approvals on corporate marketing funds have led the way to
increases in numbers of exhibitors and attendees at recent CSR-sponsored events
The funding has also increased advertising budgets as companies capitalize on
revenue growth with visibility on existing and new products and services
Companies positioned to spring ahead are leading those companies that are
somehow stuck in the cycle of falling behind specifically in the area of new product
development and technical marketing CSR sees the focus to expand the technical
scope of our annual CSRSMTA - IWLPC event with many areas of interest in
assembly and test including bonded wafers chip scale packages stacked die and
through-via technology and flip-chip andor wire-bonded configurations Review
the many updated and expanded supplier directories in CSR They list sources for
the following sockets and connectors subcontract assembly wafer bumping die
attachflip-chip bonders and defect inspection equipment with more to follow
through the year
The key objectives of CSR are to bring our loyal readers the latest in technical
innovations and business trends and to give global visibility to our advertisers
working together to continue to spring ahead in 2010
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Endicott Honors EmployeesAt an awards dinner and ceremony held
Friday April 16th at The McKinley inEndicott NY Endicott InterconnectTechnologies Inc (EI) honored 36employees for patent applications filed USpatents issued and trade secrets received in2009 ldquoI am very proud of these individualswhose bold invention creativity andtechnology innovation has contributed to thesuccess of EI ensuring our technical vitalityand allowing us to compete aggressively inthe open marketrdquo commented JamesMcNamara President and CEO at EI ldquoThisseventh annual ceremony signifies howfirmly and decisively EIrsquos corporateleadership encourages innovation as thecorner stone for the future of the companyrsquosprogressionrdquo affirmed Voya MarkovichSenior VP of RampD and CTO at EI ldquoI amhonored to be working with this team ofinventorsrdquo he continued EI has 145 filedapplications and has been awarded 103 USpatents to date including 25 new patentsissued and 7 trade secrets in 2009[wwwendicottinterconnectcom]
Even NASA Gets DupedIn 2009 a NASA probe project was
delayed nine months and exceeded itsbudget by more than 20 percent partlybecause of a counterfeit part According toBrandWatch Technologies a developer andimplementer of brand security and productauthentication solutions the problemextends beyond NASArsquos dollars andtimelines risking personal safetydiminishing confidence in US aerospaceprograms and impacting the businesses oflegitimate component manufacturers ldquoTheeffort it takes to get astronauts one stepfurther into space is immense so the factthat counterfeiters have penetrated our spaceexploration and defense programs is a shockand certainly raises concernsrdquo said PhilHuff chief executive officer of BrandWatchTechnologies ldquoUnfortunately globalizationhas made it more difficult than ever tocontrol the millions of parts and sourceswithin supply chains including those thatsupport NASA The only way to truly protectlegitimate companies and the integrity oftheir parts and enforce NASArsquos compliance
and safety standards is through proactiveproduct authenticationrdquo In response to itscounterfeit problems NASA adopted SAEAS5553 an aerospace parts standard issuedin 2009 [wwwbrandwatchtechcom]
Imec Successfully Concludes 2009At a meeting on April 30 2010 the
imec board announced its results for 2009Despite the severe economic downturnthey reported that 2009 was a satisfyingyear Using EUV lithography imec claimsfabrication of the worldrsquos first functional22nm SRAM cell an extremely smallmemory cell representing a huge technicaland logistical challenge They developeda micro-nail chip enabling intimatecontact with neurons The chip canstimulate neurons and read their signalsIt will be used in the NeuroelectronicsResearch Flanders initiative to unravel thehuman brain NERF was founded byimec VIB and KULeuven and issupported by the Flemish Government2009 was also marked by the successfulkick-off of imecrsquos solar cell researchprogram endorsed with collaborationswith important players such as SchottSolar Total GDF Suez and Photovoltech
Said Luc Van den hove President andCEO at imec ldquoThis is our way to preparefor the future to tackle the technological
and the economicalchal lenges aheadB e c a u s e w e a r econvinced that openinnovation and globalcollaborations are thekey to progress rdquo[wwwimecbe]
IWLPC 2010 Gains Momentum-Three Gold Sponsors
The International Wafer LevelPackaging Conference is delighted toannounce the 2010 gold sponsors Gold
sponsors have aspecial relationshipwith the conferencea n d g e t t h e i rcompany logoswith links put onthe conference web
site front page The 2010 sponsors areAmkor Technology Pac Tech USA andNEXX Systems
Amkor is one ofthe worldrsquos largest
providers of contract semiconductorassembly and test services and a long-time supporter and sponsor of theIWLPC conference
P a c Te c hhas also been a
sponsor in the past and IWLPC is pleasedto have them again Pac Tech is a providerof advanced wafer bumping packagingand solder-ball placement equipment andcontract services
Also a formersponsor NEXXSystems Inc is a
semiconductor equipment companyspecializing in wafer level packagingprocessing for the semiconductorpackaging industry
IWLPC attracts a large internationalattendance If your company is interestedin sponsorship or exhibit opportunitiesplease visit wwwiwlpccom or contactLeslee Johns [lesleesmtaorg] TheIWLPC is sponsored jointly by the SMTA[wwwsmtaorg] and Chip Scale Reviewmagazine [wwwchipscalereviewcom]
3D Process AdvancesExperts from SEMATECHrsquos 3D
interconnect program based at theCollege of Nanoscale Science andE n g i n e e r i n g rsquos ( C N S E ) A l b a n yNanoTech Complex outlined newdevelopments in wafer bonding copperremoval and wafer thinning at the 2010Materials Research Society (MRS)Spring Meeting on April 5-9 in SanFrancisco CA Process advances aimedat improving 3D performance include
A practical approach to copperoverburden removal by chemicalmechanical polishing (CMP) usinghigh removal rate slurry screeningand achieving good planarization
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
results with low polish defects at arate suitable for emerging 3D TSVcopper applications
The process development andassociated metrology necessary inthinning bonded 300mm TSV and non-TSV bonded wafers leaving a defect-free surface which meets therequirements for subsequent processing
An array of metrology techniques usedin characterizing a manufacturablewafer bond process to deliver a voidand dendrite-free bond for handlewafers
To accelerate progress the programrsquosengineers have been working jointly withchipmakers equipment and materialssuppliers and assembly and packagingservice companies from around the worldon early development challengesincluding cost modeling technology optionnarrowing and technology developmentand benchmarking [wwwsematechorg ]
STATS ChipPAC Transitions to 300mmClaiming to be the first in the
semiconductor industry to introduce300mm embedded Wafer-Level Ball GridArray (eWLB) wafer manufacturingc a p a b i l i t i e s S TATS Ch ipPACheadquartered in Singapore recentlyannounced the expansion of its eWLBtechnology to reconstituted 300mm wafersBy adding capacity through 300mm wafermanufacturing STATS ChipPAC expectsits customers to benefit from the cost andproductivity advantages of eWLBtechnology on the larger 300mm format
ldquo T h e 3 0 0 m me W L B w a f e rmanufacturingaccomplishmentis a milestone forthe industry and ist h e r e s u l t o fleveraging thestrengths of STATSChipPAC and itsmanufacturingpartner InfineonTechnologiesrdquos a i d Dr H a nB y u n g J o o n
Executive Vice President and ChiefTechnology Officer STATS ChipPAC Thecompany continues its development workon the eWLB evolution to enable larger
package sizes higher InputOutput (IO)density and 3D Package-on-Package (PoP)solutions to address a wider applicationmarket [wwwstatschippaccom]
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
OwnershipAs geometries get smaller new approaches hold promiseBy Alfred Sigl Garrett Oakes and Paul Kettner [EV Group St FlorianInn Austria]
and Christian Pichler and Christoph Scheiring [Datacon Technology GmbH Radfeld Austria]
he shrinkage and integrationof various functionalities intoelectrical devices such as
computers or mobile phones has leadto an ongoing need for shrinkage of theintegrated semiconductor units as wellOne possibility for manufacturinghighly integrated electrical devices isthe System-in-Package (SiP) approachwhere various semiconductor chips withdifferent functionalities are stacked andelectrically connected to each other Theshrinkage of features for exampletransistor size die thickness height ofthe die stack and the dimension andshape of interconnects between the diceaffects all aspects of the SiP Smallerdie interconnects can cause difficultiesto widely used joint technologies suchas solder bumping because of the smallamount of solder involved to the pointthat the assembly yields drop and thereliability of the interconnects decrease
The Advanced Chip-to-Wafer(AC2W) bonding approach is a two-step process for stacking and bondingdice on wafers All dice are alignedand tacked on the wafer first and inthe second step these dice are bondedsimultaneously and permanently tothe wafer This process allows the useof force while bonding the dice on thewafer In this way low solder volumeinterconnects can be formed at thewafer level with high assembly yieldand throughput The cost of ownership(CoO) combined with the throughputof the AC2W process can be an orderof magnitude smaller than forcomparable chip-to-wafer bondingprocesses While there are some issuesconcerning die joint shrinkage AC2Woffers a low cost chip-to-wafer
bonding process for high volumeproduction
IntroductionCollapsible solder-bump interconnects
are widely used for flip-chip connectionsH o w e v e r a s s t r u c t u r e s i z e o nsemiconductor devices decreases tofollow Moorersquos Law the dimensions ofthe interconnects also have to shrink Inturn the solder volume at the individualinterconnects must decrease Amongstother influences the solder alsofunctions as a compensator for heightvariations of the substrates andfunctional layers or variations due towarp and bow Decreasing the soldervolume decreases the ability tocompensate for height variation andonly with the application of force duringb o n d i n g c a n s u ff i c i e n t l y h i g hmanufacturing yield be guaranteed
During the formation of solderinterconnects the selected metalsdiffuse into each other and usuallyconvert to intermetallic compounds(IMC) at the interface In most solderconnections utilized to date thisundesirable effect occurs with aknown growth rate that depends ontemperature and metallurg y Thethickness of this layer depends onphysics and for low solder volumein t e r connec t s (Figure 1) IMCthickness is nearly that of the jointt h i c k n e s s T h e r e f o r e a s t h econnection size shrinks the ratio of
IMC to solder r ises (Figure 2) Furthermore the growth of IMC doesnot stop after the heat cycle forforming the connection At roomtemperature the conversion continuesalbeit with a very long time constantdue to its thermodynamic instabilityOne possible solution is to bring theconnection into a thermodynamicallystable state which means convertingthe metals completely to IMC andusing them directly as the material forthe interconnection In this case thevolumes of the metal components areadjusted to each other in such a waythat all material can convert to IMCwhile bonding This approach issimilar to the well-known eutecticbonding Additionally the density ofthe IMC is usually higher than thed e n s i t i e s o f t h e p a r e n t m e t a lcomponen t s l e ad ing t o vo lumes h r i n k a g e w h i l e f o r m i n g t h econnection To guarantee a goodcontact and allow a sufficiently highmetal-dif fusion rate application offorce is necessary for bonding
A more sophisticated approach formaking small metal interconnects isthermocompression bonding whichis well known from wafer-to-waferbonding It is well suited for makingv e r y s m a l l i n t e r c o n n e c t s w i t hdimens ions in the s ingle d ig i tmicrometer range In this approachforce is required during bonding to
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
overcome the microroughness andbring the two metal surfaces proximalso that the dif fusion of the metal atomscan occur to form a metal bond
Several major semiconductormanufacturers have evaluated oremployed these types of interconnectformations for volume production1-7 Inall approaches for small interconnectsthe application of force is necessary toform a proper bond For the applicationof force for chip-to-wafer bonding thesophisticated AC2W bonding processdesigned specifically for high volumeproduction is available
Advanced Chip-to-Wafer BondingThe AC2W bonding process is a
process flow for chip-to-wafer bondingspecifically designed for theapplication of force while forming thebond at a throughput appropriate forvolume production9 The concept ofseparately aligning substrates and thenbonding them to each other is wellknown and widely used for wafer-to-
wafer bonding In the AC2W bondingprocess the same concept is adapted tochip-to-wafer bonding AC2W is a two-step process (Figure 3) First all chipsare aligned and prebonded to the waferSecond all chips are bonded in parallelsimultaneously and permanently to thewafer
In the first step of the AC2Wbonding process the dice are alignedto the wafer and then the alignment isfixed by prebonding the chips to thewafer Three different methods arec o m m o n l y a v a i l a b l e f o r t h eprebonding each having a distinctapplication
1) Using a prebonding adhesive 9 aprebonding adhesive for examplebibenzyl can be used This materialhas the properties that it is a solidbelow 48deg C a liquid above that
temperature and it evaporates withoutresidues in the temperature range of250 - 280deg C The dice and theadhesive are heated above 53deg C foraligning applying the adhesive andplacing the dice on the wafer Then thestack is cooled to solidify the adhesivethus fixing the die The adhesivecompletely evaporates during thepermanent bonding step
2) Using a preapplied underfill10 preapplied underfill can also be utilizedfor die-to-substrate prebonding Thereare various methods to apply underfilleither to the target wafer or to the diceprior to bonding During prebondingthe underfill has to have either on itsown or via special treatment enoughtack to fix the dice to the wafer andsecure the alignment The usage ofpreapplied underfill for prebonding hasa large advantage in that underfilltypically has to be applied at stackedsubstrates Therefore it covers twofunctions simultaneously savingadditional cost
3) Using ultrasonics 11 ultrasonicprebonding can be used for metals withlow melting points In this case a fragileconnection between the surfaces of themetal pads is formed by ultrasonicenergy This method is preferable forMEMS fabrication because no organicmaterials are involved Furthermore noconsumables are used
All of these methods fix the dice andthereby the alignment of the dice whilethe populated wafer is transported froma flip-chip bonder to a permanentbonder (Figure 7) All methods can beperformed at high speed which meansthat the flip-chip bonder can operatein a production mode in the range ofthe highest specified throughput for theequipment The permanent bonderrequires the following features for the
chip-to-wafer bonding (1) a closedchamber for vacuum encapsulation orprocess gases (2) a pressure plate andforce application system (3) a point ofapplication of force movement systemand (4) a compliant layer Thereforeit enables the permanent bond processat high temperature (up to 550deg C)with application of force and withvacuum (down to 1x10 -5mbar) orprocess gases
1) The closed chamber for vacuumencapsulation or process gases allowshaving a specific controlled atmospherewhile the bond is formed In that waygases or vacuum can be encapsulatedin semiconductor devices such aspressure sensors or bonding-improvinggases can by used
2) The pressure plate allows theapplication of force simultaneously onall dice on the wafer during the wholeprocess of forming the bond as this isnecessary to have a high process yieldfor small interconnects
3) The point of application of force
movement allows the usage of KnownGood Dice (KGDs) only which is alarge cost saving In KGD bonding thetarget wafer is partially populatedTested chips are only placed onyielding dice on the target wafers Toguarantee the same force on each diethe point of application of force has tobe at the center of gravity of the diepopulation (Figure 4) and is achievedby the point of force applicationmovement system
4) The compliant layer compensatesfor thickness variations of the dicewhich occur when the dice originatefrom dif ferent source wafers Thevariations are usually in the range oftens of micrometers or less With thecompliant layer yield issues caused bysmall interconnects can be overcomeas shown in Figure 5
While the permanent bondingprocess force is applied to the dice onthe wafer the stack is heated up to the
Figure 4 The point of application of force has tobe at the center of gravity of the die population
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
bonding temperature under vacuum orcertain process gases and the bond isformed for all dice simultaneously Atthis time the prebonding adhesiveeither evaporates or cures dependingon the prebonding method that is usedThe bonded stack is then cooled downand can be unloaded from the chamber
The AC2W bonding concept is a newconcept compared to the well-knownControlled Collapse Chip Connection(C4) for flip chip wafer-to-wafer
bonding and chip-to-wafer bonding byonly using a flip-chip bonder All ofthese concepts have their advantagesbut there are application spaces wherethe AC2W bonding approach is thebest suited and in terms of cost ofownership the cheapest process
Comparison of C4 to AC2W ProcessThe most popular process for making
collapsible interconnections is theControlled Collapse Chip Connection(C4) process8 It mainly consists of foursteps (Figure 6 top) (1) applicationof under-bump metallization (UBM)(2) application of solder with ballforming reflow (3) fluxing and placingthe chip on the substrate and (4)assembly reflow The process flow ofAC2W is quite similar to C4 (Figure
6 bottom) (1) application of under-bump metallization (2) application ofsolder without ball forming reflow (3)
Figure 6 C4 and AC2W (for Cu-Sn-Cu eutecticbond) process flow comparison
of stacked
dies
0
1
2
3
4
5
6
7
8
W2W yield
90
81
73
66
59
53
48
43
39
AC2W
yield
90
90
90
90
90
90
90
90
90
Table 1 Yield advantage of AC2W over W2W
aligning and prebonding on substrateby prebonding adhesive (4) assemblyreflow with force
In principle the concept of the twoprocess flows are the same In bothcases the chips are fixed by anadhesive for the last step (flux for C4prebonding adhesive for AC2W) Thedifference is when and how thealignment is performed In the C4process the chips undergo a self-alignment when the solder meltsduring the final assembly reflow Atthat time the surface tension of thesolder pulls the chips to the correctposition This concept only workswhen the amount of solder is largeenough so that the droplet of solder hasa high enough surface tension to movethe chip For small solder volumeinterconnects the floating resistanceis too high and this concept fails sincethe process yield drops rapidly due toopen contacts
In the AC2W process the chip-to-wafer alignment is already completed
during the placement of the chip on thewafer and secured by the prebondingadhesive and by the application of forceduring the final bonding step Thealignment is completely done by theflip-chip bonder and not dependant onthe properties of the interconnectionmaterial Therefore higher accuracieswith smaller interconnects can beachieved as compared to the C4process and open contacts are avoidedby the application of force duringbonding Therefore the C4 process iswell suited and offers high throughputfor larger size solder interconnects butfor smaller size solder interconnectsthe AC2W process is favored
Comparison of AC2W to Wafer-to-Wafer Bonding Process
Wafer-to-wafer (W2W) bonding is awell known and widely used processapproach for connecting and stackingdevices at the wafer level The mainadvantage of W2W bonding is the veryhigh achievable alignment accuracy inthe submicrometer range with highthroughput
For flip-chip bonders thethroughput depends strongly on the
t a r g e t e d a l i g n m e n t a c c u r a c yTherefore the throughput in the firststep of the AC2W drops whenaccuracies below two micrometers aretargeted while for W2W it stays nearlyconstant for all required accuracies Inthe second step of the AC2W bondinghigh throughput is achievable since itis very comparable to W2W bondingas there are multiple dice bonded to thetarget wafer at once Also the processtime and process recipe are quitesimilar
In contrast to W2W in AC2Wbonding only known good dice areused This offers a large cost savingsWhen stacking multiple dice the W2Wyield can decrease dramatically (Table
1) Here a hypothetical yield of 90 of the devices on the processed wafersis taken into account It is assumed thatall stacked wafers have the same yieldThe yields for all other yield detractorssuch as bonding testing and chipyield are assumed to be a 100 sincethey are usually very high For W2W
the yield decreases exponentially whilefor AC2W it stays constant at thestarting level of 90
When dice with different sizes haveto be stacked on each other additionallosses occur in the W2W approachbecause the patterns on the differentwafers have to match regardless of thechip size on the wafer For exampleassume that two dice are to be stackedand one die is a quarter of the size ofthe other and the two source waferscost the same to process Whenstacking the devices with the W2Wapproach three-quarters of one waferhas to be without devices since the diceon the both wafers have to be at a
Figure 5 Open contacts can occur by (a) bow or
warpage (b) unevenness of the substrates (c)
height variation of the interconnects (top) Theseissues can be overcome by uniform application of
force on the backside of the die by the usage of acompliant layer while bonding (bottom)
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
certain position to mate with each other while bondingTherefore on one wafer only one-quarter of the wafer area iscovered with chips When looking at the process cost the waferscost the same so each are 50 of total costs In the W2Wprocess 75 of the wafer area from one wafer is unused andpossible dice are lost that would be used in the AC2W processIn this example the costs for using the W2W process ascompared to the AC2W process are 37 higher caused by thechoice of bonding process
The W2W approach is the method of choice for applicationswhere alignment accuracy in the submicrometer range isnecessary AC2W bonding offers an equivalent throughputsimultaneously with higher yield and is therefore cheaper forstacking multiple or different sized dice
Comparison of Flip-Chip Bonder Only to AC2W ProcessThe flip-chip bonder only process flow does both the alignment
and the bonding steps directly after each other for each individualdie so all the dice are bonded in serial to the wafer Dieinterconnects (eutectic bond thermocompression bond) form bydiffusion processes that need a certain amount of time usuallyin the range of tens of seconds In the flip-chip bonder onlyprocess this time is needed to bond each and every individualdie and therefore lowers the throughput dramatically In contrastfor the first step of the AC2W process the flip-chip bonder canoperate with very high throughput The time needed for diffusion
contributes to the second step of the AC2W process but since alldice are bonded in parallel the overall time contribution in therange of tens of seconds for all the dice is negligible
For better understanding here is an example Assume that2641 chips with a size of 5x5mm2 are bonded to a 300mmwafer The type of interconnection is CuSnAg which usuallyrequires 20 seconds for bonding The alignment time of a flipchip is about 05 seconds This means that in the flip-chip bonderonly process each individual die needs (20 seconds + 05 seconds =)205 seconds to be bonded to the wafer which results in athroughput of about 175 dice per hour or 0066 wafers per hourIn the AC2W process the throughput of the two steps has to beevaluated separately During the first AC2W step the throughputis determined by the flip-chip bonder alignment and placementtime (05 seconds) and therefore about 7200 dice per hour or273 wafers per hour can be processed The throughput of thesecond step is mainly determined by equipment restrictions andis in the range of about 20 minutes per wafer or three wafersper hour The 20 seconds diffusion time to form the interconnectioncontributed at the second bonding step has therefore no negativeeffect on throughput of the AC2W process
Besides the throughput there are several other variables thataffect the cost of ownership of the AC2W process such as die sizewafer size bonding process and alignment accuracy For the givenexample the cost of ownership (CoO) was calculated and it showsa cost advantage of one order of magnitude (Figure 8)
Comparison of Capillary to Preapplied Underfill UsageFor nearly every manufactured die stack there is a filler
material called the underfill applied between a die and the target
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
substrate for mechanical stabilization ofthe electrical interconnection Theunderfill is required to achieve asufficiently long lifetime of the deviceas the device has to withstand detractorsto longevity such as thermal cycleshumidity and corrosion
Available underfill materials can bedivided into two main categoriescapillary underfill and preappliedunderfill Capillary underfill is the mostw ide l y u s ed and a we l l - knowntechnology in various fields of stackingapplications like die to wafer die to leadframe and many other packing methods
The underfill is applied to the die stackafter bonding by needle or dropletdispensing The underfill may be appliedto the package at one edge a few edgesor in more complex patterns The liquidunderfill material then wicks into the gapbetween the dice due to the capillaryeffect which means it maximizes thewetted area to minimize its energyAdditionally there are some ceramicfiller particles with a diameter down inthe single digit micrometer range mixedinto the polymer base material to lowerthe coefficient of thermal expansion(CTE) to a value near the CTE of thesemiconductor material The filling ofthe die gap with capillary underfill is aseparate process that occurs after thestacking Therefore it can be used in alldie-to-substrate bonding approaches andis state of the art of die stacking with theC4 process Usage of capillary underfillfor die gaps below thirty micrometers inhigh volume production is economicallyunattractive because the filling time riseswith decreasing gap height and a void-free filling cannot be guaranteed
The usage of preapplied underfill isan alternative method to apply underfillmaterial to these kinds of small die gaps
Therefore this underfill technique allowsfor smaller overall stack height with acost structure appropriate for highvolume production As the namesuggests preapplied underfill is appliedbefore the bonding of the dice either onthe die or onto the target substrate It maybe a liquid paste or a foil depending onthe supplier and application For solderinterconnects the preapplied underfillhas to have some special properties
1) The preapplied underfill shouldallow prebonding of the die to the targetsubstrate This can be by an inherentlevel of tack or via a bistage propertywhich means that the viscosity islowered and thereby the tackiness isincreased for prebonding by heat
2) The preapplied underfill has toallow for void-free prebonding andpermanent bonding which means thatit should not demonstrate any outgasingor shrinkage during heating or finalcuring
3) The preapplied underfill has toallow for proper solder bond formation
Because the bumps are usually not infull contact after prebonding it mustbe possible to squeeze out the underfillbetween the bumps while permanentbonding takes place Usually underfillmaterial is a bistage material It is verystringy at room temperature Uponheating the viscosity decreases Thisallows the underfill to squeeze outAbove a certain temperature thematerial migrates to its final stage andit cures into a solid material
4) The preapplied underfill has tohave fluxing properties to guaranteesufficient wetting of the solder to thebumps These fluxing componentsshould not influence the mechanical orelectrical properties of the finalpackage since they cannot be removedfrom the die stack
5) The preapplied underfill has tocure without shrinking since thatwould lead to stress on the dice or voidsin the stack The underfill is usuallycured by heat
6) The preapplied underfill shouldhave a temperature behavior of itsbistage properties which fits to theneeded final metal bond temperatureand the temperature gradient
These are very difficult restrictionswhich demand very special materials forthis application After applying thepreapplied underfill the die can bebonded to the target substrate by C4 flip-chip bonder only or by the AC2Wprocess For the C4 and AC2W processa placing or prebonding of the die to thetarget substrate is necessary (Figure 6step 3) For making the permanent metalconnection the prebonded die stack hasto be heated to the bonding temperatureThis temperature rise results in a thermalexpansion or a viscosity reduction of theunderfill material Decreasing theviscosity of the underfill can lead to ashape change caused by the surfacetension These ef fects can lead to a liftingup or shifting of the die in relation tothe target substrate Again this can causeopen contacts or misalignment Thereforeto avoid these effects preappliedunderfill can only be used for a sufficientlyhigh manufacturing yield with theapplication of force while permanentbonding The preapplied underfill can
either be fully cured in the permanentbonder by tempering for a longer periodof time or at an elevated temperature Itcan also be final cured in an externalprocess
ConclusionsFor die-to-wafer interconnects the
application of force is necessary whileforming the connection The advancedchip-to-wafer bonding process is asophist icated approach with theapplication of force while bondingCompared to other approaches like flip-chip bonder only or wafer-to-waferbonding it offers a much higher yield andthroughput and therefore a lower cost ofownership Additionally preappliedunderfill the gap-filling material ofchoice for high-volume production ofsmaller devices can only be economicallyused with application of force whilebonding These are the reasons whyAC2W is best suited for high volumechip-to-wafer stacking production
References1) Ph Garrou et al Handbook of 3DIntegration Wiley-VCH Volume 1 pp40 - 43 2008
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
2) H Huebner O Ehrmann M EignerW Gruber A Klumpp R Merkel PRamm M Roth J Weber and R WielandldquoFace-to-Face Chip Integration with FullMetal Interfacerdquo Proc Advanced
Metallization Conference MaterialsResearch Society p 53 San Diego 20023) A Longford and D James ldquoCopperpillar bumping in Intel microprocessors- one approac to lead freerdquo Presentation
in Advanced Packaging ConferenceSemicon Europe April 20064) T Mitsuhashi Y Egawa O Kato YSaeki H Kikuchi S Uchiyama KShibata J Yamada M Ishino H IkedaN Takakashi Y Kurita M Komuro SMatsui and M Kawano ldquoDevelopmentof 3D-Packaging Process Technology forStacked Memory Chipsrdquo Mater Res
Soc Symp Proc Vol 970 MaterialsResearch Society 20075) ldquoSony Leads the Industry in MassProduction Devices that Achieve theSame Performance as embedded DRAMLSIs in the Low-Cost SiP Processrdquo CX-
News Vol 50 Nov 2007 http
wwwsonynetProductsSC-HPcx_news6) K Sakuma P S Andry C K TsangS L Wright B Dang C S Patel B CWebb J Maria E J Sprogis S KKang R J Polastre R R Horton J UKnickerbocker ldquo3D chip-stackingtechnology with through-silicon vias andlow-volume lead-free interconnectionsrdquoIBM J Res amp Dev Vol 52 No 6 pp611 - 622 Nov 20087) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder ldquo3D Die-to-wafer CuSnMicroconnects Formed Simultaneouslywith an Adhesive Dielectric Bond UsingThermal Compression BondingrdquoInterconnect Technology ConferenceIITC International Burlingame CAUSA p 46 20088) L F Miller ldquoControlled CollapseReflow Chip Joiningrdquo IBM J Res ampDev Vol 13 p 239 19699) S Pargfrieder T Matthias C SchaeferM Wimplinger C Scheiring H Kostnerldquo3D Packaging via Advanced-Chip-to-Wafer (AC2W) bonding enables HybridSystem-in-Package (SiP) IntegrationrdquoIWLPC - Wafer-Level Packaging
Congress November 2-4 San JoseCalifornia 200510) S Pozder A Jain R Chatterjee ZHuang R E Jones E Acosta B MarlinG Hillmann M Sobczak G KreindlS Kanagavel H Kostner and SPargfrieder Interconnect Technology
Conference IITC InternationalBurlingame CA USA p 46 2008
11) N Marenco H Kostner W ReinertG Hillmann ldquoHybrid Chip-ScaleIntegration of Inertial MEMS by Chip-to-Wafer Vacuum Bondingrdquo 2 nd
European Conference amp Exhibition on
Integration Issues of Miniaturized
Systems - MOMS MOEMS ICs and
Electronic Components Smart SystemIntegration Barcelona 2008
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
New Realities for TSV ProcessingCoO Variation on Theme
By Steve Lerner CEO [Alchimer Massy France]
-D integration and More-than-Moore are popular topics in thesemiconductor industry with
high expectations for eventual wide useof 3D-IC technologies But the pace andscale of adoption is largely dependent onlong-term cost of ownership (CoO) Thisarticle presents an alternate perspectivefrom those through-silicon-via (TSV)consortia oriented around adaptation offront-end processing examining allaspects from design to factory-floordeployment
What is a TSV A real reference for costItrsquos important to keep in mind that
TSVs are not sensitive transistors withcomplex switching characteristics Theyare in fact merely dumb wires andshould be treated as such So in thePareto chart of TSV-manufacturingconcerns the top three items would becost cost and cost (assuming reliabilityand process control are in place for thegiven application) Although eachapplication will have different priorities(parasitics mechanical and thermalcompliance etc) at the end of the daywe are still dealing with a wire
In the semiconductor industry mostexperience with dumb wires has been inthe back end where wire bonds packagepins and bumps have gone through anextraordinary evolution of reliabilityimprovement and cost reduction Therewas a time when wire-bond yield andreliability were in the 97 range Nowwe talk of parts per million (ppm)
3Outsourced assembly and test services(OSATs) were once challenged by apackage price of 1 cent per pin Now theydeliver products at a small fraction of apenny per IO 10 years ago bumped200mm wafers cost nearly $500 Today300mm wafers go for less than $50 withredistribution layer (RDL)
TSVs are on a similar trajectory Infact an interposer wafer has much morein common with a bumped RDL waferor a printed circuit board than it doeswith a typical CMOS wafer Thereforethe infrastructure to process such aninterconnect vehicle can and should berad ica l ly d i f f e ren t f rom CMOSinfrastructure It is commendable thatsome front-end consortia have modeledTSV wafer processing at below $200but if TSVs are to realize their truepotential initial cost must be less than$50 - with a target of $25 within thenext five years Given the typical five-year depreciation of those front-endmachines it is no wonder that stickershock is widespread especially amongcompanies that are not the mostdominant and integrated semiconductorplayers But there is hope
It starts with designUnfortunately designers have been
conspicuously absent from manydiscussions regarding the formation of theTSV infrastructure and run the risk ofmissing out on the greatest potential benefitsof 3-D integration The most strategicquestion from the design perspective is
about aspect ratio Theability to decrease TSVdiameter has hugeimplications for howmuch d ie space i savailable for workingcircuitry and for theoverall cost impact ofTSV adoption
And this is where the necessity toreconsider adoption of dry vacuum-based front-end processes becomes mostapparent The most notable design ruledif ferences between wet and dry TSVfilm deposition are in via aspect ratioMost front-end tooling groups currentlymodel around a 61 aspect ratio for costpurposes but state capability up to 101Why such a modest starting pointSimply because most dry tools - withthe exception of expensive low-throughput techniques such as ALD -simply canrsquot deliver the aspect ratiosmost beneficial to designers
Current wet processing can easily deliver201 aspect ratio and higher at asignificantly reduced cost Figure 1
demonstrates the impact of TSV aspectratio on silicon real estate1 TSV aspectratios of more than 101 can cut the areaneeded for vias to lt1 of the wafer surfaceand keep costs under $100wafer Thismodel assumes 10 x 10mm dice on a300mm wafer with 10000 TSVs of 50nmdepth and total wafer cost of $6359
Fur ther des igners have beenbombarded with dry film properties asthe only electrical parameters availablewhen in fact better-performing materialscan be attained through wet processingTable 1 illustrates common depositionproperties and process capabilitiesassociated with a novel family of
(continued on Page 33)
Figure 1 TSV wafer area penalty as a function of
aspect ratio with calculated costwafer
Table 1 Common film properties for eGeC films
Parameter Value Unit Notes
Thickness 50 - 500 nm
Thickness uniformity 5 3 σAdhesion All layers pass 16-square scribe tape test
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Ahalf century has passedsince underfill was firstapplied to flip-chip ICs In
that time much effort has been directedtoward optimizing thermo-mechanicalproperties such as viscosity stiffnessthermal expansion and adhesion inorder to make the underfill process ascheap effective and factory-friendly aspossible In recent years attention hasturned to increasing the thermalconductivity as a means of reducing ICtemperatures in high-power devices
UnderfillsMost commercially-available
underfills are composed of an organicresin (typically epoxy or silicone) towhich filler particles (often aluminasilica or aluminum) are added toincrease stiffness and reduce thermalexpansion The resin alone has a lowthermal conductivity (01-03 WmK)but the addition of high-conductivityparticles can easily double that valueand through careful control of particlesize and shape raise it to 15WmK ormore Employing more exotic fillersmade from carbon fiber boron nitrideor various nanoparticles and nanotubescan result in composite conductivitiesa s h i g h a s 3 0 W m K t h o u g hmanufacturability can be a concernThis one to two orders of magnitudeimprovement in thermal conductivityis impressive but the underfill is onlyone factor in an overall thermalmanagement scheme So to place thesematerial developments in perspectiveit is necessary to examine their impactat the electronic package or modulelevel
The studyThe range of package and module
designs in use today varies widely For
High Thermal Conductivity
Underfills-How Much Do They HelpSome but underfills are only part of the storyBy Zane Johnson and Nathan Schneck [Center for Nanoscale Science and Engineering North Dakota State University]
an initial study on the benefit of high-conductivity underfill a flip-chipSilicon-on-Sapphire (SoS) device waschosen SoS is a member of the silicon-o n - i n s u l a t o r f a m i l y o f C M O Stechnologies and due to sapphirersquosintrinsic radiation resistance showsdistinct benefits in aerospace andsatellite applications To simulate thethermal performance of the SoS flip-chip a Finite-Element (FE) model wasconstructed The configuration is thatof a 2 X 2mm die mounted directly toa 25 X 25mm PWB in the chip-on-board style The die has twenty eutectictin-lead solder bumps spaced equallyaround its periphery on a 333μm pitchVoid-free underfill is used to bridge the55μm gap between the die face and thePWB No heat sink or heat spreadingfeature is present The meshed FEmodel is shown in Figure 1
The FE model dissipates a steadyand uniform 100mW at the die-underfill interface and naturalconvection and radiation boundaryconditions are applied to the die andPWB surfaces to represent heat loss to
Figure 1 FE model of a chip-on-board
configuration The IC is shown in gray the underfillin yellow and the PWB in green The full extent of
the PWB is not shown and the flip-chip solder jointsare hidden from view Quarter-symmetry is assumed
to reduce the size of the model
a still air environment at 298K (25o
C)As is typical with very small devicesand ICs almost all of the powergenerated in the device flows downwardinto the PWB where it spreads laterallyand is eventually released to theenvironment As a consequence thecomposite conductivity of the PWB is ac r i t i c a l f a c t o r i n t h e t h e r m a lperformance of a chip-on-board ICPeak temperature occurs at the centerof the die with PWB temperaturesdropping with increasing distancefrom the IC Temperature contoursfrom a typical simulation are shown inFigure 2
To gauge the ef fectiveness ofenhanced-conductivity underfill theconductivities of the underfill and thePWB were varied over a realistic rangeof values A full-factorial study wasperformed with underfill conductivityvalues that ranged from 0027WmK(representing air or no underfill) to20WmK (a highly filled resin) ThePWB conductivity values were variedfrom 02WmK to 30WmK PWBconstruction varies widely but therange chosen captures many board andmodule designs of practical interestForty-nine FE simulations wereperformed The simulation results are
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
presented as maximum die temperaturerise over ambient The results aresummarized as contours in a PWBunderfill conductivity plot (Figure 3)
AnalysisNote that the contours and contour
labels are not evenly spaced Overallthe contour pattern of nearly parallellines shows that increasing PWBconductivity yields a much greaterbenefit (lower die temperature) thanincreasing underfill conductivity For
example for a PWB conductivity of15WmK and an underfill conductivityof 02WmK the model predicts a dietemperature rise of 154
o
C Increasingthe underfill conductivity to 20WmKyields a die temperature rise of 136
o
Can improvement of only 18 degreesCelsius (12) at this 100mW powerlevel
Notably die temperatures risesharply when PWB conductivity dropsbelow 5WmK but in practice fewPWB designs exhibit compositeconductivities lower than that Thecontours show that for most PWBs ofinterest l i t t le benefit is seen byincreasing the underfill conductivitybeyond 05WmK This contour patternmay change perhaps significantly forother chip-on-board designs or otherpackaging technologies
ConclusionsFor this chip-on-board configuration
only minimal thermal benefit was seenfor underfil l conductivity valuesbeyond 05WmK This study doesi l lustrate the importance of PWBc o n d u c t i v i t y i n I C t h e r m a lmanagement and that a designer
Figure 3 Die temperature rise over ambient as afunction of underfill and PWB thermal conductivity
Contour values are in o
C
wou ld b e w i s e t o i n co rpo ra t enumerous thermal vias into ICsubstrate and module designs Newldquohigh conductivityrdquo underfills do notchange this basic design imperative
Acknowledgement and disclaimerThis material is based on research
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
f you are a smaller OEM EMS orsupplier that is running lean howmuch is too much involvement in
back-office administration Would you bebetter off spending your time exclusivelyon growing your business through salesand engineering tasks per se leaving theback office to someone else If you haveall the time in the world and love whatyoursquore doing I say have at it but that isnot the typical scenario Usually CEOsand Engineering Management wind upwearing many hats So how do you knowwhen that last hat was one too many anditrsquos time to bring in the cavalry hiring oroutsourcing
The Signs Are ThereLetrsquos define back office as any of the
approximately 80 of the business tasksthat do not impact on the customerrsquos clientexperience with your company Thosefront-office tasks that do impact the
customer such as sales follow up andcustomer service should remain firmly inyour hands as your core business and notbe outsourced My rule of thumb is that ifyou can make more money doing yourcore business than you would lose bypaying someone else to do the data entryaccounting or whatever else from theback office then pay someone else to doit You still come out ahead and if youare losing money because you are not onlyneglecting your core but doing theldquowhateverrdquo poorly then definitely hiresomeone else to do it
The CEO of any small business is whatElizabeth Marasco of Bookkeepers Pluscalls a causative being a hands-onperson whose ability to make thingshappen is one of his or her most valuableassets But eventually as the successfulexecutive grows the business there is justtoo much administrative work for oneperson or even several to handle Soonthat typical 80 administrative end ofthe business begins to eat into theremaining 20 needed to continuegenerating the revenue When thathappens it becomes critical decisiontime Let us assume you have seen thesigns and decided that you are at thepoint where you need administrativehelp What are your options as a small-to-medium sized business There arethree main ones
Option 1- the EmployeeThe first would be to hire employees
either part or full time But thenironically you take even more back-officeresponsibility and cost You also find thatfor every employee hired you will berobbed of part of your own dedicated timeas you train mentor and answerquestions If you have built up enough
reserves to take on this additional cost andtime and feel it will help your companygrow it may well be the way to go andyou will have hired people to both handlethe tasks and grow with your companyBut not everyone has that option
What if yoursquore not at the point whereyou have any reserves or any extra timeto train and mentor Itrsquos a conundrumbecause you still have to free yourself tobring in more revenue What nowPerhaps a skilled virtual assistant orother expert could help
Option 2-the Virtual AssistantEnter the next player the virtual
assistant What exactly is a virtualassistant (VA) According to AnneWanchic a VA based in Florida whowrites about the subject online sheheis someone you work with but may nevermeet because they accomplish theassigned tasks from their offices oftenin their home and email fax or in someother way delivers the results to you TheVA may visit with you through virtualmeeting sites such as Go-To-Meeting oron Skype but as an independentcontractor they set up and maintain theirown office pay their own insurance andpay and file their own taxes Note thatyou will however need to keep track ofhow much you spend on an independentcontractor If it is over one thousanddollars in a calendar year you will needto issue them a Form 1099 They use thatto declare income and pay taxes
Wanchic feels your business needsmight be handled by a VA in less timethan by a part-time employee since agood VA may be able to take as much asthirty hours per week and turn it into onlythirty hours per month Many VAs haveyears of executive administrative
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
experience from the brick and mortarworld are already skilled in multi-tasking and take less time to producehigh quality work VAs usually work onretainer for ten to thirty hours per monthand are your best bet versus a part-timeemployee if the amount and type of tasksyou delegate is consistent and the cost isless than a part-time employee A goodresource to find a VA with the right skillset for your needs is to visit the InternationalVirtual Assistants Associationrsquos sitewwwivaaorg or simply do a search forVirtual Assistants
Option 3-Full-Service PartnerIf you like the idea of a company which
handles all your back office needs thena full-service partner is for you This isthe option of choice for many smallcompanies that simply do not have thetime or the background to figure out whytheir computer went down when they areon a deadline They just want it fixedThey find it very desirable to have onepoint of contact to provide their internetphone service host their website and dotheir accounting
I spoke with Pete Calderaro VP ofBusiness Development for INT acompany that takes care of many back-office needs ldquoThe thing is once you seehow much time it gives you to succeedat what you really love doing itrsquos hard
to go back to the old way of doingeverything yourselfrdquo he said He citedthe example of one company who wasspending five hours per day on lengthyspreadsheets INT looked at the endresult that the company was aiming forand developed a template for them thatincluded calculation formulas With thenew formulas in place those five hoursspent per day dropped to forty-fiveminutes ldquoUtilizing our experiencedpeople makes all the difference to a smallcompanyrdquo Calderaro concluded
For a brand new startup a full-servicepartner can arrange to lease you officefurniture and computers so you need notinvest in that during your critical first yearFor a lot of busy people thatrsquos perfect
How Do You Select a ServiceProvider
Letrsquos assume that you are convinced thatoutsourcing is for you How do you protectyourself and what are the basic steps youneed to take Figure out what you want tooutsource Good candidates are data entryblog and website maintenance accountingpayroll secretarial and research reportsCategorize them as one-off or ongoingtasks and estimate how many hours youthink each will entail Then interview bothVirtual Assistants and Full ServiceAgencies to see which fits you better Besure to include the following in yourinterview process
Availability mdash do you need them towork the same hours as you do forexample
Resumeacutemdash ask about their experienceget references and check them
Obtain samples of their work Security mdash (sometimes the bigger
firms have the advantage here)specifically
Do they permanently delete your
data post task Do they back up data and how
often Do they store it securely
offsite Do they have a secure facility
(especially applicable for any
offshore outsourcing)
Non-disclosure agreements should
be signed by any VA or firm and
should also be signed by any
employees they may have Make sure that payroll services also
include filing payroll taxes and
making sure employees get end of
year forms etc Ensure you communicate well with
each other or you will be spending
too much valuable time explaining
and reinforcing Clarify terms mdash they get paid for
performance not for effort If it
requires outside labor to complete
the agreed-upon task or more hours
than they anticipated that is their
responsibility not yours Clarify type of agreementpayment
for example per project or per hour
Depending on the type of work the
rates could be anywhere from ten
to fifteen dollars per hour to over
eighty dollars per hour It all
depends on skill level specialist
designation and various other
factors Be sure to get several quotes
for comparison And remember the
higher fee of a specialist who can
do something in an hour may be no
more expensive than explaining the
task to someone who then takes
three hours to do it Document the terms in a simple
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2D 3DPR MP - 300 mmWFR PKG
3DPRMP - 300 mmWFR
3D ( TherMoire )PRMP - 600+ mmWFR PKG SUB PCB
3DPR NPMP - 450+ mmSDP SUB PCB
2D 3DPR NPMP - 600+ mmWFR PKG SUB PCB
3DPRMP - 450+ mmSDP SUB PCB
( XYZ ) - CM PR NPMP - 300 mm WFR ( BONDED )
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
2DNP MP - 300+ mm PKG SUB PCB
2D 3DPR NPMP - 600+ mmPKG SUB PCB
3D NPMP - 300+ mmPKG SUB PCB
2D - 2 Dimension ( XY ) 3D - 3 Dimension ( XYZ ) PR - ProgrammableNP - Non ProgrammableMP - Max Product SizeCM - Contact Manufacturer
Product Type Applications WFR - Wafer PKG - Package SDP - Solder Paste SUB - Substrate PCB - PC Board
COMPANYHEADQUARTERS
OPTICAL INSPECTION
X-RAYINSPECTION
ACOUSTIC INSPECTION
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
FocalSpot Inc9915 Businesspark Avenue Ste ASan Diego CA 92131Tel +1-858-536-5050wwwfocalspotcom
GE Inspection Technologies50 Industrial Park RoadLewistown PA 17044Tel +1-866-243-2638wwwgesensinginspectioncom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Machine Vision Products Inc5940 Darwin CourtCarlsbad CA 92008Tel +1-760-438-1138wwwvisionprocom
MIRTEC Corporation103-803 SK Ventium Bldg522 Dangjeong-Dong GunpoKyunggi-Do 435-776 KoreaTel +82-31-202-5999wwwmirteccom
Nikon Metrology NVGeldenaaksebaan 3293001 Leuven Belgium Tel +32-16-74-0100wwwnikonmetrologycom
North Star Imaging Inc19875 S Diamond Lake Road 10 Rogers Minnesota 55374Tel +1-763-463-5650www4nsicom
Panasonic Factory Solutions Company of America909 Asbury DriveBuffalo Grove IL 60089Tel +1-847-495-6100wwwpanasonicfacom
PVA TePla Analytical Systems GmbHGartenstrasse 133Aalen 73430 GermanyTel +49-7361-376523-0wwwpva-analyticalsystemscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
Teradyne Assembly Test Division700 Riverpark DriveNorth Reading MA 01864Tel +1-978-370-2700wwwteradynecomatd
Test Research7F No 45 Dexing W Road Shilin DistrictTaipei City 11158 TaiwanTel +886-2-2832-8918wwwtricomtw
VI TechnologyEspace Gavaniegravere Rue de RochepleineSaint-Egregraveve 38120 FranceTel +33-4-7675-8565wwwvitechnologycom
View Micro Metrology615 South Madison Dr Tempe AZ 85281Tel +1-480-295-3150wwwviewmmcom
Viscom Inc1775 Breckinridge Parkway Ste 500Duluth GA 30096Tel +1-678-966-9835wwwviscomcom
VJ Electronix Inc234 Taylor StreetLittleton MA 01460Tel +1-978-486-4777wwwvjtcom
Xradia Inc5052 Commercial CircleConcord CA 94520Tel +1-925-288-1228wwwxradiacom
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Inspection processes and optionsMost of the time inspection is carried
out by operators looking into a
microscope to find tiny particles This
process is the least expensive upfront
and allows some kind of manual
cleaning Yet it shows several
drawbacks and can become more costly
in the end
The shrink of the pixel size down to
11μm in mass production and soon
even smaller leads to great difficulty
for the operator to accurately detect very
small defects in the range of 1μm Also
visual inspection is not a repeatable
process since dif ferent people with
dif ferent experience will output
different results The last issue with
operatorsrsquo inspection is the requirement
for a big number of inspection desks
which can consume space and imply a
lot of manual handling In the end
manual inspection usually leads to
unknown high escape rates resulting in
scrap costs at the end of the process
There is also a costly requirement in
terms of clean-room space
The other common inspection process
today is the incoming automated
inspection of the sensors in wafer
format before sensor placement wire
bonding and lens attach processes This
process is mature and quite efficient
however it has the drawback of being
held too far upstream of the lens-attach
process step which has to be applied on
For more information contact Ryan Close at
rclosepiperplasticscom
(800) 526-2960wwwpiperplasticscom
INTRODUCINGA New Material Solution for KeyMicroprocessor Test Socket Applications
bull Significantly lower moisture absorptionbull Very tight tolerance machiningbull Impact strength stiffness and minimum creep levelsbull Half the weight of ceramicsbull Greater impact resistance and toughness compared to ceramicsbull Excellent processability and wear performancebull Good dielectric properties for insulative applicationsbull Clean white or grey color
For more information on Piper PlasticsrsquoKyron EPM-2204 ceramic filled PEEKtrade polymerfor microprocessor test sockets please visit Piper Plastics at SEMICON West 2010
Piper Plasticsrsquo Kyron EPM-2204 Ceramic PEEKtrade polymer offers excellent dimensional stability and tolerance control across a broad range of temperature and humidity conditions making it ideal for high performance test socket components Competitive advantages include
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
WD up to 300 mmDS 025 - 254 mmXY plusmn 10 - 15 micromθ plusmn 005 - 05degCT 07 sec
WD up to 200 mmDS 03 - 15 mmXY plusmn 5 micromθ CMCT 14 sec
WD CMDS CMXY plusmn 10 micromθ CMCT 036 sec
WD up to 200 mmDS 015 - 500 mmXY plusmn 1 - 10 micromθ CMCT CM
WD up to 300 mmDS 05 - 25 mmXY plusmn 12 micromθ plusmn 01 - 10degCT 04 sec
WD up to 300 mmDS 007 - 100 mmXY plusmn 05 - 5 micromθ CMCT CM
WD up to 450 mmDS 05 - 35 mmXY plusmn 10 micromθ CMCT 08 - 10 sec
WD up to 300 mmDS 02 - 12 mmXY plusmn 5 micromθ CMCT CM
COMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
Advertisers are listed in Boldface type Refer to our Editorial Calendar for upcoming Directories
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
INTERNATIONAL DIRECTORY OF DIE AND FLIP CHIP BONDERSCOMPANYHEADQUARTERS
DIE BONDERCAPABILITY
DIE BONDERSPECIFICATIONS
FLIP CHIP BONDERCAPABILITY
FLIP CHIP BONDERSPECIFICATIONS
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Hybond330 State PlaceEscondido CA 92029Tel +1-760-746-7105wwwhybondcom
Kosaka Laboratory LtdMikuni East Building 2F6-13-10 Sotokanda Chiyoda-kuTokyo 101-0021 JapanTel +81-3-5812-2081wwwkosakalabcojp
Kulicke amp Soffa Industries Corp1005 Virginia DriveFt Washington PA 19034Tel +1-215-784-6000wwwknscom
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp
Compiled by AZ TECH DIRECT LLC wwwAzTechDirectcom Direct all inquiries and updates to surveysaztechdirectcomListing data has been compiled from company inputs andor website search and may not be current or all-inclusive as of the date of publication
CompanyStreet AddressCity State CountryTelephoneWebsite
CM = Contact Manufacturer
Shibaura Mechatronics Corporation2-5-1 Kasama Sakae-ku YokohamaKanagawa Prefecture 247-8610 JapanTel +81-45-897-2421wwwshibauracojp
Shibuya Kogyo Co LtdMameda-Honmachi KanazawaKanazawa 920-8681 JapanTel +81-76-262-1200wwwshibuyacojp