Voltage Fed Full Bridge DC-DC & DC-AC Converter High-Freq ...

Application ReportVoltage Fed Full Bridge DC-DC and DC-AC Converter forHigh-Frequency Inverter Using C2000

Atul Singh and Jabir VS

ABSTRACT

The High-Frequency Inverter is mainly used today in uninterruptible power supply systems, AC motor drives,induction heating and renewable energy source systems. The simplest form of an inverter is the bridge-type,where a power bridge is controlled according to the sinusoidal pulse-width modulation (SPWM) principle and theresulting SPWM wave is filtered to produce the alternating output voltage. In many applications, it is importantfor an inverter to be lightweight and of a relatively small size. This can be achieved by using a High-FrequencyInverter that involves an isolated DC-DC stage (Voltage Fed Push-Pull/Full Bridge) and the DC-AC section,which provides the AC output. This application report documents the implementation of the Voltage Fed FullBridge isolated DC-DC converter followed by the Full-Bridge DC-AC converter using TMS320F28069 ( C2000™)for High-Frequency Inverters.

Project collateral and source code discussed in this document can be downloaded from this URL: http://www.ti.com/lit/zip/sprabw0.

Table of Contents1 Basic Inverter Concept...........................................................................................................................................................22 High-Frequency Inverter – Block Diagram........................................................................................................................... 33 DC-DC Isolation Stage - High-Frequency Inverter...............................................................................................................44 DC-AC Converter.................................................................................................................................................................... 65 DC-DC Converter Section (Voltage Fed Full Bridge)...........................................................................................................76 Control Section....................................................................................................................................................................... 97 DC-AC Converter Section...................................................................................................................................................... 98 Firmware Flowchart.............................................................................................................................................................. 119 Waveforms.............................................................................................................................................................................1210 Conclusion.......................................................................................................................................................................... 1311 References...........................................................................................................................................................................1312 Revision History................................................................................................................................................................. 13A Application Schematic.........................................................................................................................................................14

List of FiguresFigure 1-1. 50 Hz Technology......................................................................................................................................................2Figure 1-2. Transformerless Inverter Technology........................................................................................................................ 2Figure 1-3. High-Frequency Inverter Technology........................................................................................................................ 3Figure 2-1. High-Frequency Inverter – Block Diagram................................................................................................................ 3Figure 3-1. Push-Pull Topology....................................................................................................................................................4Figure 3-2. Half Bridge Converter................................................................................................................................................5Figure 3-3. Full Bridge Converter................................................................................................................................................ 5Figure 5-1. Functional Block Diagram of UCC27211...................................................................................................................7Figure 5-2. Gate Drive Waveforms for the Full Bridge DC-DC Converter................................................................................... 8Figure 7-1. Functional Block Diagram....................................................................................................................................... 10Figure 8-1. Firmware Flowchart................................................................................................................................................. 11Figure 9-1. Output Voltage at No Load...................................................................................................................................... 12Figure 9-2. Output Voltage and Current (100W Load)...............................................................................................................12Figure A-1. DC-DC Converter Schematic (Voltage Fed Isolated Full-Bridge)........................................................................... 14Figure A-2. Control Section Schematic......................................................................................................................................15Figure A-3. DC-AC Converter Schematic.................................................................................................................................. 16

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SPRABW0D – MAY 2014 – REVISED APRIL 2021Submit Document Feedback

Voltage Fed Full Bridge DC-DC and DC-AC Converter for High-FrequencyInverter Using C2000

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TrademarksC2000™ and Piccolo™ are trademarks of Texas Instruments.All trademarks are the property of their respective owners.

1 Basic Inverter ConceptThere are basically three different inverter technologies:

• Inverter with a 50 Hz transformer• Inverter without a transformer• Inverter with a high-frequency (HF) transformer

S2 S4

L1S3S1

C1

Figure 1-1. 50 Hz Technology

The applied DC voltage is converted to a 50 Hz AC voltage via a full bridge (S1...S4). This is then transmitted viaa 50 Hz transformer and subsequently fed into the public grid.• Benefits:

– High degree of reliability due to fewer components– Safety through galvanic isolation of the DC and AC sides

• Disadvantages:– Low degree of efficiency resulting from high transformer losses– Heavy weight and volume (for example, due to 50 Hz transformer)

S2 S4

L1S3S1

C1

L2

Figure 1-2. Transformerless Inverter Technology

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The existing DC voltage is converted to a square 50 Hz AC voltage via a full bridge (S1...S4), then smoothed toa sinusoidal 50 Hz AC voltage via the chokes (L1+L2) and fed into the public grid.

• Benefits:– Compact and light due to lack of transformer– Very high degree of efficiency (for example, no transformer losses)

• Disadvantages:– Additional safety measures (residual current circuit breaker) required. In some countries, a lack of galvanic

isolation between the DC and AC sides is not permitted.– Complicated lightning protection– Not compatible with modules that must be earthed

S6 S8

L2S7S5

C2

L3

L1

D1 D3

D2 D4

S2 S4

S3S1

C1

Tr1

Figure 1-3. High-Frequency Inverter Technology

The full bridge (S1...S4) generates a high-frequency square-wave signal with 40 – 50 kHz, which is transmittedvia the HF transformer (Tr1). The bridge rectifiers (D1...D4) convert the square-wave signal back to DC voltageand store it in the intermediate circuit (L1+C2). A second full bridge (S5...S8) then generates a 50 Hz ACvoltage, which is smoothed to a sinusoidal 50 Hz AC voltage via the chokes (L2+L3) before being fed into thepublic grid.

• Benefits:– Compact and light, as the HF transformer is very small and light– High degree of efficiency through reduction of transformer losses– Safety through galvanic isolation between the DC and AC sides– Suitable for all module technologies, as module earthing (positive and negative) is possible

2 High-Frequency Inverter – Block Diagram

AC Input EMI Filter DPDT Relay Load

AC-DC IsolatedPower Supply

TMS320F28069C2000 Series

BatteryDC-DC

Isolation StageDC-AC

ConverterLC Filter

Figure 2-1. High-Frequency Inverter – Block Diagram

The present application report documents the implementation of the DC-DC isolation and DC-AC conversionstage using TMS320F28069. The F2806x Piccolo™ family of microcontrollers provides the power of the C28xcore and the Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low-pin countdevices. This family is code-compatible with previous C28x-based code, as well as providing a high levelof analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been

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made to the high-resolution pulse width modulator (HRPWM) module to allow for dual-edge control (frequencymodulation).

Analog comparators with internal 10-bit references have been added and can be routed directly to control thepulse width modulation (PWM) outputs. The analog-to-digital converter (ADC) converts from 0 to 3.3-V fixed fullscale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized forlow overhead and latency. The above features make the F2806x Piccolo suitable for handling both the stages ofthe High-Frequency Inverter.

The main blocks of the High-Frequency Inverter include:

• DC-DC isolation stage• DC-AC converter section

3 DC-DC Isolation Stage - High-Frequency InverterThe selection of the DC-DC isolation stage for the High-Frequency Inverter depends on the kVA requirements ofthe inverter. The power supply topologies suitable for the High-Frequency Inverter includes push-pull, half-bridgeand the full-bridge converter as the core operation occurs in both the quadrants, thereby, increasing the powerhandling capability to twice of that of the converters operating in single quadrant (forward and flyback converter).The push-pull and half-bridge require two switches while the full-bridge requires four switches. Generally, thepower capability increases from push-pull to half-bridge to full-bridge.

VOUT

R

+

D2

Cnp

VIN

PUSH PULL

Q2 Q1

ns

np ns

D1L

Figure 3-1. Push-Pull Topology

The Push-Pull topology is basically a forward converter with two primaries. The primary switches alternatelypower their respective windings. When Q1 is active, current flows through D1. When Q2 is active, current flowsthrough D2. The secondary is arranged in a center tapped configuration as shown in Figure 3-1. The output filtersees twice the switching frequency of either Q1 or Q2. The transfer function is similar to the forward converter,where “D” is the duty cycle of a given primary switch, which accounts for the “2X” term. When neither Q1 nor Q2are active, the output inductor current splits between the two output diodes.

A transformer reset winding shown on the forward topology is not necessary, the topology is self resetting.

NsV V D

out in Np2= ´ ´ ´

(1)

3.1 Half Bridge ConverterThe Half Bridge converter is similar to the Push-Pull converter, but a center tapped primary is not required. Thereversal of the magnetic field is achieved by reversing the direction of the primary winding current flow. In thiscase, two capacitors, C1 and C2, are required to form the DC input mid-point. Transistors Q1 and Q2 are turnedON alternately to avoid a supply short circuit, in which case the duty cycle d must be less than 0.5.

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+VOUT

+

D2

+VIN

0 V

L1D1T1

+

+C3

Q1

+C1

0 V

Q2+

C2

Figure 3-2. Half Bridge Converter

For the Half-Bridge converter, the output voltage VOUT equals:

NV V d

out in N

2

1

= ´

(2)

Where, d is the duty cycle of the transistors and 0 < d < 0.5.

N2/N1 is the secondary to primary turns ratio of the transformer.

3.2 Full Bridge ConverterThe transformer topology for both the Half Bridge and Full Bridge converter is the same, except that for a givenDC link voltage of the Half Bridge transformer sees half the applied voltage as compared with that of the FullBridge transformer. The current flows in opposite directions during alternate half cycles. So flux in the coreswings from negative to positive, utilizing even the negative portion of the hysteresis loop, thereby, reducing thechances of core saturation. Therefore, the core can be operated at greater Bm value here. The largest poweris transferred when the duty cycle is less than 50%. Diagonal pairs of transistors (Q1-Q4 or Q2-Q3) conductalternately, thus, achieving current reversal in the transformer primary.

Output voltage equals:

NV V d

out in N

22

1

= ´ ´

(3)

Where, d is the duty cycle of the transistors and 0 < d < 0.5.

N2/N1 is the secondary to primary turns ratio of the transformer.

+VOUT+

D2

+VIN

0 V

L1D1T1

+

+C2

Q3

0 V

Q4

+C1

Q1

Q2

Figure 3-3. Full Bridge Converter

The choice of the DC-DC isolation stage for the High-Frequency Inverter among the three topologies discussedabove depends on the VA requirement. For applications targeting 1KVA and above, the Full Bridge converter isthe ideal choice pertaining to the points below:

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• For a given input voltage, the voltage stress on the transistors is double in case of the push-pull topology thanHalf Bridge and Full Bridge configuration.

• The center tapped primary in the case of the push-pull converter limits the operation for a higher VA rating forthe same core size when compared to the Half Bridge and Full Bridge converter.

• To prevent flux walking in the DC-DC stage, the current in both the halves need to be sensed and the dutycycle needs to be corrected accordingly.

3.2.1 Flux Walking

Faraday’s Law states that the flux through a winding is equal to the integral volt-seconds per turn. This requiresthat the voltage across any winding of any magnetic device must average zero over a period of time. Thesmallest DC voltage component in an applied AC waveform will slowly but inevitably “walk” the flux intosaturation.

In a low frequency mains transformer, the resistance of the primary winding is usually sufficient to control thisproblem. As a small DC voltage component pushes the flux slowly toward saturation, the magnetizing currentbecomes asymmetrical. The increasing DC component of the magnetizing current causes an IR drop in thewinding, which eventually cancels the DC voltage component of the drive waveform, hopefully well short ofsaturation. In a high frequency switchmode power supply, a push-pull driver will theoretically apply equal andopposite volt-seconds to the windings during alternate switching periods, thus, “resetting” the core (bringing theflux and the magnetizing current back to its starting point). But there are usually small volt second asymmetriesin the driving waveform due to inequalities in MOSFET RDSon or switching speeds. The resulting small DCcomponent causes the flux to “walk”. The high frequency transformer, with relatively few primary turns, hasextremely low DC resistance, and the IR drop from the DC magnetizing current component is usually notsufficient to cancel the volt-second asymmetry until the core reaches saturation.

The flux walking problem is a serious concern with any Push-Pull topology (bridge, half-bridge or push-pull CT),when using voltage mode control. One solution is to put a small gap in series with the core. This raises themagnetizing current so that the IR drop in the circuit resistances is able to offset the DC asymmetry in the drivewaveform. But the increased magnetizing current represents increased energy in the mutual inductance, whichusually ends up in a snubber or clamp, increasing circuit losses. A more elegant solution to the asymmetryproblem is an automatic benefit of using the current mode control (peak or average CMC). As the DC fluxstarts to walk in one direction, due to the volt-second drive asymmetry, the peak magnetizing current becomesprogressively asymmetrical in alternate switching periods. However, current mode control senses the current andturns off the switches at the same peak current level in each switching period, so that ON times are alternatelylengthened and shortened. The initial volt-second asymmetry is thereby corrected, peak magnetizing currentsare approximately equal in both directions, and flux walking is minimized.

However, with the Half Bridge topology this creates a new problem. When current mode control corrects the volt-second inequality by shortening and lengthening alternate pulse widths, an ampere-second (charge) inequalityis created in alternate switching periods. This is of no consequence in full bridge or push-pull center-tap circuits,but in the half-bridge, the charge inequality causes the capacitor divider voltage to walk towards the positiveor negative rail. As the capacitor divider voltage moves away from the mid-point, the volt-second unbalance ismade worse, resulting in further pulse width correction by the current mode control. A runaway situation exists,and the voltage will walk (or run) to one of the rails.

Considering the above points, the Full Bridge converter seems to be the ideal choice for the High-FrequencyInverter rated above 1kVA.

4 DC-AC ConverterThe DC-AC Converter section of the High-Frequency Inverter is an H-Bridge, which converts the high voltageDC bus (380 V) into sinusoidal AC waveform.

The sinusoidal PWM generation is done using the PWM interrupt handler in TMS320F28069 by entering into aninfinite loop. A look-up table is formed that samples the instantaneous values at specific time intervals based onthe operating frequency of the DC-AC section. The DC-AC section is operated at 20 kHz, based on that the totalnumber of samples for half cycle is 200. The instantaneous value is then multiplied by the maximum duty cyclecount to get the duty cycle count at the corresponding sample instant. This generates the sinusoidal PWM forthe full bridge section. The DC-AC section consists of high-side and low-side drivers to drive the Mosfets in theH-Bridge configuration followed by an output L-C- L filter resulting in sinusoidal sine wave.

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5 DC-DC Converter Section (Voltage Fed Full Bridge)The DC-DC section consists of 120 V boot, 4A peak high frequency high-side and low-side driver UCC27211 fordriving the high-side and low-side FET’s of the Full Bridge converter.

In UCC27211, the high side and low side each have independent inputs, which allow maximum flexibility of inputcontrol signals in the application. The boot diode for the high-side driver bias supply is internal to the chip. TheUCC27210 is the pseudo-CMOS compatible input version and the UCC27211 is the TTL or logic compatibleversion. The high-side driver is referenced to the switch node (HS), which is typically the source pin of thehigh-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS, which istypically ground. The functions contained are the input stages, UVLO protection, level shift, boot diode, andoutput driver stages.

Figure 5-1 shows the independent control of the high-side and low-side drivers and the internal bootstrap diodecapable of withstanding the reverse voltage up to 120 V.

5

1

6

2

3

4 HS

8 LO

7 VSS

Level

Shift

UVLO

UVLO

HI

VDD

LI

HO

HB

Figure 5-1. Functional Block Diagram of UCC27211

The VDD supply of the IC is derived from the 12 V battery itself (HF inverter source). The DC-DC stage convertsthe 12 V input voltage to a regulated 380 V DC bus, which is the input to the DC-AC section. To avoid batteryinrush current at the start of the PWM, soft start is implemented that controls the rate of di/dt. The PWM’s initiallystart with a very low duty and finally duty cycle is adjusted as per the regulation point of the DC bus voltage(380 V). The operating frequency for the switches in the DC-DC section is 40 kHz, the output filter sees twice thefrequency of the switches M6 or M9 (see Figure A-1).

5.1 Voltage Fed Full Bridge Converter Transformer Calculation• Total Output Power Po = (Vo + Vrl + Vd) IoWhere, Vo = Output voltage

Vrl = Voltage drop due to winding resistance

Vd= Forward voltage drop of the output diode

Io= Output current

• The Area Product for this configuration is given as:( )Po

ApKw J Bm Fsw

2 1/

4. . . .

é ù+ hë û=

Where, η = Efficiency of the Full Bridge converter

Kw = Window factor

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J = Current Density (A/m2)

Bm = Magnetic flux density

Fsw = Switching frequency

• Primary Number of Turns( )Vin

NpAc Bm Fsw

maximum

4. . .=

Where, Ac= Core area

Vin (maximum) = Maximum input voltage applied to the Full Bridge converter

• Turns Ratio( )Vo Vrl Vd

nD Vin2. max. min

+ +=

Where, Vin min = Minimum input voltage applied to the Full Bridge converter

Secondary turns Ns = n x Np

• RMS Values of CurrentsIsec = Io√Dmax

Ipri = n x Io

Where, Isec = Secondary current

Ipri = Primary current

Using the above calculations, the number of turns can be calculated for the required output power and the rmsvalues of the primary and secondary currents can also be found out for a given core area.

The calculation was done considering 1kVA requirement with battery input as the input voltage (12 V) in EF32core and the corresponding numbers of turns were calculated for both primary and secondary.

Figure 5-2. Gate Drive Waveforms for the Full Bridge DC-DC Converter

In order to minimize flux walking, as discussed Section 3.2.1, the peak current in each of the conducting halvescan be sensed using the fully differential isolation amplifier AMC1100.

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The AMC1100 is a precision isolation amplifier with an output separated from the input circuitry by a silicondioxide (SiO2) barrier that is highly resistant to magnetic interference. This barrier has been certified to providegalvanic isolation of up to 4250 V peak, according to UL1577 and IEC60747-5-2. Used in conjunction withisolated power supplies, this device prevents noise currents on a high common-mode voltage line from enteringthe local ground and interfering with or damaging sensitive circuitry.

After sensing the peak current, the duty cycle is corrected for each of the corresponding halves and volt secondasymmetry is thereby corrected, to minimize flux walking.

6 Control SectionThe control section consists of TMS320F28069 performing the control operation generating PWM’s for bothDC-DC section and SPWM’s for the DC-AC section using the PWM interrupt handler.

• MCU PWM Outputs• DC-DC section

– PWM1DH_MCU = High-Side Input Gate Drive 1– PWM1DL_MCU = Low-Side Input Gate Drive 1– PWM2DH_MCU = High-Side Input Gate Drive 2– PWM2DL_MCU = Low-Side Input Gate Drive 2

• DC-AC section:– PWM1AH_MCU = High-Side Input Gate Drive 1 for UCC27712– PWM1AL_MCU = Low-Side Input Gate Drive 1 for UCC27712– PWM2AH_MCU = High-Side Input Gate Drive 2 for UCC27712– PWM2AL_MCU = Low-Side Input Gate Drive 2 for UCC27712

• The Opto couplers HCPL-0211 provides isolated gate drives for the DC-DC section:– PWM1DH = High-Side Input Gate Drive for UCC27211 (Driver 1)– PWM1DL = Low-Side Input Gate Drive for UCC27211 (Driver 1)– PWM2DH = High-Side Input Gate Drive for UCC27211 (Driver 2)– PWM2DL = Low-Side Input Gate Drive for UCC27211 (Driver 2)

7 DC-AC Converter SectionThe DC-AC converter section consists of high- and low-side driver UCC27712, which is a high-voltage, high-speed power Mosfet and IGBT driver with independent low side and high side referenced output channels. It hasa floating channel designed for bootstrap operation and fully operational to +600 V. The floating channel can beused to drive an N-channel power MOSFET or IGBT in the high-side configuration, which operates up to 600 V.

Figure 7-1 shows the functional block diagram of the driver. The bootstrap diode is placed external to the driverand the device can handle peak currents up to 4A.

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VSSCOMLevelShift Pulse

Generator

HIN

PulseFilter

HV LevelShifter

UVDetect

R

R

S

Q

Q

VB

HO

VS

UVDetect

VCC

LO

COM

DelayVSSCOM

LevelShift

LIN

Figure 7-1. Functional Block Diagram

The AC voltage feedback to the MCU for closed-loop control is given by scaling down the voltage by a resistordivider network and rectifying it by means of a precision rectifier circuit. The precision rectifier circuit is built withthe high-speed precision difference amplifier INA143 followed by TL082 powered from a dual supply (±12 V).The rectified and scaled down Sine wave is fed to the MCU for closed-loop control of the output voltage.

The load current sense is done using ACS709, which is a precision linear Hall sensor integrated circuit withcopper conduction path. Applied current flows through the copper conduction path, and the analog outputvoltage from the Hall sensor IC linearly tracks the magnetic field generated by the applied current. The voltageon the overcurrent input (VOC pin) allows to define an overcurrent fault threshold for the device. When thecurrent flowing through the copper conduction path (between the IP+ and IP– pins) exceeds this threshold, theopen drain overcurrent fault pin transitions to a logic-low state and can be used to shut down the PWM pulsesof the DC-AC section and DC-DC section as well to provide protection against overload and short circuit of theload.

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8 Firmware Flowchart

Power on reset

Set the clock to 60 MHz

Initialize GPIO

Initialize ADC

Initialize PWM1 for DC-DC Conversion

Configure the PWM1 Interrupts

Start the PWM switching

with very low duty cycle for

soft start

Is the DC BUS

voltage equal

to 380 Volts?

Increase the

Duty Cycle

NO

YES

Enter Infinite loop and

operate using the interrupt

handlers

Initialize PWM2 for DC-AC conversion

Configure the PWM2 Interrupts

Generate the Sine

modulated PWM using the

PWM Interrupt Handler

Figure 8-1. Firmware Flowchart

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9 Waveforms

Figure 9-1. Output Voltage at No Load

Figure 9-2. Output Voltage and Current (100W Load)

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10 ConclusionThis application report documents the concept reference design for the DC-DC Stage and the DC-AC Convertersection that can be used in the High-Frequency Inverter using TMS320F28069, which handles the PWMgeneration and closed loop control of both the stages.

The reference design was tested for 100W load and can be further tested at higher VA ratings modifyingthe power components of the DC-AC Converter Section. The reference design is targeted for High-FrequencyInverters rated for higher VA used in the industrial segment.

11 References1. Analysis of a Voltage-fed Full Bridge DC-DC Converter in Fuel Cell Systems by A. Averberg, A. Mertens,

Power Electronics Specialists Conference, 2007. PESC 2007. IEEE.2. A Current Mode Control Technique with Instantaneous Inductor Current Feedback for UPS Inverter by H.Wu,

D.Lin, D. Zhang, K. Yao, J.Zhang, IEEE transaction, 1999.3. Power Electronics Converter, Applications and Design by Mohan, T.M. Undeland, and W.P. Robbins.4. TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064,

TMS320F28063, TMS320F28062 Piccolo Microcontrollers Data Manual (SPRS698)

12 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (January 2018) to Revision D (April 2021) Page• Updated the numbering format for tables, figures and cross-references throughout the document...................3

Changes from Revision B (June 2015) to Revision C (January 2018) Page• Updates were made in Section 6........................................................................................................................9• Updates were made in Section 7........................................................................................................................9• Update was made in Appendix A......................................................................................................................14

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A Application SchematicA.1 Application Schematic

PW

M1D

L

PW

M1D

H

PW

M2D

L

PW

M2D

H

1D

H

1D

L

2D

H

2D

L

1D

H

1D

L

2D

H

2D

L

C1

D

C2

D

C1D

C2D

ISW

AD

C

VB

AT

380

VD

C

VB

AT

5V

DC

3.3

VD

CIS

O

VB

AT

VB

AT

T2

EE

32/1

6/9

14

71

8

2

3456

910

13

C8

1

100

nF

C3

51

0u

F

C8

02

20

uF

C7

34

.7uF

D2

2A

15V

12

J4

VB

AT1 2

R6

5

4.7

E

U2

1 AM

C1100

VD

D2

8

GN

D2

5

VIN

N3

VO

UP

7V

INP

2

VD

D1

1

GN

D1

4

VO

UN

6

U2

0

TL

196

3A

SH

DN

1

IN2

GN

D3

TAB6

AD

J5

OU

T4

R7

0

4.7

E

M6

PH

P2

0N

Q2

0T

D2

3

DS

EP

8-1

2A

D1

6A

15V

12

R8

5

25m

Oh

m

D2

1

DS

EP

8-1

2A

C7

81

00

nF

L7

EE

32/1

6/9

18

23

45

67

910

1112

1314

D1

7

DS

EP

8-1

2A

R8

73

1.9

26

k

D2

0

DS

EP

8-1

2A

M9

PH

P2

0N

Q20

T

R8

61

00

k

U1

8 UC

C2

72

11

HB

2

LO

8

LI

6

HO

3H

I5

VD

D1

VS

S7

HS

4

C7

4

100

nF

R6

2

4.7

E

M7

PH

P2

0N

Q2

0T

C8

24

.7uF

M8

PH

P2

0N

Q2

0T

R6

8 4.7

E

U1

9 UC

C2

72

11

HB

2

LO

8

LI

6

HO

3H

I5

VD

D1

VS

S7

HS

4

D2

2

15V

12

D1

6

15V

12

C9

4

470

0p

F/2

kV

C8

31

00

nF

Figure A-1. DC-DC Converter Schematic (Voltage Fed Isolated Full-Bridge)

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RS

23

2

TM

ST

RS

Tn

TD

IST

DI

VT

RE

FT

DO

RT

CK

TC

KE

MU

1E

MU

0

UA

RT

1T

XD

_2

32

UA

RT

1R

XD

_2

32

UA

RT

1T

XD

_2

32

UA

RT

1R

XD

_2

32

RX

DT

XD

LE

D1

LE

D2

LE

D3

LE

D4

TX

D

LE

D1

LE

D2

LE

D3

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www.ti.com Application Schematic



15


https://www.ti.com


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Figure A-3. DC-AC Converter Schematic

Application Schematic www.ti.com




https://www.ti.com


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