-
dst
juato, Mn yl. El
ompesenbanix coodied cagesom
technology in energy compensation applications [412].According
to the operating principle, it is possible to
distinguish two major types of acac converters: (1)
directasiai
www.ietdl.org
IEdcac converters, which perform the energy conversion in aingle
stage; (2) indirect acac converters, which utilises anntermediate
dc-link. In the latter case, since conversion isccomplished by the
cascade connection of a rectier/nverter, its performance will be
limited to high commutation
SssvhT Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332oi:
10.1049/iet-pel.2014.0099better quality for both output voltages
and input currents,with a maximum voltage transfer ratio of 86.6%.
Sincethen, other concepts have been applied to matrix
convertercontrol such as space vector modulation (SVM) [15]. TheVM
strategy offers the advantage of allowing a betterelection of the
required voltage and current vectors,implifying control algorithms
and providing maximumoltage transfer ratio without the need to add
thirdarmonic modulator components. The matrix converterfrequency,
and phase that the load demands, someresearches have focused their
efforts in utilising this
introduced a high frequency PWM approach [14] enabling
by an electrical source to the requirements of
magnitude,performance of the compensator.
1 Introduction
The actual technological advance achieved in the
powerelectronics area has allowed the optimisation of
componentswithin the energy conditioning eld. The
seriescompensation device known as Dynamic Voltage Restorer(DVR)
was introduced for voltage sag mitigation, and hasbeen utilised to
unify power converter topologies able toinject compensation
voltages into distribution feeders, inorder to protect sensitive
loads from voltage disturbances.Converters based on the utilisation
of a dc-link areconsidered a solution for DVR implementation. For
example,variants of conventional DVRs that have appeared in theopen
research which include the use of a high frequencytransformer to
reduce the size of reactive components [1],devices with reduced
energy storage elements [2], multileveltopologies using ying
capacitors [3], just to mention some.All the aforementioned
topologies use the dc-link.Since the acac converters may adapt the
energy provided
frequencies. On the other hand, direct acac converters maybe
divided in three main categories: (i) AC-link converters;(ii)
Naturally Commutated Cycloconverters (NCC); (iii)Direct acac matrix
converters (MC), which are based on theforce-commutation principle.
Among these devices, the directmatrix converter exhibits several
remarkable operationalcharacteristics as input current with low
harmonic content,controllable input power factor, eliminates the
requirement ofan intermediate energy storage link, etc., aspects
that makethis kind of technology quite attractive. However,
restrictionsas the limited voltage ratio and the absence of the
dc-link,which implies input/output coupling, increase the
difcultyto dene adequate control strategies [13].Over the years
some pulse width modulation (PWM)
techniques have been developed in order to control a
matrixconverter. Originally, they were mainly concerned with
theoutput voltage control, neglecting the quality of the
inputcurrents waveform, sometimes exhibiting high harmoniccontents.
The real development of matrix convertermodulation starts in the
1980s, when Alesina and VenturiniPublished in IET Power
ElectronicsReceived on 6th February 2014Revised on 9th August
2014Accepted on 15th August 2014doi: 10.1049/iet-pel.2014.0099
Voltage compensator baseconverter without energyJose M.
Lozano-Garcia1, Juan M. Ramirez21Electrical Engineering Department,
Universidad de GuanaComunidad de Palo Blanco, Salamanca, 36885,
Guanajuat2Electrical Engineering Department, Centro de
InvestigaciCINVESTAV, Unidad Guadalajara, Av. del Bosque 1145,
CoE-mail: [email protected]
Abstract: The objective of this study is to present a voltage
cwhich can cope with common power quality problems pracquires from
the grid the necessary energy during the disturdc-link and the need
of energy storage components. A matrexposed, as well as a detailed
explanation of the proposed mveried that even when the supply
voltage exhibits unbalancnot exhibit difculties to synthesise the
compensation voltfullled. Numerical simulations and experimental
results frISSN 1755-4535
on a direct matrixorage
o, Carr. SalamancaV. de Santiago,xicode Estudios Avanzados del
Instituto Politcnico NacionalBajo, Zapopan 45019, Jalisco,
Mxico
ensator based on a matrix converter without energy storage,ted
in power distribution systems. The proposed schemece, which
eliminates the drawbacks imposed by the use of anverter study under
unbalanced input voltage conditions ised direct space vector
modulation (MDSVM). It has beenonditions and harmonic distortion,
the control strategy does, provided the restrictions imposed by the
formulation area laboratory scale prototype are presented to
validate the321& The Institution of Engineering and Technology
2015
-
ence
www.ietdl.orgperformance under unbalanced supply and
abnormalconditions has been discussed in several investigations[8,
1620]. The modulation strategy used in this paper,named modied
direct space vector modulation (MDSVM),is different from that
presented in [1618], where theconversion process has been divided
into two stages:rectication and inversion. The proposed
algorithmimplements the power conversion directly from ac-to-ac,and
it is capable to operate in adverse conditions at theconverter
input terminals. In case of unbalanced and/ordistorted supply
voltages, the algorithm modies the dutycycles by incorporating the
characteristics of the supplyvoltages, adjusting the calculated
values according to thedisturbances presented in the system
voltages. It isnoteworthy that, because of the MDSVM adaptive
nature,there is no need to perform extra
mathematicaltransformations, as symmetrical components or Fourier,
toidentify the type of disturbance and determine the requiredduty
cycles.Once the drawback of input/output coupling in matrix
converters has been overcome entirely by the novelmodulation
strategies, topologies which eliminate the,usually bulky, dclink
but retain dclinklike functional
Fig. 1 Generation of the output line-to-line and input current
refera Required states for tracking Uout(ref ) within sector Ib
Fixed vectors for current vector I in(ref ) trackingcapability
represent an interesting alternative and several ofthese have
published. A family of acac topologies basedon the traditional
matrix converter has been proposed forDVR applications, connecting
to the distribution feedereither in series [21] or in shuntseries
[22, 23]. In [24],authors present a DVR based on a traditional
back-to-backfull-bridge conguration with a ctitious dc link.
Severaltopologies based on the traditional matrix converter
[21,2528] have also been proposed for DVR applications.Moreover,
the interesting article by Prasai and Divan [29]utilises a matrix
converter with minimum energy storage.Among these matrix converter
architectures, topologiesbased on the vector-switching matrix
converter, or simplyvector-switching converter (VeSC) [30], appear
particularlyattractive given their modularity, simplicity, and ease
ofoperation. Recent research has shown the hardware viabilityof
VeSC-based DVRs [23, 31], but it addresses onlybalanced voltage sag
conditions.Owing to the direct matrix converter operative
characteristics, when it is controlled by the MDSVM, it
ispossible its use for voltage compensation purposes, in
322& The Institution of Engineering and Technology
2015applications that involve unbalanced and harmonicdistortion in
the supply voltage. Thereby, the main aim ofthis paper is to
exhibit the ability of the matrix converter togenerate unbalanced
and distorted voltages to counteract thesystem abnormal conditions.
Simulation and experimentalresults validate the analysis, and
demonstrate the feasibilityof the proposed DVR topology.
2 Matrix converter modulation algorithm
In the formal SVM, a three-phase time variant set of signals
ismapped into a complex vector in terms of the - coordinates.This
modulation technique relies on the Park transformationand the
tracking of a reference vector. Through thecombination of the two
adjacent vectors dening a sector,plus a zero component, it is
possible to synthesise therequired vector. When the input voltages
applied to thematrix converter are sinusoidal and balanced, the
analysisperformed to the resulting space vectors shows that
thecomplex plane is divided into six sectors forming a
regularhexagon. The major aim of the SVM strategy is to controlthe
output line-to-line voltage vector and the phase anglebetween the
input voltage and input current vectors within
vectors using SVM strategyany sector, Fig. 1.However, since
conventional modulation strategies are
derived under the assumption of balanced conditions
andconsidering that in applications concerning voltagecompensation
to generate controllable output voltagesbecomes a compelling
requirement, the development of ageneral modulation strategy that
encompasses typicalabnormal conditions is required.
2.1 Modied direct space vector modulation underunbalanced
conditions
For unbalanced cases, let considers a three phase voltagesystem
dened as follows
V p =va(t)vb(t)vc(t)
=
Vin sin vt( )k1 Vin sin vt
2p
3+ u1
( )
k2 Vin sin vt 4p
3+ u2
( )
(1)
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332doi:
10.1049/iet-pel.2014.0099
-
www.ietdl.org
where coefcients k1 and k2 specify the degree of unbalancein two
of the input voltage magnitudes. Likewise, byadding the angles 1
and 2, it is possible to include anglesdifferent from 2/3 among
phases. Under such conditions,the line-to-line input voltages
become
V l =vab(t)vbc(t)vca(t)
=
x1 Vin sin vt b1( )
x2 Vin sin vt + b2( )
x3 Vin sin vt + b3( )
(2)
where, xj and j ( j = 1,2,3) are functions of k1, k2, 1 and
2,Appendix 1. The input voltage Park vector is dened by [33]
U inl(t) = (vab(t)+ vbc(t) ej(2p/3) + vca(t) e j(4p/3))= U inl e
j/U inl (3)
U inl =
NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMe3
v2ab(t)+ v2bc(t)+ vab(t) vbc(t)( ) (4)
/U inl = tan12vbc(t)+ vab(t)NameMeNameMe
3
vab(t)
( )(5)
Equations (3)(5) represent the input line-to-line voltage
Parkvector, modulus and argument, respectively. It is worth
notingthat for line-to-line voltages, the homopolar or
zerocomponent is equal to zero.Substituting (2) within (3)(5), all
actual unbalanced
conditions can be taken into account, where the
balancedcondition is a particular case. Similarly, the
correspondinginput phase voltage Park vector and its zero component
isdened by [32]
U inp(t) = (va(t)+ vb(t) ej(2p/3) + vc(t) ej(4p/3))= U inp ej/U
inp (6)
Uinp0(t) = (va(t)+ vb(t)+ vc(t)) (7)
With the purpose of setting up quantitative indexes
amongarguments and modulus on Park vectors (U inp and U
inl),expressions dened as a function of the same variables forboth
vectors are required. Thus, the following relationshipsarise
U inp
=
NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMev2ab(t)+
v2bc(t)+ vab(t) vbc(t)
(8)
/U inp = tan1NameMeNameMe3
vbc(t)
2vab(t)+ vbc(t)( )
(9)
Then,
U inl = NameMeNameMe3 U inp (10)/U inl = /U inp +
p
6(11)
These two expressions can be satised independently of
theunbalance degree. The output line-to-line voltage and inputIET
Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332doi:
10.1049/iet-pel.2014.0099current vectors are dened by [32]
Uoutl(t) = (vAB(t)+ vBC(t) e j(2p/3) + vCA(t) e j(4p/3))= Uoutl
ej/Uoutl (12)
I in(t) = (ia(t)+ ib(t) ej(2p/3) + ic(t) e j(4p/3))= I in e j/I
in (13)
Expressions obtained for vectors Uoutl and I in, can be
utilisedfor both, balanced and unbalanced conditions.
Themodications imposed by unbalanced or distortedconditions on the
input voltages are manifested on theoutput xed vectors
characteristics. In this case, xedvectors still split the complex
space in six sectors; however,the maximum magnitude of each vector
may be varying.Such variations have to be considered at the moment
ofsynthesising the reference vectors, since modulus andargument of
reference vectors will depend on xed vectorsand consequently on the
active states.
2.2 Voltage reference tracking
Assuming that reference vectors Uoutl(ref ) and I in(ref )
arelocated within sector I, Fig. 1, the following relations canbe
stated, in order to determine the reference outputline-to-line
voltage vector [3336]
Uoutl(ref ) = U Ioutl mI
( )+ U IIoutl mII( )
(14)
Uoutl(ref ) = U IIIoutl mIII
( )+ U IVoutl mIV( )
(15)
where mi represents the commutation vectors duty cycle,
thatis,
mi =TiTs
i = I , II , III , IV{ } (16)
Ts is the sample time and Ti is the time elapsed while the
ithstate is on. From Fig. 1 and [3336] the followingexpressions may
be deducted
Uoutl(ref ) = U Ioutl mI
( )+ U IIoutl mII( )
= 2NameMeNameMe3
Uoutl(ref ) cos /Uoutl(ref ) p3
( ) e j(p/6)
(17)
Uoutl(ref ) = U IIIoutl mIII
( )+ U IVoutl mIV( )
= 2NameMeNameMe3
Uoutl(ref ) cos /Uoutl(ref ) + p3
( ) ej(p/6)
(18)
Each xed vector has three alternatives, Fig. 1, whichmodulus
varies instantly depending on the line-to-line inputvoltages. One
way to attain the vector Uoutl(ref )is selectingthe commutation
states that produce the largest modulus. Asa consequence, the
selected commutation states depend onthe position of vector U inp
and consequently on the inputline-to-line voltages according to
(9), which also allows toestablish a relationship between the input
line-to-line323& The Institution of Engineering and Technology
2015
-
voltages and the sector where U inp is located,
despiteunbalanced conditions.Rearranging (17) and (18) in terms of
the input line-to-line
voltage vector
II( ) IV( )
mIII =2NameMeNameMe3
Uoutl(ref )
U inl
cos /Uoutl(ref ) +p( ) cos p+/I in(ref )( )
NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMe2 + w
www.ietdl.orgmI =2NameMeNameMe3
Uoutl(ref ) U inl
cos /Uoutl(ref )
p
3
( ) cos p
3+/I in(ref )
( )cos uin
(25)
mII =2NameMeNameMe3
Uoutl(ref )
U inl
cos /Uoutl(ref )
p
3
( ) cos p
3/I in(ref )
( )cos uin
(26)
Vout 1
3NameMeNameMe2
Vin
NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeg+
l+
NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeg2 + l
(I in(ref ) = I in mII + I in mIV (21)
Iin(ref ) = I Iin mI
( )+ I IIIin mIII( )
(22)
After mathematical simplications, and in order to avoid theuse
of current parameters [3336],
mII sinp
6/I in(ref )
( ) mI sin
p
6+/I in(ref )
( )= 0 (23)
mIV sinp
6/I in(ref )
( ) mIII sin
p
6+/I in(ref )
( )= 0
(24)
2.4 Duty cycles computation
Solving the equations set (19), (20) and (23), (24) [32],
theduty cycles becomeUoutl(ref )
cos /Uoutl(ref ) p3( )
= U inl cos /U inl( )mI U inl cos /U inl 4p3
( )mII
(19)
Uoutl(ref )
cos /Uoutl(ref ) + p3( )
= U inl cos /U inl( )mIII U inl cos /U inl 4p3
( )mIV
(20)
2.3 Current tracking
Similarly, the input reference current I in(ref ) can be
determinedby [3336]324& The Institution of Engineering and
Technology 2015 3 3cos uin
(27)
mIV =2NameMeNameMe3
Uoutl(ref )
U inl
cos /Uoutl(ref ) +
p
3
( ) cos p
3/I in(ref )
( )cos uin
(28)
The last expressions are valid within the intervals
p6, /Uoutl(ref ) ,
p
6, p
6, /I in(ref ) ,
p
6(29)
It is necessary to verify that
mI + mII + mIII + mIV 1 (30)
If the sum of duty cycles is less than one, the use of zero
statesis required. Substituting (25)(28) into (30) results
[32],
Uoutl(ref )
NameMeNameMe3
2 U inl cos uin
cos /Uoutl(ref )
( ) cos /I in(ref )
( )(31)
Considering that for each sector it holds that
cos/I in(ref )
[ ]max
= 1 and cos/Uoutl(ref )[ ]
max= 1, from (8),
the inputoutput voltage relationship q = (Vout/Vin)( )
canbe established (see (32))
where variables , l and j are specied in Appendix 1. From(32) it
may be observed that U in
is a time variant quantitywhich depends on the unbalance degree.
Besides, it can benoted that the maximum voltage relationship is
reachedwhen cosin = 1. Then, (see (33) at the bottom of the
page).
Equation (33) implies that under unbalanced conditions oninput
voltages, the reference output voltage vector is at themost 0.866
times the minimum value of the input voltagePark vector. For
example, during balanced conditions themaximum balanced output
voltage vector that may begenerated, corresponds to 0.866 times the
maximum circlethat can be inscribed inside the hexagon, Fig. 2a. On
theother hand, if a sag of 50% takes place on input phase b,the
input vector describes an ellipse, thus reducing theavailable locus
for the output voltage generation. In thisparticular case, the
maximum magnitude of the balancedoutput voltage that can be
generated is reduced by a factorof 2/3, Fig. 2b. The latter also
can be applied in the case ofharmonic distortion present on input
voltages, where, aslong as the output voltage vector magnitude
remains belowthe 86.6% of the input voltage vector magnitude at
anytime, compensation can be achieved.
NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMe2
2gl sin 2vt + l g
w
{ }) cos uin (32)IET Power Electron., 2015, Vol. 8, Iss. 3, pp.
321332doi: 10.1049/iet-pel.2014.0099
-
ined
www.ietdl.orgFinally, taking into account a unitary input power
factor,the duty cycles become [32]
mI = Uoutl(ref )
U inl 2 cos /Uoutl(ref ) p3
( ) (vbc(t) vab(t))
(34)
mII = Uoutl(ref )
U inl 2 cos /Uoutl(ref ) p3
( ) (vca(t) vbc(t))
(35)
mIII = Uoutl(ref )
U inl 2 cos /Uoutl(ref ) + p3
( ) (vbc(t) vab(t))
(36)
Fig. 2 Comparison of the maximum balanced output voltages obtaa
Voltage vectors for balanced input voltage conditionb Voltage
vectors for unbalanced condition (50% sag on phase-b)mIV =
Uoutl(ref )
U inl 2 cos /Uoutl(ref ) + p3
( ) (vca(t) vbc(t))
(37)
From the above expressions, the incorporation of the
supplyvoltages characteristics into the computation of the
dutycycles makes the modulation process adaptive todisturbances at
the input voltages. The relevance of thisstrategy resides on the
fact that it can prevent theundesirable features of the supply
voltages frompropagating onto the output voltages.The main
advantages of the proposed MDSVM technique
is that it allows: (i) fast and accurate generation of
balanced,unbalanced and distorted reference output voltages,
despitethe input voltages condition; (ii) output voltages and
inputcurrents with acceptable harmonic content; (iii) magnitude
Vout 1
3NameMeNameMe2
Vin
NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeg+
l+
NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeg2 +
l2
(
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332doi:
10.1049/iet-pel.2014.0099and frequency control in output voltages;
(iv) controllableinput power factor; (v) implementation with only
twoline-to-line voltage measurements and without extramathematical
transformations.
3 Matrix converter as voltage compensator
The operational benets of the MDSVM technique allows
theincorporation of the matrix converter technology into
theconventional DVR conguration. The system shown inFig. 3, is
utilised to test the developed algorithm. Theproposed DVR topology
is intended for compensatingbalanced and unbalanced conditions, as
well as harmonicdistortion in the voltage supply, with the purpose
ofreducing operational complexity since energy storagedevices are
not required. In this conguration, the energycomes from the
incoming supply. During voltage sags, thematrix converter input
voltage drops proportionally; hence,
under balanced and unbalanced conditions on input voltagesthe
maximum injected voltage would become,
V inj
NameMeNameMe3 /2 a| | (38)where V inj is the injected voltage
vector in pu, and a is avoltage sag factor dened as the ratio
between the voltageduring the sag and the load rated voltage. For
example, ifthe supply voltage falls to 0.5 pu at rated load,
themaximum possible voltage, injected by the matrixconverter, will
be 0.432 pu, which would be unsatisfactory.Hence, the ability to
compensate for symmetric voltage sagswould be, theoretically,
limited up to 0.45 pu voltage drops.
3.1 Voltage controller
The control strategy used to test the proposed
compensatortopology, as it was structured for implementation in
aneZdsp board, is displayed in Fig. 4. The primary control
NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMe+
w2 2gl sin 2vt + l g
w
{ })max
(33)
325& The Institution of Engineering and Technology 2015
-
Fig. 3 Topology of the voltage compensator based on a matrix
converter.
www.ietdl.orgstructure is based on the combination of an
open-loop supplyvoltage feed-forward control and a closed-loop
PI-based loadvoltage feedback control. The feed-forward
componentprovides the required transient response at the beginning
ofthe disturbance. The closed-loop voltage feedback is addedto
minimise any steady state error in the fundamentalcomponent. The
voltage compensator is synchronised to thegrid by a phase-locked
loop (PLL). A relatively slow PLLis used to limit the inuence of
harmonics andnon-symmetrical input voltages. At the instant
thedisturbance occurs, the difference between the voltagereference
and the measured voltage at the supply terminalsFig. 4 Control
diagram for the voltage compensator
326& The Institution of Engineering and Technology 2015is
utilised for the feed forward loop to determine the baseof the
voltage to be injected. The actual load voltage iscompared with the
rated load voltage and the error is fed toa conventional PI-based
voltage controller. Finally, outputsfrom both main control branches
are combined to generatethe signal references to the compensator,
which are thentransformed into coordinates in order to implement
theMDSVM and compute the duty cycles. The injectedvoltages must
satisfy the MDSVM restriction
Uout(ref )
MAX
NameMeNameMe3
/2 U inl
MIN (39)IET Power Electron., 2015, Vol. 8, Iss. 3, pp.
321332doi: 10.1049/iet-pel.2014.0099
-
3.2 Simulations
Fig. 3 depicts the schematic of the matrix converter-basedDVR. A
second order RLC lter is used at the inputterminals of the
converter to improve the input currentswaveform. A second order RLC
lter is utilised at theoutput terminals of the matrix converter in
order to lter theswitching harmonic components in the generated
voltages.The combined effect of the non-ideal ac source and
thethree phase line is represented by the inductance Ls.Dynamic
performance of the whole system is veried bynumerical simulation
using PSCAD/EMTDC. Table 1summarises the system key parameters used
for thesimulation.The cut-off frequency of the lters can be
obtained by
fo =1
2pNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeLf Cf
(40)Therefore, the cut-off frequencies are 1.073 and 0.464
kHzfor input and output lters, respectively; which are adequateto
improve the quality of the input currents and outputvoltages, since
the commutation frequency in the converter
The Park vectors U inl and Uoutl on the complex plane
aredisplayed in Fig. 5 and Fig. 6a displays the input voltagesin
time domain. In this case, voltage imbalance is exhibitedon both
sets of terminals in the matrix converter.Nonetheless, as long as
the vector Uoutl remains inside thevector U inl loci, the control
algorithm will be able tosynthesise the output-voltage. Figs. 6 and
7 depict voltageand current waveforms during the voltage sag
period. Notethat the RL load acts as a low-pass lter, reducing
almostall the current harmonic components. Likewise, the
matrixconverter generates a set of unbalanced voltages to
achieve
Table 1 Parameters for simulation
Cif: input filter capacitor 10 FLif: input filter inductor 2.2
mHRif: input filter resistor 50 Cof: output filter capacitor 4.7
FLof: output filter inductor 25 mHRof: output filter resistor 100
Rload: load resistor 120 Lload: load inductor 213 mHVload: maximum
load voltage 113.13 VIload: maximum load current 0.7835 A
www.ietdl.orgis 6 kHz.The matrix converter-based compensator is
utilised for
voltage sags and swells compensation, as well as
harmonicssuppression.The state-space equations for the matrix
converter-based
DVR system becomes [32]
dx
dt= f (x, u) (41)
where x and u are the state variables and inputs, respectively;f
(x, u) is the non-linear function vector dened in appendix2. The
state variables included are the input current, theinput lter, the
output lter, and the RL load, in the d-qreference frame.In the rst
simulation case, unbalanced voltage sag of 40%
is applied to input phase b, within the interval 0.4 s0.5 s,
inorder to evaluate the compensator near its operational limit.
Fig. 5 Park vectors U inl and U outl on the complex planea Input
and Output line-to-line voltage vectors in complex spaceb
Line-to-line voltage vectors magnitude.IET Power Electron., 2015,
Vol. 8, Iss. 3, pp. 321332doi: 10.1049/iet-pel.2014.0099the
compensation, which provokes a distortion in thecurrents drawn by
the converter and consequently thesystem currents are distorted as
well, Fig. 7. The totalharmonic distortion (THD) of output voltages
and systemcurrents during the disturbance are exhibited in Fig. 8.
Thecontrol algorithm has accomplished to reduce theimbalanced
percent from 15.38% at the input voltages to0.42%, value which
fulls the NEMA criterion aboutpermitted imbalance percent of 1.
Besides, each outputphase voltage presents an average THD lower
than 3%during the fault, which falls inside the
guidelinesestablished in the IEEE-519 for general power systems
ofmedium voltage.Once evidenced the capacity of the proposed
topology to
operate in a satisfactory way under unbalanced conditions,its
behavior was veried under the presence of harmoniccomponents on the
input voltage (results are omitted for thesake of brevity)
[32].327& The Institution of Engineering and Technology
2015
-
Fig. 7 Simulation results: Compensator response under unbalanced
voltage variationFrom top to bottoma Load currentsb Phase a matrix
converter input currentc Phase a supply system current
Fig. 6 Simulation results: Compensator response under unbalanced
voltage variationFrom top to bottoma Supply voltagesb Compensation
voltagesc Load voltages
www.ietdl.org
328& The Institution of Engineering and Technology 2015
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332doi:
10.1049/iet-pel.2014.0099
-
3.3 Experimental results
A laboratory-scale prototype has been assembled usingIGBTs in
the common collector conguration. The control
algorithm has been implemented using the xed-point
DSPTMS320F2812. Voltage sag correction and harmonicsuppression are
veried by means of several experimentaltests.
Fig. 8 Simulation resultsa Load voltages THDb System supply
currents THD
www.ietdl.orgFig. 9 Experimental results: Supply and load
voltages during unbalanca Pre-sag conditionb Sag condition (20
V/div, 5 ms/div)c Pre-sag conditiond Sag condition (20 V/div, 10
ms/div)
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332doi:
10.1049/iet-pel.2014.0099ed voltage sag test
329& The Institution of Engineering and Technology 2015
-
www.ietdl.orgLoad voltage and current presented in Fig. 9
exhibits thecompensator performance for an unbalanced case, where
a37.5% voltage sag is applied to phase-a. Similarly to thesimulated
waveforms, the load voltages are fullymaintained, which demonstrate
the effectiveness of thematrix converter as compensator. The
distortion on the loadvoltages is partly because of the inductors
saturation used inboth lters, input and output, Fig. 3, because low
frequencyinductors were used. Besides, an important factor
toconsider is the modulation index. Before the sag takesplace, a
very low modulation index is being used; then, thedistortion is
more notable during the pre-sag condition.During the disturbance,
currents on the supply system aredistorted as expected, but the
load currents remain almostinvariant.The following study involves
harmonic distortion in the
supply voltages, because of a non-linear load, a diodebridge
rectier plus a resistive load. After the compensationtakes place,
the fth and seventh harmonic components arereduced by a factor of
20 and 15 dB, respectively; thus,THD is reduced too. Fig. 10
displays voltages and currentswith and without compensation. Note,
under compensation,that the load voltages include some high order
harmoniccomponents, which may be generated by the saturation ofthe
output lter inductors. Nevertheless, the effects of theseharmonics
may be tolerable for the load.
Fig. 10 Experimental results: Supply voltages (top) and load
currentsa Without compensationb With compensation (20 V/div, 5
ms/div)c Without compensationd With compensation (0.5 A/div, 5
ms/div)
330& The Institution of Engineering and Technology 20154
Conclusions
This paper proposes a novel voltage compensator topologyusing a
direct matrix converter without energy storage, tocope with power
quality issues presented in distributionsystems. The main
contributions of this paper aresummarised in the following:
The mathematical development of the MDSVM techniqueto control
the matrix converter operation. A detailed analysisof the acac
matrix converter under unbalanced conditions ispresented. The
proposed technique allows the converter togenerate a totally
controllable output voltage despite theadverse existing conditions
in the input voltages. The design of a novel multi-functional DVR
topology,proposed to improve the power quality in
distributionsystems. Development of a detailed model of the DVR
topology inorder to evaluate their dynamic behavior
throughtime-domain PSCAD/EMTDC simulations. Development of
mathematical models for the DVRtopology intended for future
stability and power owcontrol analysis. Design and implementation
of a laboratory-scale prototypeof the matrix converter-based DVR to
validate the MDSVMtechnique operation, which was implemented in
a
(bottom) during the distorted voltage test
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332doi:
10.1049/iet-pel.2014.0099
-
IET Electr. Power Appl., 2007, 1, (3), pp. 439448
16 Saribulut, L., Tmay, M.: Robust space vector modulation
technique
30 Venkataramanan, G.: Three-phase vector switching converters
forpower ow control, Proc. Inst. Elect. Eng.Elect. Power Appl.,
www.ietdl.orgfor unbalance voltage disturbances, Electr. Power
Syst. Res., 2010,80, pp. 13641374
17 Jahangiri, A., Radan, A., Haghshenas, M.: Synchronous control
ofindirect matrix converter for three phase power conditioner,
ElectricPower Syst. Res., 2010, 80, pp. 857868
18 Kumar, V., Joshi, R.R.: DSP-Based matrix converter operations
undervarious abnormal conditions with practicality. Proc. Int.
Conf., NewDelhi, December 2006, pp. 14
19 Rivera, M., Rojas, C., Rodriguez, J., Espinoza, J.: Methods
of sourcecurrent reference generation for predictive control in a
direct matrixconverter, IET Power Electron., 2013, 6, (5), pp.
89490114 Alesina, A., Venturini, M.: Solid-state power conversion:
a Fourieranalysis approach to generalized transformer synthesis,
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modulationstrategies: A new general approach based on space-vector
representationof the switch state, IEEE Trans. Ind. Electron.,
2002, 49, pp. 370381DSP-based board eZdsp-TMS320F2812, along with a
fourstep commutation strategy.
The incorporation of matrix converter technology intothe
conventional DVR conguration may result in acost-effective and
multi-functional solution. Simulated andexperimental results
presented show the feasibility of theproposed topology. This
analysis may be useful to study theuse of the matrix converter in
future applications.
5 Acknowledgment
This work was supported by PROMEP under
103.5/13/7048project.
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7 Appendix 1
x1
=NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMe1+
k21 2k1 sin u1
p
6
( )
x2
=NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMek21
+ k22 2k1k2 sin u1 u2
p
6
( )
x3
=NameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMeNameMe1+
k22 2k2 sin u2
5p
6
( )
b1 = tan1k1 cos u2 + (5p/6)
( )1 k1 sin u1 (p/6)
( )( )
b2 = tan1k1 cos u2 + (5p/6)
( ) k2 cos u2 + (p/6)( )k1 sin u1 (p/6)
( ) k2 sin u2 (5p/6)( )( )
b3 = tan1k2 cos u2 + (p/6)
( )k2 sin u2 (5p/6)
( ) 1( )IECON, November 2006, pp. 1938194329 Prasai, A., Divan,
D.: Zero-energy sag corrector with reduced device
count, IEEE Trans. Power Electron., 2009, 24, (6), pp.
1646165320 Blaabjerg, F., Casadei, D., Klumpner, C., Matteini, M.:
Comparison oftwo current modulation strategies for matrix converter
under unbalancedinput voltage conditions, IEEE Trans. Ind.
Electron., 2002, 49,pp. 289296
21 Wang, B., Venkataramanan, G.: Dynamic voltage restorer
utilizing amatrix converter and ywheel energy storage, IEEE Trans.
Ind.Appl., 2009, 45, (1), pp. 222231
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voltage restorerbased on matrix converters. Proc. IEEE Mod.
Electric Power SystemMEPS, Wroclaw, Poland, September 2010, pp.
17
23 Ramirez, J.M., Garcia-Vite, P., Lozano, J.M., Mancilla-David,
F.:Dynamic voltage restorers based on ac-ac topologies. Proc.
IEEEPower and Energy Society General Meeting, July 2012, pp. 17
24 Babaei, E., Kangarlu, M.F.: Voltage quality improvement by a
dynamicvoltage restorer based on a direct three-phase converter
with ctitious dclink, IET Gen., Transm., Distrib., 2011, 5, (8),
pp. 814823
25 Subramanian, S., Mishra, M.: Interphase ACAC topology for
voltagesag supporter, IEEE Trans. Power Electron., 2010, 25, (2),
pp. 514518
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voltagerestorers without DC link. Proc. IEEE ISIEA, October 2009,
(2),pp. 10161021
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voltagerestorer based-on matrix converter. Proc. 45th Int. UPEC,
August/September 2010, pp. 16
28 Perez, J., Cardenas, V., Moran, L., Nunez, C.: Single-phase
ACACconverter operating as a dynamic voltage restorer (DVR). Proc.
IEEE331& The Institution of Engineering and Technology 2015
-
g = x1 cos b1( )+ x2k1 cos b2( ) cos u1 2p3
( )
+ x3k2 cos b3( )
cos u2 +2p
3
( )
l = x2k1 sin b2( )
sin u1 2p
3
( )+ x3k2 sin b3
( )sin u2 +
2p
3
( )
w = x1 sin b1( )+ x2k1 sin b2 + u1 2p3
( )
+ x3k2 sin b3 + u2 +2p
3
( )
8 Appendix 2
f (x, u) = [ f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12]T
f1 = viqs +1
Lsvds Rif ids idif idload
( ) vdi[ ]
f2 = vids +1
Lsvqs Rif iqs iqif iqload
( ) vqi
[ ]
f3 = viqif +RifLif
ids idif idload( )
f4 = vidif +RifLif
iqs iqif iqload( )
[
+vqo iqof +Vin
UiRofvqo
vqinjRof
( )}]
f6 = vvdi +1
Cifiqs iqload
vqiU2i
[
vqo iqof +Vin
UiRofvqo
vqinjRof
( ){
+vdo idof +Vin
UiRofvdo
vdinjRof
( )}]
f7 = viqof +1
Lof
VinUi
vdo
( ) vdinj
Lof
f8 = vidof +1
Lof
VinUi
vqo
( ) vqinj
Lof
f9 = viqinj +idofCof
+ 1RofCof
VinUi
vdo
( ) vdinj
RofCof idload
Cof
f10 = v idinj +iqofCof
+ 1RofCof
VinUi
vqo
( ) vqinj
RofCof iqload
Cof
f11 = v iqload +RifLload
ids idif idload( )
+ 1Lload
vdi + vdinj( )
idloadRif + Rload
Lload
f12 = vidload +RifLload
iqs iqif iqload( )
www.ietdl.orgf5 = vvqi + Cifids idload
vdiU2i
vdo idof +Vin
UiRofvdo
vdinjRof
( ){332& The Institution of Engineering and Technology
2015+Lload
vqi + vqinj iqload if loadLload11 ( ) R + RIET Power Electron.,
2015, Vol. 8, Iss. 3, pp. 321332doi: 10.1049/iet-pel.2014.0099