TEST REPORT Silanna Semiconductor Proprietary and Confidential Page 1 Patents: www.PowerDensity.com/patents Document 11075 Ver. 1.0 TEST REPORT SZ-RD12-65W EVB Description This test report of SZ-RD12-65W evaluation board describes a 65 W universal input offline power supply with programmable output voltage (5 V/3.25 A, 9 V/3.25 A, 15 V/3.25 A, 20 V/3.25 A). The power supply uses SZ1130 (Flyback PWM controller with integrated active clamp circuit) IC, GaN Systems GS-065-008-1-L (650 V E-mode GaN Transistor), and Weltrend WT6633P USB PD controller. This design shows the high-power density and efficiency that can be achieved due to the high level of integration of the SZ1130 controller. This document contains the power supply specification, schematic, bill-of-materials, transformer documentation, printed circuit layout, and performance data. Key Specs Schematics Input 90-265 Vac Output Voltages 5 V, 9 V, 15 V, 20 V Max Output Current 3.25 A Max Output Power 65 W Output Port USB-PD Efficiency > 94% Full Power Efficiency SZ1130 Features ▪ Integrated High Voltage Active Clamp FET, Active Clamp Driver, and Start-up Regulator ▪ Capable of Over 94% Efficiency ▪ Flat Efficiency Across Universal (90-265 VAC) Input Voltage and Load ▪ Tight Switching Frequency Regulation for Improved Input EMI Filter Utilization ▪ Up to 140 kHz Switching Frequency Operation ▪ OptiMode TM Cycle-by-Cycle Adaptive Digital Control ▪ Multi-Mode Operation (Burst Mode, Quasi- Resonant, Valley Mode Switching) ▪ Advanced Valley Mode Switching for low EMI ▪ Self-Tuning Valley Detection ▪ OTP, UVLO, OVLO, PCL, OPP and OSC Protections ▪ <50mW No Load Power Consumption of the IC ▪ Up to 65 W Output Power Applications ▪ High-Power-Density USB-PD AC/DC Power Supplies VBULK_S (15) OOVP_S (16) V5OUT (13) GND (6) BOOT_CL (4) FB (12) ISENSE COMPARATORS OptiMPulseLinkEncoder/Decoder Startup Regulator VISNS_PEAK VOOVP_TH OOVP COMPARATOR SW (3) V10 (7) ISNS (11) GATE (8) Main Switch Driver Active Clamp Driver Digital OptiModeVBULK COMPARATORS VBULK_REFs TEMP (9) Primary GaN Systems GS-065-008-1-L Active Clamp FET V10 VNTCTH/ VNTCR VAUX_S (14) NTC COMPARATOR QR COMPARATOR CLAMP (1) Sync Rec Secondary A D C V5OUT VBULK RFB CV5OUT CA Regulator 1 CC * RC2 RC1 RB2 RB1 CBST1 RSENSE RA2 RA1 CV10 Secondary FET COUT VOUT NC (10) VOUT CBULK RT2 DAUX * DBST RT1 DCL * CB2 CA2 RDAMP * VA ZBST Auxiliary 5V LDO WAKE COMPARATOR VWAKE_FT H / VWAKE_RTH RGATE * DGATE RBST CBST2 CBST3 RF CF Bootstrap Charging Circuit * -t 0 [n] Silanna Semiconductor SZ1130-00
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TEST REPORT Silanna Semiconductor Proprietary and Confidential Page 1 Patents: www.PowerDensity.com/patents Document 11075 Ver. 1.0
TEST REPORT SZ-RD12-65W
EVB Description
This test report of SZ-RD12-65W evaluation board
describes a 65 W universal input offline power supply with
programmable output voltage (5 V/3.25 A, 9 V/3.25 A, 15
V/3.25 A, 20 V/3.25 A). The power supply uses SZ1130
(Flyback PWM controller with integrated active clamp
circuit) IC, GaN Systems GS-065-008-1-L (650 V E-mode
GaN Transistor), and Weltrend WT6633P USB PD
controller. This design shows the high-power density and
efficiency that can be achieved due to the high level of
integration of the SZ1130 controller.
This document contains the power supply specification,
Silanna Semiconductor Proprietary and Confidential Page 2 For more information: www.PowerDensity.com Document 11075 Ver. 1.0
Warning
Disclaimers:
1. Caution – High Voltage Operation: Lethal high voltages are present when this evaluation board ispowered from AC mains. Improper contact with high voltages could lead to electrical shock, burnand/or fire hazards, risking property damage, personal injury, and death.
2. Evaluation Purpose Only: This evaluation board is intended for evaluation purpose only and not forcommercial use. Care must be taken when testing the board, and an isolation transformer should beutilized.
3. Patents: The evaluation board design, along with circuits shown in this test report, may be covered byone or more U.S. and foreign existing/pending patents.
Silanna Semiconductor Proprietary and Confidential Page 4 For more information: www.PowerDensity.com Document 11075 Ver. 1.0
Power Supply Specifications
The evaluation board performance data presented in this report exceeds the power supply specifications listed in the following table.
Description Symbol Min. Typ. Max. Units Comments
Input
Voltage Vin 90 115/230 265 VAC 2 Wire Input
Frequency fline 47 60/50 63 Hz
Efficiency
5 V/3.25 A η5V/3.25A 90 %
@ 115 Vac, 25 °C ambient
9 V/3.25 A η9V/3.25A 93 %
15 V/3.25 A η15V/3.25A 93 %
20 V/3.25 A η20V/3.25A 93 %
4-Point Ave Efficiency
5 V ηave_5V 82.37 %
CoC version 5 tier 2 4-point (25%, 50%, 75%,
100%) average efficiency
9 V ηave_9V 87.60 %
15 V ηave_15V 88.99 %
20 V ηave_20V 89.16 %
No-Load Input Power
Pin 75 mW @ 230 Vac, 25 °C
ambient
Programmable Output Voltage
VOUT 5 20 V
Environmental Conducted EMI
Meets CISPR22B/EN55022
Ambient Temperature
TAMB 0 40 °C No airflow, sea level.
NOTE: The circuit board needs to be evaluated for additional tests, such as ESD and Line Surge to use the evaluation board design presented in this test report as a charger/adapter. Furthermore, the layout of the board needs to be adjusted according to the target shape and form factor of the end application.
Silanna Semiconductor Proprietary and Confidential Page 16 For more information: www.PowerDensity.com Document 11075 Ver. 1.0
Performance Data
Electrical Data
Efficiency
DoE Level VI and CoC Version 5 Tier-2 4-point (25%, 50%, 75%, 100%) average efficiency, along with CoC Version 5 Tier-2 10% load efficiency requirements.
Table 4: Load Efficiency Requirements
Vout/Iout DoE Level VI 4-Point
Average Efficiency
CoC V5 Tier-2 4-Point
Average Efficiency CoC V5 Tier-2 10% Efficiency
5 V/3.25 A 81.88% 81.84% 72.99%
9 V/3.25 A 86.87% 87.30% 77.60%
15 V/3.25 A 87.77% 88.85% 78.99%
20 V/3.25 A 87.54% 89.16. % 79.16%
115 Vac 4-point average efficiency (measured after the USB-PD disconnect FET)
Silanna Semiconductor Proprietary and Confidential Page 21 For more information: www.PowerDensity.com Document 11075 Ver. 1.0
Key Waveforms
The key waveforms for the worst case voltage conditions as seen by the primary side Gan Transistor and secondary side MOSFET are shown below. Due to the active clamp operation of SZ1130, there is practically no voltage spike at the switching node as shown in the following figures.
Vin=265 Vac, Vout=20 V, Iout=3.25 A, Vds_pri (max) = 568V
Vds_sec (max) = 77V
Vin=265 Vac, Vout=20 V, Iout=0 A, Vds_pri (max) = 548V
Vds_sec (max) = 79V
Figure 12: Voltage stress on the primary and secondary side MOSFET during worst case operating conditions
Silanna Semiconductor Proprietary and Confidential Page 22 For more information: www.PowerDensity.com Document 11075 Ver. 1.0
Conducted EMI Scans
The following conducted EMI measurements demonstrate more than 6 dB margin is maintained under all input (115 Vac/ 230 Vac) and output voltage (5 V/ 9 V/ 15 V/ 20 V) conditions with floating output.
Vin=115 Vac, Vout=5 V, Iout=3.25 A Vin=115 Vac, Vout=9 V, Iout=3.25 A
Vin=115 Vac, Vout=15 V, Iout=3.25 A Vin=115 Vac, Vout=20 V, Iout=3.25 A
Silanna Semiconductor Proprietary and Confidential Page 24 For more information: www.PowerDensity.com Document 11075 Ver. 1.0
Thermal Measurements
The key thermal IR camera pictures and component temperatures are shown below for 90Vac/20V/65W (worst-case) operating condition after 1hr bake time. The maximum component temperatures is lower than 95 0C.
RefDes Description 90VAC 265VAC
U1 SZ1130-00 88.5°C 76.6°C
BR1 Bridge Rectifier 93.4°C 59.4°C
T1 Transformer 94.4°C 89.5°C
Q2 Primary GaN Transistor 91.1°C 94.9°C
Q1 Secondary SR MOSFET 86.3°C 81.6°C
Vin=90 Vac, Vout=20 V, Iout=3.25 A (top) Vin=90 Vac, Vout=20 V, Iout=3.25 A (bottom)
Vin=90 Vac, Vout=20 V, Iout=3.25 A (side left) Vin=90 Vac, Vout=20 V, Iout=3.25 A (side right)
Figure 14: Thermal IR pictures after 1hr bake time at 90Vac/20V/65W.