VLSI/FPGA Design and Test Flow with Mentor Graphics CAD Toolsnelson/courses/elec4200/ClassMaterial/NelsonF... · VLSI/FPGA Design and Test Flow with Mentor Graphics CAD Tools ...

VLSI/FPGA Design and Test Flow

with Mentor Graphics CAD Tools

Victor P. Nelson

ASIC Design Flow

BehavioralModel

VHDL/Verilog

Gate-LevelNetlist

DFT/BIST& ATPG

VerifyFunction

VerifyFunction

SynthesisFront-EndDesign

Transistor-LevelNetlist

PhysicalLayout

Map/Place/Route

Verify Function& Timing

Verify Timing

DRC & LVSVerification

IC Mask Data/FPGA Configuration File

Standard Cell IC & FPGA/CPLD

Test vectors Full-custom IC

Back-EndDesign

Physical Design – FPGA (same front end design)

Map to FPGA LUTs, FFs, IOBs

Component-Level Netlist

Xilinx “ISE”Altera “Max Plus 2”

Place & Route

Configuration File

Generate Programming

Data

FPGA/PLD Technology

FilesUser-SpecifiedConstraints

Simulation Model

Generate Timing Model

ASIC CAD tools available in ECE� Modeling and Simulation

� Modelsim, ADVance MS/Questa, Eldo, Mach TA/ADiT� Verilog-XL, NC_Verilog, Spectre

� Design Synthesis (digital)� Leonardo Spectrum, Precision RTL� Design Compiler (Synopsys), RTL Compiler (Cadence)

� Design for Test and Automatic Test Pattern Generation� Design for Test and Automatic Test Pattern Generation� DFT Advisor, Fastscan, Flextest

� Schematic Capture & Design Integration� Design Architect-IC� Design Framework II (DFII) – Composer

� Physical Layout� IC Station� SOC Encounter, Virtuoso

� Design Verification� Calibre� Diva, Assura

Red – Mentor GraphicsBlue – Cadence/Synopsys

Mentor Graphics Analog/Mixed-Signal IC

Design FlowTechnology-specific netlist from front-end tools

Mentor Graphics CAD Tools (select from “eda” list in user-setup on the Sun network)

� ICFlow** – For custom & standard cell IC designs� IC flow tools (Design Architect-IC, IC Station, Calibre)� Digital/analog/mixed simulation (Modelsim,ADVance MS,Eldo,MachTA)� HDL Synthesis (Leonardo)� ASIC Design Kit (ADK) - Support files for various technologies

� DFT� ATPG/DFT/BIST tools (DFT Advisor, Flextest, Fastscan)� ATPG/DFT/BIST tools (DFT Advisor, Flextest, Fastscan)

� Modelsim** (HDL Simulation)� FPGA (FPGA Advantage, Modelsim, Leonardo)

� *Xilinx/ISE (Xilinx FPGA/CPLD - back end design)

� *QuartusII (Altera FPGA/CPLD - back end design)

� *Ims/6.2 (IMS chip tester)

** Installed on both Solaris and Linux servers* Vendor-Provided (Not Mentor Graphics) Tools

Mentor Graphics ASIC Design Kit (ADK)

� Technology files & standard cell libraries� AMI: ami12, ami05 (1.2, 0.5 μm)� TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μm)

� IC flow & DFT tool support files:� Simulation

� VHDL/Verilog/Mixed-Signal models (Modelsim/ADVance MS)� VHDL/Verilog/Mixed-Signal models (Modelsim/ADVance MS)� Analog (SPICE) models (Eldo/Accusim)� Post-layout timing (Mach TA)

� Synthesis to standard cells (LeonardoSpectrum)� Design for test & ATPG (DFT Advisor, Flextest/Fastscan)� Schematic capture (Design Architect-IC)� IC physical design (standard cell & custom)

� Floorplan, place & route (IC Station)� Design rule check, layout vs schematic, parameter extraction (Calibre)

Xilinx/Altera FPGA/CPLD Design

� Technology files & libraries for front-end design with Mentor Graphics tools� Schematic symbols for Design Architect

� Simulation models for Quicksim II, Quicksim Pro

� Synthesis library for Leonardo� Synthesis library for Leonardo

� Vendor tools for back-end design (map, place, route, configure, timing)

� Xilinx Integrated Software Environment (ISE)� Xilinx XST can synthesize the design from VHDL or Verilog (instead of Leonardo)

� Altera Quartus II & Max+Plus2

Front-end design & verification

Create Behavioral/RTL HDL Model(s)

Simulate to VerifyFunctionality

Modelsim(digital)

VHDL-AMSVerilog-A

ADVance MS (analog/mixed signal)

VHDLVerilog

SystemC

Functionality

SynthesizeCircuit

Synopsys -Design CompilerLeonardo Spectrum,Xilinx ISE (digital)

(digital) (analog/mixed signal)

Technology Libraries

Technology-Specific Netlistto Back-End Tools

Simulate to VerifyFunction/Timing

VITALLibrary

Design Constraints

ADVance MSDigital, Analog, Mixed-Signal Simulation

WorkingLibrary

Design_1Design_2

VITAL

IEEE 1164 ResourceLibraries

VHDL,Verilog,VHDL-AMS, Verilog-A,

SPICE Netlists SPICEmodels

ADVance MSSimulationSetup

EZwaveor Xelga

InputStimuli

Eldo,Eldo RF ModelSim

View ResultsMach TAMach PA

Analog(SPICE) Digital

(VHDL,Verilog)

Mixed Signal(VHDL-AMS,Verilog-A)

ADVance MS : mixed-signal simulation

A/D converter

digital

analogVHDL-AMS

ADVance MS: mixed Verilog-SPICE

Verilog top(test bench)

SPICEsubcircuit

Automated Synthesis with

Leonardo Spectrum

VHDL/Verilog Behavioral/RTL ModelsTechnology

Synthesis Libraries

Leonardo Spectrum(Level 3)

FPGA

ASIC

Technology-SpecificNetlist

DesignConstraints

VHDL, Verilog, SDF,EDIF, XNF

Level 1 – FPGALevel 2 – FPGA + TimingLevel 3 – ASIC + FPGA(we have Level 3 ASIC only)

ADKAMI 0.5, 1.2TSMC 0.35, 0.25

Automated Synthesis with

Synopsys Design Compiler

VHDL/Verilog Behavioral/RTL ModelsTechnology

Synthesis Libraries

Design Compiler (shell) Design Vision (GUI)

ASIC

DW

Technology-SpecificNetlist

DesignConstraints

Verilog, SDF, DDC database,SDC constraints, REP report

Synopsys DesignWareComponentLibrary

Leonardo – ASIC Synthesis Flow

Synthesizegeneric gates

Map to technologycells & optimize

Read &check HDL

generic gates& modules

cells & optimize

Write netlist,SDF, reports

Synthesis example

1. Load technology library: tsmc035 (ASIC), or Xilinx Spartan2 (FPGA)

2. Load design file: modulo7.vhd3. Specify constraints: clock freq, delays, etc.4. Optimization: effort, performance vs. area4. Optimization: effort, performance vs. area5. Write synthesized netlist output(s):

modulo7_0.vhd : VHDL netlist for ModelSim & DFTmodulo7.v : Verilog netlist for import into DA-ICmodulo7.sdf : For ModelSim to study timing modulo7.edf : EDIF netlist for 3rd party toolsmodulo7.xnf : Xilinx netlist for Xilinx ISE

Behavioral model to be synthesized-- modulo-7 counter with asynchronous reset and synchronous load/countlibrary ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;entity modulo7 isport( count,load,reset,clk: in std_logic;

I: in unsigned(2 downto 0); -- “unsigned” form of std_logic_vectorQ: out unsigned(2 downto 0)); -- defined in IEEE “numeric_std” package

end modulo7;architecture Behave of modulo7 is

signal Q_s: unsigned(2 downto 0);begin

process (reset,clk) beginif (reset='0') then Q_s <= "000";elsif (clk'event and (clk='1')) then

if (count = '1') and (Q_s = "110") then Q_s <= "000";elsif (count='1') then Q_s <= Q_s + 1;elsif (load='1') then Q_s <= I;end if;

end if;end process;Q<=Q_s;

end;

Synthesized netlist (1)-- Definition of modulo7-- Thu Sep 21 10:48:09 2006-- LeonardoSpectrum Level 3, 2005a.82--library IEEE;use IEEE.STD_LOGIC_1164.all;

entity modulo7 isentity modulo7 isport (count : IN std_logic ;load : IN std_logic ;reset : IN std_logic ;clk : IN std_logic ;I : IN std_logic_vector (2 DOWNTO 0) ;Q : OUT std_logic_vector (2 DOWNTO 0)) ;

end modulo7 ;

Synthesized netlist (2)

architecture Behave of modulo7 issignal Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, NOT_reset, nx4, nx14, nx22, nx48, nx60, nx169, nx179, nx189, nx202, nx204, nx208, nx212, nx214, nx218, nx225, nx228, nx230: std_logic ;

beginQ(2) <= Q_2_EXMPLR ;Q(1) <= Q_1_EXMPLR ;Q(1) <= Q_1_EXMPLR ;Q(0) <= Q_0_EXMPLR ;ix170 : mux21_ni port map ( Y=>nx169, A0=>nx14, A1=>Q_0_EXMPLR, S0=>nx225);ix15 : oai22 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>nx202, B0=>nx230,

B1=>count);ix203 : nand02 port map ( Y=>nx202, A0=>count, A1=>nx204);ix205 : nand04 port map ( Y=>nx204, A0=>count, A1=>Q_2_EXMPLR,

A2=>Q_1_EXMPLR, A3=>nx228);ix180 : oai32 port map ( Y=>nx179, A0=>nx208, A1=>count, A2=>load,

B0=>nx212, B1=>nx225);Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>nx208, D=>nx179,

CLK=>clk, R=>NOT_reset);

Synthesized netlist (3)

ix211 : inv01 port map ( Y=>NOT_reset, A=>reset);ix213 : aoi22 port map ( Y=>nx212, A0=>I(2), A1=>nx214, B0=>nx22, B1=>nx4 );ix216 : inv01 port map ( Y=>nx214, A=>count);ix219 : nand02 port map ( Y=>nx218, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR);Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx189,

CLK=>clk, R=>NOT_reset);ix190 : mux21_ni port map ( Y=>nx189, A0=>nx60, A1=>Q_1_EXMPLR, S0=>nx225);ix190 : mux21_ni port map ( Y=>nx189, A0=>nx60, A1=>Q_1_EXMPLR, S0=>nx225);ix61 : ao32 port map ( Y=>nx60, A0=>nx48, A1=>nx218, A2=>nx4, B0=>I(1),

B1=>nx214);ix49 : or02 port map ( Y=>nx48, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR);ix226 : nor02_2x port map ( Y=>nx225, A0=>count, A1=>load);Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>nx228, D=>nx169,

CLK=>clk, R=>NOT_reset);ix231 : inv01 port map ( Y=>nx230, A=>I(0));ix5 : inv01 port map ( Y=>nx4, A=>nx202);ix23 : xor2 port map ( Y=>nx22, A0=>nx208, A1=>nx218);

end Behave ;

Post-synthesis timing analysis� Leonardo can generate SDF (std. delay format) file with technology-specific, VITAL-compliant timing parameters.

(CELLTYPE "dffr")(INSTANCE Q_0_EXMPLR_EXMPLR)(DELAY(ABSOLUTE(ABSOLUTE(PORT D (::0.00) (::0.00))(PORT CLK (::0.00) (::0.00))(PORT R (::0.00) (::0.00))(IOPATH CLK Q (::0.40) (::0.47))(IOPATH R Q (::0.00) (::0.55))(IOPATH CLK QB (::0.45) (::0.36))(IOPATH R QB (::0.53) (::0.00))))

(TIMINGCHECK(SETUP D (posedge CLK) (0.47))(HOLD D (posedge CLK) (-0.06))))

Post-synthesis simulation (1)(Leonardo-generated netlist)

� Verify that synthesized netlist matches behavioral model� Verify timing information predicted by Leonardo

� Create library of simulation primitives for std cells:� Create library of simulation primitives for std cells:>vlib adk>vcom $ADK/technology/adk.vhd>vcom $ADK/technology/adk_comp.vhd

VITAL models of ADK std cells

Package of ADK component declarations

Post-synthesis simulation (2)

� Edit the synthesized VHDL netlist file (modulo7_0.vhd) to include the package of component declarations:

-- Definition of modulo7-- Thu Sep 21 10:48:09 2006-- Thu Sep 21 10:48:09 2006-- LeonardoSpectrum Level 3, 2005a.82--library IEEE;use IEEE.STD_LOGIC_1164.all;library adk; -- add these two linesuse adk.adk_components.all;

entity modulo7 isport (…..

Post-synthesis simulation (3)

� Compile the VHDL netlist:

vcom modulo7_0.vhd

� Simulate the model with timing:� Simulate the model with timing:

vsim modulo7 –sdftyp modulo7.sdf –do modulo7.do

(modul7.do is a “force file”)

� Verify that the synthesized circuit produces the same results as the behavioral circuit

ASIC Physical Design (Standard Cell)(can also do full custom layout)

FloorplanChip/Block

Component-Level Netlist (EDDM format)

Std. CellLayouts

Mentor Graphics“IC Station”

(adk_ic)Libraries

ICblocks

Place & RouteStd. Cells

IC Mask Data

Design RuleCheck

Mach TA/Eldo Simulation Model

BackannotateSchematic

GenerateMask Data

Layout vs.SchematicCheck

Design Rules

Process Data

Calibre Calibre Calibre

ICblocks

Cell-Based IC

I/O pads

Cell-Based Block

Basic standardCell layout

Source: Weste “CMOS VLSI Design”

Preparation for Layout

1. Use Design Architect-IC to convert Verilog netlist to Mentor Graphics EDDM netlist format

� Invoke Design Architect-IC (adk_daic)� On menu bar, select File > Import Verilog

� Netlist file: count4.v (the Verilog netlist)� Output directory: count4 (for the EDDM netlist)� Mapping file $ADK/technology/adk_map.vmp

2. Open the generated schematic for viewing2. Open the generated schematic for viewing� Click Schematic in DA-IC palette � Select schematic in directory named above (see next slide)� Click Update LVS in the schematic palette to create a netlist to be used later by

“Calibre”

3. Create design viewpoints for ICstation tools� adk_dve count4 –t tsmc035 (V.P’s: layout, lvs, sdl, tsmc035)

Can also create gate/transistor schematics directly in DA-IC using components from the ADK library

DA-IC generated schematic

Create a std-cell based logic block in

IC Station

� Invoke: adk_ic� In IC Station palette, select: Create Cell

� Cell name: count4� Attach library: $ADK/technology/ic/process/tsmc035� Process: $ADK/technology/ic/process/tsmc035� Process: $ADK/technology/ic/process/tsmc035� Rules file: $ADK/technology/ic/process/tsmc035.rules� Angle mode: 45� Cell type: block� Select With connectivity� EDDM schematic viewpoint: count4/layout� Logic loading options: flat

Create Cell dialog box

Auto-”floorplan” the block

place & route > autofp

Auto-place the std cells

Autoplc > StdCel

Auto-place ports (signal connections on cell boundaries)

Autoplc > Ports

AutoRoute all nets (hand-route unrouted “overflows”)

Then: Add > Port Text to copy port names from schematic – for Calibre

16 by 8 divider circuit

Layout design rule check (DRC)

� Technology-specific design rules specify minimum sizes, spacing, etc. of features to ensure reliable fabrication� Design rules file specified at startup

Ex. tsmc035.rules

� From main palette, select ICrules � Click Check and then OK in prompt box(can optionally select a specific area to check)

� Rules checked in numeric order

Layout vs. schematic check

Calibre Interactive LVS

� From ICstation menu: Calibre > Run LVS� In popup, Calibre location: $MGC_HOME/../Calibre

� Rules: $ADK/technology/ic/process/tsmc035.calibre.rules

� Input: count4.src.net (previously created in DA-IC)

� H-cells: $ADK/technology/adk.hcell (hierarchical cells)� H-cells: $ADK/technology/adk.hcell (hierarchical cells)

� Extracted file: count4.lay.net

� Compares extracted transistor-level netlist vs. netlist saved in DA-IC

Post-layout parameter extraction

Calibre Interactive PEX

� Extract Spice netlist, including parasitic RC� Simulate in Eldo or MachTA

� ICstation menu: Calibre>Run PEX� Options similar to Calibre LVS� Extraction options:

� lumped C + coupling cap’s� distributed RC� distributed RC + coupling cap’s

� Output file: count4.pex.netlist

Top level layout design flow**

1. Create a symbol for each core block (adk_daic)2. Create a chip-level schematic from core blocks and pads

(adk_daic)3. Generate design viewpoints (adk_dve)4. Create a layout cell for the chip(adk_ic)4. Create a layout cell for the chip(adk_ic)

� Place core logic blocks from the schematic� Generate a pad frame� Move/alter core blocks to simplify routing� Route pads to core blocks� Design rule check & fix problems

5. Generate mask data

** Refer to on-line tutorials by Yan/Xu and by Dixit/Poladia

Core logic blocks for top-level schematic

� Generate a symbol for each “core” logic block� In DA-IC, open the schematic (eg. modulo7)

� Select: Miscellaneous > Generate Symbol

� Add “phy_comp” property to the symbol� Select the body of the symbol

� From the popup menu: Properties > Add

� Enter property name: phy_comp

� Enter property value: mod7b

(layout cell name for the block created in IC Station)

� Check & save

Example on next slide

Symbol with phy_comp property

Layoutcell is“mod7b”for logicfor logicschematic“modulo7”

Chip-level schematic

� In DA-IC, create a schematic for the chip� Instantiate core blocks

� Menu pallete: Add > Instance

� Select and place generated symbol

� Add pads from ADK Library>Std. Cells>Pads >tsmc035 : In, Out, � Add pads from ADK Library>Std. Cells>Pads >tsmc035 : In, Out, BiDir, VDD, GND

� Wire pads to logic blocks and connectors

� Assign pin numbers, if known� Change pad instance name to PINdd (dd = 2-digit pin #)

� Check & save

� Create design viewpoints with adk_dve

Example on next slide

Assigning PAD pin numbers

Change instance name property on pads to PINxxxx = 2-digit pin number (01 – 40 for Tiny Chip package)

Place pad onchip pin 01

Default instancenames

Top-level schematic for “modulo7” chip

Hierarchicalconnectors

VDD/GNDPads

Core blockconnectorson “Pad” pins

Wire block I/O pinsto pad signal pins

Core block

Instancename =PINxx(chip pin #)

Chip layout

� Start IC Station (adk_ic) & create a new layout cell� enter cell name� logic source is “layout” viewpoint of chip schematic� same library, process file, rules file, and options as standard cell layout

� Open the schematic � Open the schematic � ADK Edit menu: Logic Source > Open� In the schematic, select all core cells (but not pads)� Place the cells: Place > Inst

� Generate the pad frame� Top menu bar: ADK > Generate Padframe > tsmc035

Chip layout (2)

� Move, rotate, flip core logic cells as desired to make routing easier� BUT - DO NOT EDIT OR MOVE PAD CELLS

� Autoroute all connections � Select autoroute all on P&R menuSelect autoroute all on P&R menu� Click “options” on prompt bar, and unselect “Expand Channels” (prevents pads from being moved)

� Add missing VDD/GND wires, if necessary� Autorouter might only route 1 VDD/GND wire, even if multiple VDD/GND pads

� Manually add others: Objects>Add>Path� VDD/GND net width = 50� VDD/GND net vias = 6x6 (copy an existing via)

Modulo-7 counter in pad frame