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Hindawi Publishing CorporationVLSI DesignVolume 2012, Article ID
102585, 3 pagesdoi:10.1155/2012/102585
Editorial
VLSI Circuits, Systems, and Architectures forAdvanced Image and
Video Compression Standards
Maurizio Martina,1 Muhammad Shafique,2 and Andrey Norkin3
1 VLSI Lab, Department of Electronics and Telecommunications,
Polytechnic University of Turin, Corso Duca degli Abruzzi
24,I-10129 Torino, Italy
2 Chair for Embedded Systems (CES), Department of Computer
Science, Karlsruhe Institute of Technology (KIT) Kaiserstrasse
12,76131 Karlsruhe, Germany
3 Ericsson Research, Torshamnsgatan 23, 164 83 Stockholm,
Sweden
Correspondence should be addressed to Maurizio Martina,
[email protected]
Received 26 August 2012; Accepted 26 August 2012
Copyright © 2012 Maurizio Martina et al. This is an open access
article distributed under the Creative Commons AttributionLicense,
which permits unrestricted use, distribution, and reproduction in
any medium, provided the original work is properlycited.
1. Introduction
In the last ten years image and video compression
researchdeveloped new techniques and tools to achieve high
com-pression ratios even when high quality is required.
Thesetechniques involve several parts of the
compression/decom-pression chain including transform stages,
entropy coding,motion estimation, intraprediction, and
filtering.
At the same time image and video compression standardswere ready
to identify the most relevant novelties andincorporate them. In
this scenario JPEG2000 and MPEG4-part 10, also known as
H.264/advanced video coding (AVC),are two important examples of
standards able to performsignificantly better than their ancestors
JPEG and MPEG2.Recently, stemming from the AVC standard, video
compres-sion started facing new challenges. The increasing
requestfor high quality, virtual reality, and immersive gaming
high-lighted how video compression standards have to face notonly
high definition and high rate sequences but also 3Dor multiview
systems. These challenges are part of the highefficiency video
coding (HEVC) and multiview video c oding(MVC) standards.
Unfortunately, both HEVC and MVCstandards yield to high complexity
burden.
In particular, even if some works on the implementationof the
MVC standard have already been proposed in theliterature, several
critical aspects, including performance,memory management, power
consumption, and reconfig-urability are still open issues. On the
other hand, HEVC is theultimate standard for video compression
issued by the Joint
Collaborative Team on Video Coding. As a consequence,works
available in the literature mainly address new toolsand performance
of the HEVC standard. Thus, results oncomplexity and implementation
issues are still on going. Inthis scenario, advances in camera and
display technologiesand continuously increasing users’ sensation
for true three-dimensional (3D) reality have led to the evolution
of new 3Dvideo services with multiview videos, like true-3DTV,
freeviewpoint TV (FTV), realistic-TV, in-car
3D-infotainment,3D-personal video recording and playback,
3D-surveillance,immersive video conferencing, high-end medical
imaging,remote eHealth applications like 3D-teleoperation
theaters,telework office, teleshopping, and so forth. The
feasibilityof multiview video recording of 2–4 views on
mobiledevices has been demonstrated by the early case studieson
3D-camcorders/3D-mobile phones by Panasonic, SharpLynx, Fujifilm,
Sony, Minox, etc. However, multiview videoprocessing of 4–8 views
for mobile devices and of 16−>100views for advanced 3D
applications (3DTV/FTV, 3D-medicalimaging, 3D surveillance, etc.)
is foreseen to be adopted in2015–2020 at a wide range.
On the other hand, HEVC [4] is a next generation videostandard,
which is regarded as a next major step in videocoding
standardization after AVC. The standardization hasbeen conducted
jointly by VCEG and MPEG in a JointCollaborative Team on Video
Coding (JCT-VC). The stand-ardization has reached a committee draft
stage in February2012. When starting the standardization, the goal
was toachieve twice better compression efficiency compared to
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2 VLSI Design
AVC standard. That means that the same subjective picturequality
should be achieved at twice lower bitrate comparedto High Profile
of AVC. The standard is primarily focusedon coding
higher-resolution video, such as HD and beyond.Higher-resolution
videos often have different signal statisticsfrom the
lower-resolution content. Moreover, coding higher-resolution video
also generates higher requirements to thecompression ratio as well
as to computational complexity ofboth encoding and decoding. Higher
resolutions and higherframe rates set restriction on standard’s
computational com-plexity, which was taken into account when
working onthe standard. Another aspect of video compression that
wasaddressed in developing HEVC is a requirement of
easyparallelization, which facilitates higher resolution coding
byperforming encoding and decoding of video in parallel onmultiple
processors.
In order to meet up the present and future demands ofdifferent
multimedia applications, one interesting researchdirection concerns
the development of unified videodecoders that can support all
popular video standards on asingle platform. It is worth noting
that several video com-pression standards use the DCT-based image
compression.Since the DCT computation and quantization process
arecomputation intensive, several algorithms are proposedin
literature for computing them efficiently in dedicatedhardware.
Research in this domain can be classified intothree parts: (i)
reduction of the number of arithmetic oper-ators required for DCT
computation, (ii) computation ofDCT using multiple constant
multiplication schemes, (iii)optimization of the DCT computation in
the context ofimage and video encoding.
Another important aspect related to the complexity
ofvideo-coding standards is the large amount of coding toolsused to
achieve high compression rates while preserving thevideo visual
quality. As an example, the prediction steps ofH.264/AVC (composed
by intraframe prediction and inter-frames prediction) are
responsible for the main contributionof compression provided by
this standard, which results inabout 50% fewer bits to represent a
video when comparedto MPEG-2. This result is achieved through the
insertionof a large number of coding modes in the prediction
stepsand selecting the best one to encode each macroblock
(MB).However, the computation of a large number of predictionmodes
provided by H.264/AVC standard is extremely expen-sive in terms of
computational complexity. In particular forHD formats several
millions of complete encoding opera-tions are needed for each video
frame. In order to supportreal time video encoding and decoding,
specific architecturesare developed. As an example, multicore
architectures havethe potential to meet the performance levels
required bythe realtime coding of HD video resolutions. However,
toexploit multicore architectures, several problems have to
befaced, such as the subdivision of an encoder application
inmodules that can be executed in parallel. Once a good
parti-tioning is achieved, the optimization of a video
encodershould take advantage of the data level parallelism to
increasethe performance of each encoder module running on
theprocessing element of the architecture. A common approachis to
use single instruction multiple data instructions to
exploit the data level parallelism during the execution.
How-ever, several points have not been addressed yet, for
example,how the data level parallelism is exploited by SIMD
andwhich instructions are more useful in video processing.Moreover,
different instruction set architectures (ISAs) areavailable in
modern processors and comparing them is animportant step toward
efficient implementation of videoencoders on SIMD
architectures.
In 2007, the notion of electronic system level design(ESLD) has
been introduced as a solution to decrease thetime to market using
high-level synthesis. In this context,CAL was introduced as a
general-use data flow target agno-stic language based on the data
flow process networkmodel of computation. The MPEG community
standardizedthe RVC-CAL language in the reconfigurable video
coding(RVC) standard. This standard provides a framework to
des-cribe the different functions of a codec as a network of
func-tional blocks developed in RVC-CAL and called actors.
Somehardware compilers of RVC-CAL were developed, but
theirlimitation is the fact that they cannot compile
high-levelstructures of the language so these structures have to be
man-ually transformed. Thus, this research field requires
furtherinvestigation. This special issue is dedicated to research
pro-blems and innovative solutions introduced above in allaspects
of design and architecture addressing realizationissues of
cutting-edge standards for image and video compre-ssion. The
authors have focused on different aspects includ-ing (i) VLSI
architectures for computationally intensiveblocks, such as the DCT
and the intraframe coding mode, (ii)automatic code generation and
multicore implementationof complex MPEG4 and H.264 video encoders.
Due to theincreasing importance of stereo and 3D video processing
aninvited paper dealing with this topic is included in the
issue.
2. VLSI Architectures for ComputationallyIntensive Blocks
As long as new standards have been developed, severalresearch
efforts were spent to design efficient VLSI archi-tectures for
computationally intensive blocks. Stemmingfrom the works of Chen
and Loeffler, several techniqueswere proposed to reduce the
complexity and to increasethe flexibility of architectures for the
computation of theDCT. Formal techniques as subexpression
elimination andcanonical sign digit (CSD) representation are viable
tech-niques to optimize architectures for the computation ofthe
DCT. The paper “optimized architecture using a novelsubexpression
elimination on loeffler algorithm for DCTbased image compression”
by M. Jridi et al. presents a novelcommon sub-expression
elimination technique that is usedwith the canonical sign digit
(CSD) representation to reducethe complexity of the Loeffler
algorithm for DCT implemen-tation. An FPGA-based implementation is
provided withvideo quality results in terms of peak signal to noise
ratio(PSNR). Other approaches are based on the factorizing theDCT
by the means of simpler and modular structures. Somethese ideas
were already described in Rao Kamisetty works,but their impact on
VLSI implementation has not been com-pletely studied especially
when flexibility and multistandard
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VLSI Design 3
requirement have to be taken into account. In the paper “Npoint
DCT VLSI architecture for emerging HEVC standard”by A. Ahmed et al.
a variable-sized DCT architecture ispresented. The architecture
stems from the Walsh-Hadamardtransform and uses the lifting scheme
to reduce the numberof multiplications required. The authors
provide hardwareimplementation results for a 90 nm ASIC technology.
Thepaper “low cost design of a hybrid architecture of
integerinverse DCT for H.264, VC-1, AVS, and HEVC” by M.Martuza and
K. A. Wahid proposes a unified architecture forcomputation of the
integer inverse DCT of multiple modernvideo codecs. Moreover, the
authors show both FPGA- andASIC-based implementation results.
It is known that the DCT is only one of the most
com-putationally intensive blocks in video compression
systems.Several other blocks, including motion estimation
andentropy coding, are known to be a significant part of
thecomputational burden of video compression systems. Withthe
H.264/AVC standard very high quality is obtained evenwith very low
bit rates. Such an impressive improvementis obtained due to the
possibility to employ a large num-ber of new tools, as
intraprediction, coupled with severalcoding modes. As a
consequence, the optimal choice ofa coding mode is a very
computationally intensive task.Thus, techniques for the fast
identification of the optimal ornearly-optimal coding mode are of
paramount importance.The paper “low complexity hierarchical mode
decision algo-rithms targeting VLSI architecture design for the
H.264/AVCvideo encoder” by G. Corrêa et al. presents a set of
heuri-stic algorithms targeting hardware architectures that lead
toearlier selection of one encoding mode. The resulting solu-tion
leads to a significant complexity reduction in the encod-ing
process at the cost of a relatively small compression per-formance
penalty.
3. Automatic Code Generation andMulticore Implementation
The development of VLSI architectures, circuits, and systemsfor
video compression is a time-consuming task. As a con-sequence,
industries are always working hard to be ready withproduct that are
on the cutting-edge of the available tech-nology. Automatic code
generation is a very appealing stra-tegy to speed up the design
process and to reduce recurrentcosts. In the paper “automatic
generation of optimizedand synthesizable hardware implementation
from high-leveldataflow programs” by K. Jerbi et al., the authors
describea methodology that from a high-level language called
CalActor Language (CAL), which is target agnostic, automati-cally
generates image/video hardware implementations ableto largely
satisfy the real time constraints for an embeddeddesign on
FPGA.
Other directions have been investigated to reduce thetime
required to develop hardware components. The avail-ability of high
performance multicore processors (e.g. GPUs)is pushing several
researchers to use software solutions evenfor very complex systems
as video encoders. This directionis investigated in the paper “an
efficient multi-core SIMDimplementation for H.264/AVC encoder”, by
M. Bariani et al.
where the optimization process of a H.264/AVC encoder onthree
different architectures with emphasis on the use ofSIMD extensions
is described. Experimental results are givenfor all the three
architectures.
4. Depth Maps Extraction
The availability of devices for 3D displaying together
withstandards for 3D and multiview video processing has
high-lighted how 3D video is a very challenging topic. One of
themain issues is related to the fact that the signals acquiredfrom
cameras are 2D, and signal processing is required tomerge data
together to create a 3D video sequence or to createa new view of
the scene. In particular, it is widely recog-nized that extracting
depth maps from 2D images is oneof the key elements to create 3D
video. In this perspective,the invited paper “hardware design
considerations for edge-accelerated stereo correspondence
algorithms” by C. Ttofisand T. Theocharides deals with this hot
topic: extractingdepth maps from 2D images. In particular, in this
work theauthors present an overview of the use of edge
informationas a means to accelerate hardware implementations of
stereocorrespondence algorithms. Their approach restricts thestereo
correspondence algorithm only to the edges of theinput images
rather than to all image points, thus resultingin a considerable
reduction of the search space. The resultingalgorithms are suited
to achieve real-time processing speedin embedded computer vision
systems. For both algorithms,optimized FPGA architectures are
presented.
Maurizio MartinaMuhammad Shafique
Andrey Norkin
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