vlsi

.- COLOR STICK ENCODING LAYERS MASK LAYOUT ENCODING CIFLAYER

I t~~u•on J n+ active) ~1@) ND GREEN I Thinox*

*Thinox = n-diff. +transistor channels

RED I I Polysilicon ~ NP

I 1111111111111111111111 SLUE Metal1 NM

J1 I BLACK • Contact cut • NC

I - I GRAY NOT APPLICABLE Overglass NG

nMOS

D l ONLY Implant Nl

YELLOW

nMOS Buried

~ ONLY • NB BROWN

contact

FEATURE FEATURE (STICK) FEATURE (SYMBOL) FEATURE (MASK)

J: s t: m ~-n-type ) enhancement .

mode transistor D

G S D

Transistor length to width ratio L: W should be shown. G

I L: W l l:W • L: W . w. n-type depletion • ··- -+- [§ g] )

mode transistor

~ ~ I I nMOS only s .. G D

Source, drain and gate labelling will not normally be shown. ~ i

COLOR PLATE 1(a) Encodings for a simple single metal nMOS process. (See Figure 3.1(a) for nMOS monochrome encoding details.)

COLOR

GREEN - -

AEO - -BLUE - -BLACK

- -GRAY

YELLOW (STICK)

YELLOW

DARK BLUE OR PURPLE

BLACK

STICK ENCODING

--- Encod ing as in

Color plate 1 (a)

-,... - - - --

--~ green outline here for clarity

Not shown on diagram

I I

• Demarcation line

----

BROWN ....., ..... - iiiiiii ....

p-well edge is shown as a demarcation line in stick diagrams

BLACK X

LAYERS

r-n-diffuslon ...., (h• active) ~ Thltiox* ....I

Poly Ill leon ---Metal1 - -

Contact cut - -

Over glass

p-diffusion (p+active)

p+mask

Metal 2

VIA

p-well

VDD or

Vss contact

-

-

MASK LAYOUT ENOODING CIF LAYER

• Thinox = n-dft. + p-dft. + transistor ehannels -

CAA or

CNA f- - - - - - - - -

Encoding as in - - -CPF

- -Color plate 1 (a) CMF f- - - - - - - - -cc ~ - - - - - - - -

COG -p+mask

CAA or

CPA

either or

CPP

I I CMS

rn CVA

I . I CPW

n• t '[l!IJhlli' cc

FEATURE FEATURE (STICK) FEATURE (SYMBOL) FEATURE (MASK)

n-type enhancement mode transistor

(as in Color plate 1 (a))

Demarcation line

+ L: W

Transistor length to width ratio L:W may be shown.

p-type enhancement mode transistor ·

Demarcation line

+ G

D ~ ~ ......_

----

Note : p-type transistors are placed above and n-type below the demarcation line G p+mask

COLOR PLATE 1 (b) Color encodings for a double metal CMOS p-well process. The same well encoding and demarcation line is used for an n-well process. For a p-well process, the n features are in the well. For an n-well process, the p features are in the well. (See Figure 3.1{b) for CMOS monochrome encoding details.)

COLOR

ORANGE

PINK

PALE GREEN

STICK ENCODING

-,---1

< Not separately encoded

Not separately encoded

LAYERS

Polysilicon 2

Bipolar npn transistor

p-base of bipolar npn transistor

Buried collector of bipolar npn transistor

· MASK LAYOUT ENCODING CIF LAYER

~"""<'~,~~~~ . '-..\'· ~··-... . .............. ~'"""""''~~.y~-~"'"" CPS

See Color plate 6 Not also Figure 3. 13(f) applicable

CBA

CCA

FEATURE FEATURE (STICK) FEATURE (SYMBOL) FEATURE (MASK)

n-type enhancement · poly. 2 transistor.

Demarcation line

Transistor length to width ratio L: W may be shown .

p-type enhancement poly. 2 transistor

Demarcation line

IQ:tai s Fo

G

Note: p-type transistors are placed above and n-type below the demarcation line

npn bipolar transistor < See Figure 3. 13(f)

and Color plate 6

COLOR PLATE 1 (c) Additional encodings for a double metal double poly. BiCMOS n-well process. The same well encoding and demarcation line as in Figure 3.1 (b) is used for an n-well process. For a p-well process, the n features are in the well. (See Color plate 6 for additional BiCMOS color encoding details and see Figure 3.1(c) for monochrome encoding details).

1 :1

GND

4 :1 nMOS inverter

Simple n-well based BiCMOS inverter (stick diagram)

Simple symbolic notation

Transistors

n-channel MOS

p-channel MOS

npn BiCMOS

rn-tr;,__ GREEN ~----outl ine

.0 1 0 ___ vE~Low

..._.-- outl1ne

WIRES etc., as ior stick diagrams

1:1

p-well CMOS inverter

substrate connection

Alternative design for an n-well based BiCMOS inverter

Simple n-well based BiCMOS inverter (symbolic diagram)

COLOR PLATE 1 (d) Color stick diagram examples. (See Figure 3.1 (d) monochrome stick diagrams and simple symbolic encoding.)

CMOS inverter liP & 0/P on polysilicon

Stick diagram

Vss

Color fill Color outline

0 2 5 10 15

Lambda I I I I I.., Lambda

0/P

Color hatching Monochrome

COLOR PLATE 2 Example layout encodings.

Design rules for wires (interconnects) (ORBIT 2 I-'m CMOS)

Minimum width Thin ox Min. separation as shown Minimum

width n-diff. (n•active) ~iff-(e:,activel..... Metal1

31-ln:~s~/h] diff.todiff.

_ n-diff. and p-diff. cannot cross or join S = 2.5 11..;;-~to metal 1

31!~~ S 12/Z'?~ffiJ- Poly. todiff. E2.5~>m

-_ 1 11m separalton diff./poly.1 1.5 11m sepn diff./poly. 2 ~ 2.51!m

Metal2 -211m~ , -;m 2.5 11m Po1 2 1..-. * - Poly. to poly. _ ___;__ r--- Poly. 2 3~>m ... ._..__;___~-

2 11m m~~""'~"""~ ;1 - Metal 2 to metal 2 - ~~::::..,::.;.;,.:::,. ,:::J 2J!.m 3 I'm

Z~,.,""'..,;,. -,.dge z~~~~~~~~~~~~ :::=!E: 1 .5 11m min. overlap -- 3 !-'m 211m 211m -- 1 .5 11m min.overlap ::::IE: tZ · ~ Capacitors poly. 1 /poly. 2 ~ · · · · · ·

Poly. 2 overlapping poly. 1 Poly. 1 overlapping poly. 2

Otherwise poly. 2 must not be coincident with poly. 1

Note: Where no separation is specified, wires may overlap or cross (e.g. metal may cross any layer). For p-well CMOS, n-diff. wires can only exist inside and p-diff. wires outside p-well. For n-well CMOS, p-diff. wires can only exist inside and n-diff. wires outside n-well. ·

Avoid coincident edges where metal 1 and metal 2 runs follow the same path for> 25!-lm length (underlap metal1 edges by 0.8J1m).

Transistor related design rules (ORBIT 2 11m CMOS)

2 Minimum sizes and overlaps

---~:2 ·5 1..._ Minimum overlap of n-diffusion (n• active) beyond gate. 3 I-'m

min. width

Poly. 1 transistors

Minimum overlap of 2.51.._ p-diffusion (p• active) I-'m beyond gate.

All devices shown are n-type. The same rules apply for p-type.

2.5 11m min. sepn contact cut to gate and overlap of diff.

COLOR PLATE 3 ORBIT™ 2 J.lm design rules (a) (b).

Rules for contacts and vias (ORBIT 2 f!m CMOS)

1. Meta11 to poly. 1 or poly. 2

Metal 1q'poly. 1

A~ernative color representation+ I I I 2i!m 4flm

Sllffi ~

3 . Multiple contact cuts

S = 2 !.tiT1 min. separation

Alternative color separations

2. Metal 1 to n+ or p+ active (diff.)

4 . Via metal 1 1 metal2

I ~!J.~ I

t.51J.M 2!J.m

TI~J.M

2 !J.m min. space from via to Poly. 1 or 2 or active edge

1.IS1J.M 1.51J.M

5 . Vias from metal 2 to metal1 and thence to other layers 1 .5 !.tiT1 / Via outside active to active edge

3 11M min. width ' 2.5 l 3 11M min. width

d ld I!J.m ld ld · -- --- -1.5 ~- J. -

f 2!J.m ===== ~~~~~~1.111.11 1.5 !J.m ~~ ---- -l -

Via to via min.

Note that vias must not be placed over contacts.

COLOR PLATE 4 ORBIT™ 2 ~m design rules (c).

2 11M min. space from vta Inside poly. 1 or 2 or active to edge

Rules for r.-well and V00 and V55 contacts (ORBIT 2 1-'ffi CMOS process)

n-well

V00 and V55 contacts

Sf.lm 5 2.5f.!m f..l.ffi min.

3 !Am min. width

-Jiilool I.,._

Metal1 (hatohlng omitted for clarity)

V00 contact ton-well. Note that edges of well and contact may coincide.

n-well

n-well spacings and width

Rules for pad and overglass geometry (ORBIT 2 !Am CMOS)

min.

Top+ type features

100 urn----.] · -J 100 x 100 urn metal 1

1 901-'m

overglass opening

-~

90x90 !Am aperture in overglass

I 90f.'m II 75f.!mmin. ~~~ ~overglass~ . ... •I 20ym j 1 ~ 5 !Am min. metal

open1ng mm. lr overlap of overglass lr-----~--~------scr~i~--ri~ng--------~------------,1

Other rules and encodings:

Via overlap of pad 2 !Am Pad to active separation 20 !Am minimum Color encoding for overglass mask ... gray.

COLOR PLATE 5 ORBIT™ 2 IJ.m design rules (d) (e).

Special rules for BiCMOS transistors (ORBIT 2 1-1m CMOS)

Note : For clarity, layers have not been drawn transparent. Note that BCCD underlies the entire area and the p-base underlies all within its boundary.

COLLECTOR EMITTER BASE OXIDE

Buried n+ subcollector (BCCD) p+ connection to base

Cross-section through npn transistor (ORBIT 2 1-1m BiCMOS)

COLOR PLATE 6 ORBIT™ 2 Jlm design rules (f) .

Data liP

Data 0 /P

Note that the transistors a and b also c and d have been merged in the mask layout.

--~--~--_.----~---1--__ ._ __ _. vss

0 1 0 1

(a) Symbol ic diagram

... From liP or from preceding bit cell

Data liP

r 0'7

0 2 0 2 . "\.- I

Bounding box

-- - ~p-well ,,.... ... ,.._ ________ 1-bit cell

(b) Derived mask layout

COLOR PLATE 7 1-bit CMOS shift register cell.

Symbolic diagram

8 A

I I I I I I I I I I I I C I

I It I I I ·e

BiCMOS

. v .• I,.-~.~-·~.~--~ ·I·-~ I;.{·.; I~-·~.~·-~ ·I··~.~.~-.;.-:-.;., .. ; ... I. t I I I I I I I I I I I I I I I I I I I I I I I I I

I t I I I I I I I I I I I I I I I I I I I I I I I I I I I J I I I I I I I I I I I I I I I I I I I I · I I I I

Mask layout

COLOR PLATE 8(a) A BiCMOS 2 input nand gate.

Symbolic diagram

B I I I t I I I I I

B

A 8

A I I

A

I I I I I t I t I t I I I I I I I I I I I I I I I I I I I I I V,

- ~ - r - r · t-~ - ~ - ; - - r - r - ~ · i · i·i · t · W·i · i·i · i - i · l · i · i · ~ · i · i · { · ~ oo

Mask layout

COLOR PLATE 8(b) A BiCMOS 2 input nor gate.

-•-

Implant

(a) (ii) Mask layout

c (4:1)

(Source of inputs assumed as shown in stick diagram)

A I I

Input source through pass transistors

·~-,, ! l!

(b) (i) Sti ck diagram

A

(Optio dema line

_;. /w nal ) · rcation

B

- ~.

"

(a) (i) Stick diagram

1:2

I-

0/P

i :l

GND

c Input from an Inverter output

-1"1"'

0/P -- ~

-

Vss

COLOR PLATE 9(a) Three input nMOS nor gate; (b) two input CMOS (p-well) nor gate.

(a) Standard cell layouts

Standard cells TA.x11f..

(ii)

(b) Mask layout

Stick diagram

z

,,

-_,

COLOR PLATE 10 n-type pass transistor based 4-way MUX.

k

lo

:::

t

s, 'li..l

"

""' "' ~ I• Whir . ..t. r:rm ...,.

ra.l

"' s,

'"' "

"'"" ""' .......

......

·" "

Mask layout

Note that the n and p switch networks are identical-each comprising 6 minimum size contactltransistor structures plus 1 long double transistor switch.

Stick diagram

- 0/P IMX n

'-... Demarcation line

COLOR PLATE 11 CMOS transmission gate based 4-way MUX.

·(v£·s aJn6!.::1 aas) Jo~eJaua6 )j:>O(:> (s~uawa(dwo:> pue) ase4d-oM~ JOJ ~noAe( )!sew z ~ 31Vld ~010:>

::.c:: (.)

(.) og (.)

c co () ()~ :5 w 0

II

() 0 (.)

IO t-::;) a.. z ::.c::

18 10 0 ()g (.)

II

lo 1<.> (.)