VLSI-unit 1

8/6/2019 VLSI-unit 1

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CMOS Technology depends on using both N-Type and P-Type devices on thesame chip.

The two main technologies to do this task are: P-Well (Will discuss the process steps involved with this technology)

The substrate is N-Type. The N-Channel device is built into a P-Type well within the parentN-Type substrate. The P-channel device is built directly on the substrate.

N-Well The substrate is P-Type. The N-channel device is built directly on the substrate, while the P-

channel device is built into a N-type well within the parent P-Type substrate.

Two more advanced technologies to do this task are:Becoming more popular for sub-micron geometries where device performance and density must bepushed beyond the limits of the conventional p & n-well CMOS processes.

Twin Tub Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate.

Silicon-on-Insulator (SOI) CMOS Process SOI allows the creation of independent, completely isolated nMOS and pMOS transistors

virtually side-by-side on an insulating substrate.

C omplementary MOS fabrication


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P-well on N-substrate

Steps : N-type substrate Oxidation, and mask (MASK 1) to create P-well (4-5 m deep) P-well doping

P-well acts as substrate for nMOS devices.The two areas are electrically isolated using thick field oxide (and oftenisolation implants [not shown here])

P-well

SiO 2

N-type substrate


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Polysilicon Gate FormationSteps : Remove p-well definition oxide

Grow thick field oxide Pattern (MASK 2) to expose nMOS and pMOS active regions Grow thin layer of SiO 2 (~0.1 m) gate oxide, over the entire chip surface Deposit polysilicon on top of gate oxide to form gate structure

Pattern poly on gate oxide (MASK 3)

Thick fieldoxide

Gate (patternedpolysilicon on thin oxide)

Thin gate oxide(SiO 2)

P

N-type substrate

nMOS active region

pMOS active region


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nMOS P+ Source/Drain difusion self-aligned to Poly gate

Implant P + nMOS S/D regions (MASK 4)

Thick fieldoxide

P

N-type substrate

P+ implant/diffusion

P+ mask


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pMOS N+ Source/Drain difusion self-aligned to Poly gate

Implant N + pMOS S/D regions (MASK 5 often the inverse of MASK 4)

P

N-type substrate

N+ implant/diffusion

N+ mask

P+ N+


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pMOS N+ Source/Drain difusion, contact holes & metallisation

Oxide and pattern for contact holes (MASK 6)

Deposit metal and pattern (MASK 7)Passivation oxide and pattern bonding pads (MASK 8)

P-well acts as substrate for nMOS devices.Two separate substrates : requires two separate substrate connectionsDefinition of substrate connection areas can be included in MASK 4/MASK5

P

N-type substrate

P+ N+

N+ for N-substratecontact)

P+ (for P-substratecontact)

Vdd V ss

Vin

Vout

P channelDevice N channel

Device


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CMOS N-well process

An N-well process is also widely used

N-well

P-type substrate

N+

P+

P+

for P-substratecontact) N+ (for N-substrate contact)

Vdd V ss

Vin

Vout

P channelDevice

N channelDevice


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MOS Transistor

S (Source) D (Drain)G (Gate)

Substrate

Channellength Location of

conductinglayer

DD

n-ChannelTransistor OFF - no D-to-S Cur ent

0Volts V Volts0 Volts


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MOS Transistor

S (Source) D (Drain)G (Gate)

Substrate

Channellength Location of

conductinglayer

n-Channel Transistor: ON - D -to-S Current

0Volts VDD VoltsVDD Volts


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Switch Models for MOS Transistors

n-Channel Normally Open (NO) Switch Contact

p-Channel Normally Closed (NC) Switch Contact

XG

D

S

Symbol

X :

Switch M odel:

X:X

SimplifedSwitch Model

XG

D

S

Symbol

X:

Switch Model

X:X

SimplifiedSwitch Model


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Circuits of Switch Models

Series

Parallel

X: X

Y: Y

Series

X A N D Y

X: X Y:Y

Parallel

X OR Y


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Fully-Complementary CMOS Circuit

Circuit structure for fully-complementary CMOS gate

+Vlogic 1

logic 0

F

F usingp-typetransistors(NC switches)

F usingn-typetransistors(NO switches)

X1

X2

Xn

General Structure


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CMOS Circuit Design Example

Find a CMOS gate with the following function: Beginning with F0, and using F

The switch model circuit in terms of NOswitches:

F = X Z + Y Z = (X + Y)Z

F0 Circuit: F = X Y + Z

X: XZ: Z

Y: Y


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The switch model circuit for F1 in terms of NCcontacts is the dual of the switch model circuit for F0:

The function for this circuit is:

which is the correct F.

X: X Y: Y

Z: Z

F = (X + Y) ZF1 Circuit:


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Replacing theswitch models with CMOStransistors;note inputZ must be

used.


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CMOS Inverter

A Y 01

VDD

A Y

GNDA Y


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CMOS Inverter

A Y 01 0

VDD

A=1 Y=0

GND

ON

OFF

A Y


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CMOS NAND Gate

A B Y 0 0 1

0 11 01 1

A=0

B=0

Y=1OFF

ON ON

OFF


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CMOS NAND Gate

A B Y 0 0 1

0 1 11 01 1

A=0

B=1

Y=1OFF

OFF ON

ON


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CMOS NAND Gate

A B Y 0 0 1

0 1 11 0 11 1

A=1

B=0

Y=1ON

ON OFF

OFF


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CMOS NAND Gate

A B Y 0 0 1

0 1 11 0 11 1 0

A=1

B=1

Y=0ON

OFF OFF

ON


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CMOS NOR Gate

A B Y 0 0 1

0 1 01 0 01 1 0

A

BY


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3-input NAND Gate

Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

A

B

Y

C


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Inverter Cross-section

Typically use p-type substrate for nMOStransistor Requires n-well for body of pMOS transistors Several alternatives: SOI, twin-tub, etc.

n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO 2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor


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Well and Substrate Taps

Substrate must be tied to GND and n-well to V DD

Metal to lightly-doped semiconductor formspoor connection called Shottky Diode

Use heavily doped well and substrate contacts /taps

n+

p substrate

p+n well

A

YGND VDD

n+p+

substrate tap well tap

n+ p+


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Inverter Mask Set

Transistors and wires are defined by masks Cross-section taken along dashed line

GND V DD

Y

A

substrate tap well tapnMOS transistor pMOS transistor


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Detailed Mask Views

Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well


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Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well

Cover wafer with protective layer of SiO2(oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed

wafer Strip off SiO2

p substrate


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Oxidation

Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO 2


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Photoresist

Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

p substrate

SiO 2Photoresist


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Lithography

Expose photoresist through n-well mask Strip off exposed photoresist

p substrate

SiO 2Photoresist


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Etch

Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has beenexposed

p substrate

SiO 2Photoresist


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Strip Photoresist

Strip off remaining photoresist Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next step

p substrate

SiO 2


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n-well

n-well is formed with diffusion or ionimplantation

Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si

Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Sin well

SiO 2


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Strip Oxide

Strip off the remaining oxide using HF Back to bare wafer with n-well

Subsequent steps involve similar series of steps

p substraten well


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Polysilicon

Deposit very thin layer of gate oxide < 20 (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of siliconlayer Place wafer in furnace with Silane gas (SiH4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor Thin gate oxidePolysilicon

p substraten well


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Polysilicon Patterning

Use same lithography process to patternpolysilicon

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well


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Self-Aligned Process

Use oxide and masking to expose where n+dopants should be diffused or implanted

N-diffusion forms nMOS source, drain, and n- well contact

p substraten well


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N-diffusion

Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion

Polysilicon is better than metal for self-alignedgates because it doesnt melt during laterprocessing

p substraten well

n+ Diffusion


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N-diffusion

Historically dopants were diffused Usually ion implantation today

But regions are still called diffusion

n wellp substrate

n+n+ n+


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N-diffusion

Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+


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P-Diffusion

Similar set of steps form p+ diffusion regionsfor pMOS source and drain and substratecontact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+


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Contacts

Now we need to wire together the devices Cover chip with thick field oxide

Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact


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Metallization

Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal


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Processing Steps:

Substrate Selection


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Anisotropic etch:


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From P- island for N-Device:


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From N-island for P-device:


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Growth & oxide through thermal oxidation:


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Deposit Doped Silicon:


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Etch polysilicon:


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N-Implantation for Source & Drain:


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P-Implantation:


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Grow phosphorus glass Etch glass to form contact cut Evaporating Alumini

B l d f f d


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Balanced performance of n and pdevices can be constructed


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SILICON ON INSULATOR

What is SOI? Characteristics of SOI Fabrication methods Basic categorization Electrical anomalies

Advantages and Disadvantages

7/12/2011 UNIVERSITY OF CALIFORNIA, IRVINE


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What is SOI?-SOI Silicon-on-Insulator

-Si layer on top of aninsulator layer tobuild active devicesand circuits.

- The insulator layer isusually made of SiO2



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Characteristics

Include:- High speed- Low power- High device density - Easier device isolation structure


SOI F b i ti


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SOI FabricationProcesses-SOS Silicon-on-Sapphire-SIMOX Separation by Implantation of Oxygen-ZMR Zone melting andrecrystallization

-BESOI Bond and Etch-back SOI-Smart-cut SOI Technology



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Categorization

-Categorization based on thethickness of the silicon film.- The first is a partially-depleteddevice and the latter is a fully-depleted device.

-Each has its own advantagesand disadvantages.

-PD device threshold voltage isinsensitive to film thickness.

-FD device has reduced shortchannel and narrow channeleffects.


El i l li


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Electrical anomalies

Floating-body effect:-Usually seen in Partially-Depleted devices.

- As shown in figure, theMOS structure isaccompanied by aparasitic bipolar device inparallel.

- The base of this device isfloating.




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Kink Effect:-Sudden discontinuity in draincurrent.

-Seen when the device is biasedin the saturation region.

- The bipolar device is turned on.

Solution:-Provide a body contact for thedevice.

- Use FD devices.



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Self-heating effect:- Thermal insulation is provided by the oxide surface.- Heat dissipation is not efficient.- This happens only when there is logic switching in the device.

In fully-depleted devices, the threshold voltage is sensitive to ththickness of the silicon film.

Manufacturing process is comparatively difficult.



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Advantages of SOI

Suitable for high-energy radiation environments

Parasitic capacitances of SOI devices are muchsmaller.

No latch-up.



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Advantages

-Easier deviceisolation

-High devicedensity

-Easier scale-downof threshold voltage.


Uses in digital and analog


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Uses in digital and analogcircuits

A combination of FD and PD devices are usedin digital circuitry.

Superior capabilities of SOI CMOS technology usage in memory cell implementation.


Uses in digital and analog


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Uses in digital and analogcircuits

SOI technology is useful for implementing highspeed op-amps given its low Vt.

Higher transconductance (especially of FD)implies higher gain.

Lower power consumption compared to bulk devices at low current level.



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Disadvantages

Major bottleneck is high manufacturing costs ofthe wafer.

Floating-body effects impede extensive usage oSOI.

Device integration dopant reaction with theoxide surface.

Electrical differences between and SOI nad bulkdevices.



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Conclusion

Due to its characteristics, SOI is fast becoming standard in IC fabrication.

Several companies have taken up SOImanufacturing.

High-volume production of SOI is yet tobecome common.



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Interconnect

(i).Metal Interconnect Polysilicon & diffusion (N+,P+)


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Lay out Diagram:


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(ii).Poly Interconnect:


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(iii).Local Interconnect:


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Circuit Elements:


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Latchup


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Latchup problem:

Latchup : Shorting of VDD and Vss lines Chip breakdown Latchup Equivalent Circuit:

Vertical : pnp p = source/drain of p device (Emitter) n = n-well (Base) p = p-substrate (Collector)

Lateral : npn n = source/drain of n device (Emitter) p= p-substrate (Base) n= n-well (Collector)

Rsubstrate, Rwell Parasitic devices and resistors


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Latch up Problem:


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Equivalent Circuits:


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Characteristics curve:


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THANK U

VLSI-unit 1

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