VLSI Power Delivery For Core, I/O, and Analog Supplies Claude R. Gauthier, Ph.D., Brian W. Amick Sun Microsystems Inc., Major Electrical Interfaces ■ Core Power Delivery ■ Physical and electrical view ■ Parasitic inductance estimation ■ Distribution issues, guidelines ■ I/O Power Delivery and Signaling ■ Signal return current ■ Analog Power Delivery ■ Summary
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VLSI Power Delivery For Core, I/O, andAnalog Supplies
Claude R. Gauthier, Ph.D.,
Brian W. Amick
Sun Microsystems Inc.,
Major Electrical Interfaces Core Power Delivery
Physical and electrical view
Parasitic inductance estimation
Distribution issues, guidelines
I/O Power Delivery and Signaling Signal return current
Analog Power Delivery
Summary
Microprocessor Design Constraints Power supply impedance
Z=(∆VSPEC)/(∆IESTIMATE): Ex. 1.8-V x 5% / 10-A = 9-mΩ
Must deliver power over a broad frequency spectrum
Time (cpu clock cycles)
Po
wer
Max
Avg
Min
Architectural Power Model To Estimate ∆IClockGating
Decoupling Capacitor Modeling Wide range in performance and cost
Example: 3 different capacitors
Parasitics between banks must be included
SymbolWave
D0:A0:vm(1)
D0:A0:vm(4)
D0:A0:vm(7)
Volts
Mag
(log
)
1m
10m
100m
1
10
Frequency (log) (HERTZ)100k1x 10x 100x
1g
|X(f)|=1/(2πCF)|X(f)|=2πF*ESL
X(f)=ESR
1st OrderCapacitorModel
ESL
ESR
Cap
Impe
danc
e
Frequency
1mΩ
10mΩ
100mΩ
1Ω
10Ω
1MHz 10MHz 100MHz 1GHz.1MHz
Low Frequency Electrical View
Bumps,GridPCBPCBVoltage
Regulator PlanesVias and
Planes Package
BulkCaps
CeramicCaps
Package Vias,Planes, Caps
On-Chip
SwitchingLogic
Non-SwitchingLogic
Imp
ed
an
ce
Frequency
FREGULATOR FBULK FCERAMIC FPACKAGE
1/(jωCB )
1/(jωCC )
1/(jωCP )
1/(jωCDIE )
Z
Z
Qualitative Look At Frequency Domain
Cap
Inductance of Vias, Pins, Bumps Mutual inductance [1],[2]
Self inductance [1],[2]
Loop inductance of arrays is pattern dependent [3]
Muo2π------l l
s-- 1 l
2
s2
-----+
+
1 s2
l2
-----+
– sl--+ln
=
Luo2π------l 2
ld--- 1 4l
2
d2
--------+
+
1 0.25d2
l2
-----------------+
– 0.5dl---
ur4
------+ +ln
=
POOR BETTER
d
l
s
Inductance Simplification Can collapse to single inductor
Use a script/spreadsheet to construct a matrix
Lump same-type inductors in parallel and place powerand ground inductors in series
Simulate w/ spice in AC domain to determine equivalentseries inductance (V=I*jωL)
LP1
LPN
LG1
LGN
Mij1-AAC
LEFF
1-AAC
Power Plane Inductance Planes are present in the package and on the board
Loop inductance [2]:
Most planes are actually perforated
Decrease inductance for multiple pairs by 2n-1dielectrics, where n is the number of power planepairs, assuming VDD-GND-VDD-GND stack-up
Thin spacing decreases inductance
Luoπ
------ld
B C+-------------- 1.5+ln
=
d
B
Cµo
l
Low/Mid-Frequency Chip Model Estimate switching capacitance from thermal power
CSWITCH=P/(V2f)
On-die decoupling capacitance is typically about 10xthe switching capacitance (rule of thumb)
Yield issue (decoupling is ~15-20% of die area)
Scaling issue for process shrinks - leakage
Equivalent series resistance (ESR) Ratio of one type to the other is design-specific
High ESRCapacitor(Channels)
Low ESRCapacitor(Sub-blocks)
SwitchingCapacitance
Non-switchingCapacitance
Selecting and Sizing Capacitors Construct system model and determine R and L
from physical geometry
Run AC analysis with circuit simulator by sweepingload switching frequency
Different types of caps target different frequencies Board Capacitor: 1-MHz to 10-MHz
Package Capacitor: 10-MHz to 200-MHz
On-Chip Capacitor: High-Frequency
Find number & types of caps with spice simulationWhile (! full AND ! meeting_spec) Beginincrement num_caprun_ac_analysisextract_impedanceIf (impedance < target) BeginExitEndIfIf (full AND ! meeting_spec) Beginreplace_capEndIfEndWhile