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VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design Saraju P. Mohanty, N. Ranganathan and Ravi K. Namballa Dept. of CSE, University of South Florida, Tampa, FL 33620 smohanty,ranganat,rnamball @csee.usf.edu Abstract Watermarking is the process that embeds data called a watermark into a multimedia object for its copyright protection. The digital watermarks can be visible to a viewer on careful inspection or completely invisible and cannot be easily recovered without an appropriate decoding mechanism. Digital image watermarking is a computation- ally intensive task and can be speeded up sigificantly by implementing in hardware. In this work, we describe a new VLSI architecture for implementing two different visible wa- termarking schemes for images. The proposed hardware can insert on-the-fly either one or both watermarks into an image depending on the application requirement. The proposed circuit can be integrated into any existing digital still camera framework. First, separate architectures are derived for the two watermarking schemes and then integrated into a unified architecture. A prototype CMOS VLSI chip was designed and verified implementing the proposed architecture and re- ported in this paper. To our knowledge,this is the first VLSI architecture for implementing visible watermarking schemes. 1 Introduction Watermarking is the process that embeds data called a wa- termark, tag or label into a multimedia object such that wa- termark can be detected or extracted later to make an asser- tion about the object. The object may be an image, audio, video, or text. In general, any watermarking scheme consists of three parts, such as, the watermark, the encoder and the decoder. The marking algorithm incorporates the watermark into the object, whereas the verification algorithm authenti- cates the object determining both the owner and the integrity of the object. The watermarks can be applied either in spatial domain or in frequency domain. According to human per- ception, the digital watermarks can be divided into four cate- gories : visible watermark, invisible-robust, invisible-fragile and dual [1, 2]. A visible watermark is a secondary translu- cent overlaid into the primary image and appears visible to a viewer on careful inspection. Controller Interface and Watermarking Controller Input Memory (Flash, SDRAM) DSP Processor Image Sensors A/D Converter Output Watermarking Processor Watermarking Datapath Figure 1: System Architecture of a Secure Digital Still Camera Several software based watermarking schemes have been presented in the literature; however, only a few hardware schemes have been proposed. Strycker, et. al. [4] proposed the implementation of a real-time spatial domain watermark embedder and detector on a Trimedia TM-1000 VLIW pro- cessor. Mathai, et. al. [5] present a chip implementation of the same video watermarking algorithm. A DCT domain in- visible watermarking chip is presented by Tsai and Lu [6]. Garimella, et. al. [7] proposed a VLSI architecture for invisible-fragile watermarking in spatial domain. Mohanty, et. al. [8] described a watermarking chip that has spatial domain invisible robust and fragile watermarking function- alities. In this work, we focus on the VLSI implementation of two spatial domain visible watermarking schemes, one pro- posed by Braudaway, et. al. [9] and the other by Mohanty, et. al. [3]. The VLSI chip can insert either one or both the watermarks depending on the requirement of the user. The proposed watermarking chip can be integrated within any ex- isting digital still camera. We provide the schematic view of a still camera that includes a watermarking module in Fig. 1, and call such a camera as a ”secure digital still camera”. 2 Watermarking Algorithms In this section, we outline the watermarking algorithms in brief with the modifications needed for hardware imple- mentation. The notations listed in Table 1 are needed for describing the algorithms.
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VLSI Implementation of Visible W atermarking for a Secure ...cessor. Mathai, et. al. [5] present a chip implementation of the same video watermarking algorithm. A DCT domain in-visible

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  • VLSI Implementation of Visible Watermarking for a Secure DigitalStill Camera Design

    SarajuP. Mohanty, N. RanganathanandRavi K. NamballaDept.of CSE,Universityof SouthFlorida,Tampa,FL 33620�

    smohanty,ranganat,rnamball� @csee.usf.eduAbstract

    Watermarking is the processthat embedsdata calleda watermark into a multimedia object for its copyrightprotection. The digital watermarkscan be visible to aviewer on careful inspectionor completelyinvisible andcannotbeeasilyrecoveredwithoutan appropriatedecodingmechanism.Digital image watermarkingis a computation-ally intensivetask and can be speededup sigificantly byimplementingin hardware. In this work, wedescribea newVLSIarchitecture for implementingtwo differentvisiblewa-termarkingschemesfor images.Theproposedhardwarecaninserton-the-flyeitheroneor bothwatermarksinto animagedependingon the application requirement. The proposedcircuit canbeintegratedinto anyexistingdigital still cameraframework. First, separatearchitecturesare derivedfor thetwowatermarkingschemesandthenintegratedinto a unifiedarchitecture. A prototypeCMOSVLSI chip was designedandverifiedimplementingtheproposedarchitecture andre-portedin this paper. To our knowledge, this is thefirst VLSIarchitecturefor implementingvisiblewatermarkingschemes.

    1 Introduction

    Watermarkingis theprocessthatembedsdatacalledawa-termark,tagor label into a multimediaobjectsuchthatwa-termarkcanbedetectedor extractedlater to make anasser-tion aboutthe object. The objectmay be an image,audio,video,or text. In general,any watermarkingschemeconsistsof threeparts,suchas, the watermark,the encoderandthedecoder. Themarkingalgorithmincorporatesthewatermarkinto the object,whereasthe verificationalgorithmauthenti-catestheobjectdeterminingboththeownerandtheintegrityof theobject.Thewatermarkscanbeappliedeitherin spatialdomainor in frequency domain. According to humanper-ception,thedigital watermarkscanbedividedinto four cate-gories: visible watermark,invisible-robust,invisible-fragileanddual [1, 2]. A visible watermarkis a secondarytranslu-centoverlaidinto theprimaryimageandappearsvisible to avieweroncarefulinspection.

    Controller

    Interface

    and

    Watermarking

    Controller

    Input

    Memory

    (Flash, SDRAM)

    DSP

    Processor

    Image

    Sensors

    A/D

    Converter

    Output

    Watermarking Processor

    Watermarking

    Datapath

    Figure1: System Architecture of a Secure Digital StillCamera

    Severalsoftwarebasedwatermarkingschemeshave beenpresentedin the literature; however, only a few hardwareschemeshave beenproposed.Strycker, et. al. [4] proposedtheimplementationof a real-timespatialdomainwatermarkembedderanddetectoron a TrimediaTM-1000VLIW pro-cessor. Mathai,et. al. [5] presenta chip implementationofthesamevideowatermarkingalgorithm.A DCT domainin-visible watermarkingchip is presentedby Tsai andLu [6].Garimella, et. al. [7] proposeda VLSI architectureforinvisible-fragilewatermarkingin spatialdomain. Mohanty,et. al. [8] describeda watermarkingchip that hasspatialdomaininvisible robust andfragile watermarkingfunction-alities.

    In this work, we focus on the VLSI implementationoftwo spatialdomainvisible watermarkingschemes,onepro-posedby Braudaway, et. al. [9] andthe otherby Mohanty,et. al. [3]. TheVLSI chip caninserteitheroneor both thewatermarksdependingon the requirementof the user. Theproposedwatermarkingchipcanbeintegratedwithin any ex-isting digital still camera.We provide theschematicview ofastill camerathatincludesawatermarkingmodulein Fig. 1,andcall sucha cameraasa ”securedigital still camera”.

    2 Watermarking Algorithms

    In this section,we outline the watermarkingalgorithmsin brief with the modificationsneededfor hardwareimple-mentation. The notationslisted in Table 1 are neededfordescribingthealgorithms.

  • Table1: List of Variables used in Explanation�: Original (or host)grayscaleimage�: Watermarkimage(agrayscaleimage)�������: A pixel location��: Watermarkedimage���������: Original imagedimension� ��� : Watermarkimagedimension���: ����� block of theoriginal image�� � : ����� block of thewatermarkimage �� ��: ����� block of thewatermarkedimage��� � : Scalingfactorfor ����� block� �: Embeddingfactorfor ����� block � : Meangrayvalueof theoriginal image � � � : Meangrayvalueof imageblock ���! � � : Varianceof theoriginal imageblock ����#"%$�& : Themaximumvalueof � �� "(' � : Theminimumvalueof � �� "%$�& : Themaximumvalueof � �� "(' � : Theminimumvalueof � ��*) � ' �,+ : Grayvaluecorrespondingto white pixel� � : A globalscalingfactor-/. � -10: Linearregressionco-efficients-(2 � -(3: Linearregressionco-efficients

    Algorithm 1 (Proposedin [9]) : The watermarked imageis obtainedby addinga scaledgrayvalueof theimageto thehostimage.Theamountof scalingis donein suchawaythatthealternationof eachoriginal imagepixel occursperceptu-ally by equaldegree. The original formula is simplifed asfollows,wherethescalingfactor 4%5 determinesthestrengthof thewatermark[10].

    687:9=@?BADCEFFFFFG FFFFFH6�9I;J=K?BABLNMO9I;J=K?BA1P 5RQTSVUXW,YZK[]\ ^K^V_T`ba 58cedbf gih5jQkSVUeWlY%monp 4%5

    for58cedbf gih5jQkSVUeWlYrqtsvu sws�x�xkyiz6�9I;J=K?BABLNMO9I;J=K?BA a 58cedbf gih{K|VZ]\ Z m 4}5

    for58cedbf gih5jQkSVUeWlYr~tsvu sws�x�xkyiz

    (1)

    Theaboveequationis furthersimplifiedto makethehard-wareimplementationeasier. At thesametime, careis takento makesurethatthehardwareis asaccurateasthesoftwareimplementations.We assume

    6�XIC y�y andsimplify theaboveequationsto thefollowing.

    687:9I;J=K?BADC EFFG FFH6�9I;J=K?BABLPw^]\ |V{V_V^ ` MO9=@?BA�9�6�9I;J=K?BA@A np

    for69=@?BA q u yixw6�9I;J=K?BABLP�{K|VZ]\ Z ` MO9=@?BA@6�9I;J=K?BA

    for69=@?BA ~ u yixw (2)

    We further simplify the above expressionsand remove thecubic root function with a piecewise linear model. Wedivide the gray values range s =T6 eI* to four ranges,

    suchas s = 5jQTSKUeWlY , 5jQTSVUXW,Y = 5jQkSVUeWlY , 5jQTSKUeWlY = Z 5jQTSVUXW,Y , and Z 5jQkSVUXW,Y =T6 8eI . We fit four linear regressionco-efficientsthatbestapproximatesthecubicroot in eachof theseranges.Moreover, we roundupthefractioninvolvedin thecompari-sonoperationandthe final simplified expressionthat is im-plementedusinghardwareis asfollows.

    6 7 9I;J=K?BADC

    EFFFFFFFFFFFFFFG FFFFFFFFFFFFFFH

    6�9I;J=K?BABLPJ�{K|VZ]\ Z ` MO9=@?BA169=@?BAfor

    69=@?BA ~ 6�9I;J=K?BABL P K^]\ |V{V_K^T` MO9I;J=K?BA16�9I;J=K?BAfor

    t6�9I;J=K?BA ~z�6�9I;J=K?BABL P w n^]\ |V{V_K^T` MO9I;J=K?BA16�9I;J=K?BAfor z� 69=@?BA ~  x6�9I;J=K?BABLP(w p^]\ |V{V_K^ ` MO9I;J=K?BA16�9I;J=K?BAfor   x 69=@?BA ~¡ 8¢ 6�9I;J=K?BABL P( K�£^]\ |V{V_K^T` MO9I;J=K?BA16�9I;J=K?BAfor  ¢ ¤69=@?BAo y�z

    (3)

    Algorithm 2 (Proposedin [3]) : Thepixel grayvaluesaremodifiedbasedon the local andglobal statistics. The wa-termakinginsertionprocessconsistsof the following steps.Both thehostimage(oneto bewatermarked)

    6andthewa-

    termark(image)M

    aredividedinto blocksof equalsizes(thetwo imagesmay be of unequalsize). Let ¥§¦ denotethe ¨ Iblock of the original image

    6and ©�¦ denotethe ¨ I block

    of thewatermarkM

    . For eachblock ( ¥§¦ ), thelocalstatistics;meanªB¦ 5 andvariance«�¦ 5 arecomputed.Theimagemeangray value ª 5 is also found out. The watermarked imageblock is obtainedby modifying ¥ ¦ asfollows.

    ¥ 7 ¦ C 4(¦¥§¦ L¬ ¦©�¦ ¨ C   =* ulueu (4)Where,4 ¦ and ¬ ¦ arescalingandembeddingfactorsrespec-tively, dependingon ª ¦ 5 and « ¦ 5 of eachhostimageblock.

    The choiceof 4 ¦ and ¬ ¦ are governedby certainchar-acteristicsof humanvisualsystem(HVS) andmathematicalmodelsareproposedsothattheperceptualqualityof theim-agearenotdegradeddueto watermarkaddition.The 4(¦ and¬ ¦ areobtainedasfollows. The 4%¦ and ¬ ¦ for edgeblocksaretakento be 4 d®�¯ and ¬ d g respectively. The 4(¦ and ¬ ¦arefoundoutusingthefollowing equations.

    4 ¦ C °±²´³ kµ¶�· PK¸ 9/¹ª ¦ 5 ¸ ¹ª5 A `¬ ¦ C ¹«¦ 5 P   ¸ µ¶w· P@¸ 9º¹ªB¦ 5 ¸ ¹ª 5 A `` (5)Where,

    ¹ª ¦ 5 and ¹ª5 are normalisedvaluesof ª ¦ 5 and ª5 ,and

    ¹« ¦ 5 arenormalisedlogarithmvaluesof « ¦ 5 . The 4 ¦ and¬ ¦ arescaledto the ranges( 4}d g , 4%d®�¯ ) and( ¬ d g , ¬ d®�¯ )respectively, where 4}d g and 4%d®�¯ areminimumandmax-imum valuesof scalingfactor, and

    ¬ d g and ¬ d®�¯ aremin-imum andmaximumvaluesof embeddingfactor. Thesepa-rametersdeterminetheextentof watermarkinsertion.A lin-eartransformationis usedto scalecurrent 4 ¦ and ¬ ¦ valuesto theranges( 4 d g , 4 d®�¯ ) and( ¬ d g , ¬ d®�¯ ), respectively.

  • Let currentvaluesof 4 ¦ be written as 4%»¦ , and 4%»d g and4(»do�¯ , respectively denotethe currentminimum andmaxi-mum values. Similarly, let currentvaluesof

    ¬ ¦ be writtenas¬ »¦ , and ¬ »d g and ¬ »d®�¯ , respectively denotethe current

    minimum andmaximumvalues. The 4 ¦ and ¬ ¦ valuesarescaledasfollows.4 ¦ C a �¼}½@¾´¿�¼ UXÀwÁ¼}½@¾ ¿ Á¼ UXÀ m 4%»¦ L a 4%d®�¯ ¸ a �¼B½K¾Â¿�¼ UXÀwÁ¼B½K¾ ¿ Á¼ UXÀ m 4%»d®�¯ m¬ ¦ C avà ¼B½K¾ ¿ à ¼ UeÀà Á¼B½K¾ ¿ à Á¼ UeÀ m ¬ »¦ L a ¬ d®�¯ ¸ aÄà ¼}½@¾ ¿ à ¼ UXÀà Á¼}½@¾ ¿ à Á¼ UXÀ m ¬ »d®�¯ m (6)

    We usedfirst-orderderivatives for edgedetection. Forhorizontaledgedetection,we computethehorizontalgradi-ent as: Å v9I;J=K?BAÆCÇ69=@?BA ¸ 6�9I;ÈL   =@?BA . The verticalgradientis computedas ÅÊÉ 9=@?BADCË6�9I;J=K?BA ¸ 69=@?¤L   Afor verticaledgedetection.Theamplitudeof anedgeis cal-culatedas, Å 9I;J=K?BA/CÌ Å �9=@?BA8Ì8LÌ ÅÊÉ 9=@?BA]Ì . Themeanamplitudefor a block is computedas,ÅÊÍ C °Î%Ï1ÐÄÎ%ÏÒÑ d Ñ g Å 9=@?BA (7)Whenthe meanamplitudefor a block exceedsa predefinedthreshold,we declareit asan edgeblock. The valuesof

    ;and

    ?correspondto thepixel locationsof individual blocks

    with referenceto theoriginal imagepixel location.Themeangrayvalueof a block is calculatedastheaver-

    ageof the grayvaluesof all pixels in the imageblock. Themeangrayvaluesarenormalizedwith purewhite pixel grayvalue.Thus,thenormalizedmeangrayvaluesof ablock is,¹ª ¦ 5 C °Î Ï ÐÓÎ Ï a °5jQkSVUeWlYwm Ñ d Ñ g 6�9I;J=K?BA (8)Where,

    ;and

    ?are the pixel locationsof the ¨ I image

    block,sameastheir locationsin theoriginal image.Thenor-malizedstandarddeviation of grayvaluesfor the ¨ I blockis calculatedasfollows.¹« ¦ 5 C °Î Ï ÐÓÎ Ï a 5jQTSVUXW,Ywm Ñ d Ñ gÔÔ 6�9I;J=K?BA ¸ 5RQTSVUXW,Y ÔÔ (9)Theexponentialtermin Eqn. 5 is approximatedasa Taylorseriesuptothesquareterm.

    In stepthreeof theinsertionalgorithm,scalingneedsto bedoneusinga linear transformation,to find thecurrentmini-mum andmaximumvaluesfor both 4%¦ and ¬ ¦ over all theblocks. The hardwareperformanceis going to be severelydegradedsinceit hasto wait till all thepixelsof the imagesareprocessedto derive the local statisticsof all the blocks.So, we modify the above Eqn. 5 to ensurethat the perfor-manceof thehardwareis improvedwith no compromiseonthequality. Wefind 4 ¦ and ¬ ¦ usingthefollowingequations.4(¦ C 4 d g LJ9 4 d®�¯ ¸ 4 d g A °±²³ µ¶w· P@¸ 9/¹ªB¦ 5 ¸ ¹ª 5 A `¬ ¦ C¬ d g L9I¬ d®�¯ ¸ ¬ d g A¹« ¦ 5 P   ¸ µ¶�· P ¸ 9Õ¹ª ¦ 5 ¸ ¹ª5 A `` (10)Extensive simulationsfor variousimagesshow that the 4 ¦and

    ¬ ¦ obtainedusingEqn. 6 andEqn. 10 arecomparable(maximumdifferenceis ykÖ [1]).

    Comparator

    Register

    FileMultiplier Multiplier

    Multiplier

    Adder

    WI (m,n)

    αI

    I(m,n) W(m,n)

    (a) For Algorithm 1

    αk β k

    Edge Detection

    Unit

    0 1 0 1

    minβmaxα

    Multiplier Multiplier

    Adder

    WI (m,n)

    αk

    β kand CalculationUnit

    I(m,n) W(m,n)

    (b) For Algorithm 2

    Figure2: Datapath Architectures for the Algorithms

    3 VLSI Architecture

    We developan architecturefor the first algorithmshownin Fig. 2(a). A register file is usedto storethe constantsneededto scaletheimage-watermarkproductin Eqn. 3. Westorethe constants

    °{K|VZ]\ Z , ^�\ |*{V_K^ , n^]\ |V{V_V^ , p^�\ |*{K_V^ , and £^�\ |*{V_K^and the other constant4%5 is assumedasa parameter. Thecomparatoris usedto determinetherangein which a partic-ular pixel gray valuelies, suchthat an appropriateconstantcanbe picked up from the registerfile. The left sidemul-tiplier calculatesappropriateconstanttimes the host imagepixel grayvaluesandtheright sidemultiplier is usedto find4 5 timesthewatermarkimagepixel grayvalue. Theresultsof the above two multipliers are fed to the third multiplierwhicheffectively calculatestheproductof constants,4%5 , thehostimagepixel grayvalue,andthewatermarkimagepixelgrayvalue,respectively. Theproductis addedto thehostim-agepixel grayvaluesusingtheadderto obtainwatermarkedimagepixel grayvalues.Theabovedescribedprocessis car-ried out for all thepixelsto obtainthewatermarkedimage.

    Thearchitecturebeingproposedfor thesecondalgorithmis shown in Fig. 2(b) which presentthe operationat pixellevel. The ” 4%¦ and ¬ ¦ calculationunit” computesthe 4(¦and

    ¬ ¦ valuesfor the ¨ I non-edgeblock usingexpressionin Eqn. 10. The”edgedetectionunit” determinesif a blockis an edgeblock or non-edgeblock. If the Å Í exceedsanuserdefinedthreshold,thenit is an edge-block.Larger thethresholdmorearetheblocksdeclaredasedge-blocks.Themultiplexorshelpin selectingthescalingandembeddingfac-tors betweenthe edgeandnon-edgeblocks. The multiplieron theleft calculatesthescalingfactorstimesthehostimagepixel grayvalue.Theright sidemultiplier multipliestheem-beddingfactorwith the watermarkimagepixel gray value.Theproductsfrom thesetwo multipliersareaddedusinganadderto find thewatermarked imagepixel grayvalue. Thisprocessis repeatedfor all pixelsin ablock,andsubsequentlyfor all theblocksin theimage.

  • Adder / Subtractor

    Adder / Subtractor

    Adder

    Accumulator

    Multiplier

    kIµ

    <

    ( − 0.5 )

    kIµ

    <

    Multiplier

    16384

    1

    Adder / Subtractor

    Adder

    Accumulator

    1

    8192

    kIσ

    <

    Multiplier

    Multiplier

    αmax

    αmin( − )

    Multiplierβ min

    Adder

    αmin

    Adder

    β max β min( − )

    β k αk

    I(m,n)

    0.5

    1

    Divider

    128

    Exponential Unit

    (a) × � and Ø � Calculation

    Adder / SubtractorAdder / Subtractor

    Adder

    Adder

    Accumulator

    Multiplier

    1

    64

    Comparator

    ThresholdAmplitude

    µG

    I(m+1,n) I(m,n) I(m,n+1)

    G(m,n)

    Edge or Non−edge Block

    (b) EdgeDetection

    Figure3: Individual Datapath Units for Algorithm 2

    4 ¦ and ¬ ¦ calculationunit: The architecturaldetails ofthe” 4 ¦ and ¬ ¦ calculationunit” areshown in Fig. 3(a).Thehardware implementsthe calculationfor 4 ¦ and ¬ ¦ repre-sentedas Eqn. 10 for one block at a time. The left sideadder-accumulatorcombinationfinds the sumof all the im-agepixel gray valuesfor a block. After the sum is multi-

    plied with a °Î Ï ÐÓÎ ÏJÙ °5 QkSVUeWlYwm , we get thenormalisedmeangrayvalueof ¨ I block denotedby ¹ªB¦ 5 . Sincewe have as-sumedblock size of xÚNx , and 6 8eI as y�z , this evalu-atesto

    °° ^KZV[ . It may be notedthat 6 8eI is ywy , but using y�z makeshardwareimplementationeasier, the latterbeingrepresentableasa power of two. In the original algorithm9/¹ª ¦ 5 ¸ ¹ª5 A is thedeviation of a meangrayvalueof a blockfrom theimagemeangrayvalue.Weareevaluatingthedevi-ationof meanblock grayvaluefrom mid-intensityof 5RQTSVUXW,Yfor simplicity, . Thus,

    9/¹ª ¦ 5 ¸ ¹ª5 A is computedas 9º¹ª ¦ 5 ¸ sÄuÛy A ,whennormalisedwith

    6]8eI. This assumptionaccelerates

    the hardwareperformanceto a greatextentsincethe block-by-blockwatermarkingcanbeperformedwithoutwaitingforthe global imagestatisticscomputedover the whole imagebeforethe watermarkinsertioncanbe performed. The ex-pressionµ¶�· P ¸ 9Õ¹ªB¦ 5 ¸ ¹ª 5 A ` is computedusingthe”expo-nentialunit”.

    Theadder/subtractorunit findstheimagepixel grayvalueabsolutedeviation from 5jQTSVUXW,Y . The adder-accumulatorfol-lowing this accumulatethe Ñ d Ñ g ÔÔ 69=@?BA ¸ 5jQkSVUeWlY ÔÔ fora block. When this sum is multiplied with a °Î Ï ÐÓÎ Ï m Ùa 5jQkSVUeWlYwm , which is xÄ ¢ for our case,we getthenormalisedstandarddeviation

    ¹«�¦ 5 . Theright sidedivider dividesexpo-

    nentialvaluecomputedbeforeby¹« ¦ 5 . Thequotientis then

    multiplied with 4%do�¯ ¸ 4%d g . Theabove productis addedto 4}d g to evaluate4 ¦ expressedin Eqn. 10. Theexponen-tial unit resultis fed to a adder/subtractoron left sidewhichfindsits differencefrom 1. Theresultis thenmultipliedwith¹« ¦ 5 obtainedfrom thecomputationsperformedbefore.Theproductobtainedis thenmultipliedwith

    ¬ d®�¯ ¸ ¬ d g . Thisproduct is then addedto

    ¬ d g which in turn gives the re-quired

    ¬ ¦ asperEqn.10.Edgedetectionunit: Thearchitecturefor determiningif a

    blockis anedgeor non-edgeblockis shown in Fig. 3(b). Theabsolutevaluesof thehorizontalgradient

    Ì Å 9=@?BA8Ì andtheabsolutevalueof verticalgradient

    Ì Å É 9I;J=K?BA]Ì arecalculated.The amplitudeof an edge Å 9I;J=K?BA is calculatedusing thefirst adder. Then, the adder-accumulatorcombinationfindsthesumof Å 9=@?BA for all pixelsof a block. Theabovesumwhenmultiplied with a °Î Ï ÐÄÎ Ï m 9jC zi A , we get the meanamplitudeÅÊÍ for a block. Thecomparatorcomparesthe ÅÊÍvalueswith anuserdefinedthresholdanddeclarestheblockasanedgeor non-edgeblock.

    The individual datapathsfor both the algorithms arestitchedtogetherusing multiplexors and a combineddata-path shown in Fig. 4(a) is obtained. Both the datapathssharethe samemultipliers, as it is evident from Fig. 4(a),the multiplexors help in selectinginput for the multipliers(WhenSelectis ”0” algorithm1 is used).Thecontrollerthatdrivesthedatapathis shown in Fig. 4(b). Thecontrollerhassix states,suchasInit, ReadBlock,WriteBlock, ReadPixel,WritePixel, andDisplayImage.WhentheStartsignalis ”1”thewatermarkingprocessis initiated. Dependingon theSe-lect signaloneof the watermarkingschemesis chosenandthe correspondingdatapathneedsto be driven to carry outthewatermarkingprocess.

    4 Prototype Chip Implementation

    The implementationof the watermarkingdatapathandcontrollerwascarriedout in the physicaldomainusingtheCadenceVirtuosolayouttool usingbottom-to-tophierarchi-caldesignapproach.Thedesigninvolvedtheconstructionoffour mainunits,suchastheexponentialunit, theedgedetec-tion unit, the 4(¦ and ¬ ¦ calculationunit, registerfile, andtheaccumulator. All of theaboveunitshavemultipliers,adders,adder/subtractor, divider, comparator, andsoon. Thesesmallfunctionalunitsarelaid outindividually throughmodulariza-tion andlaterinterfacedwith eachotherto getthefour abovementionedunits. The datapathand the controller are con-structedusingthe main units andthe functionalunits. Thelayoutsof thegatesat thelowestlevel of hierarchyaredrawnusingtheCMOSstandardcell designapproach.Wedesignedour own standardcell library containingbasicgates,suchasAND, OR, NOT. The completelayout of the watermarking

  • αk β k

    Edge Detection

    Unit

    0 1 0 1

    minβmaxα

    αk

    β kand CalculationUnit

    0 1

    Register File

    Comparator

    0 1

    αI

    Multiplier Multiplier

    Multiplier

    0 10 1

    I(m,n) W(m,n)Select

    Adder

    WI (m,n)

    (a) Datapath for Algo-rithms1 and2

    Read

    Pixel

    Read

    Block

    Write

    Block

    Display

    Image

    Write

    Pixel

    Init

    BlockCompleted=1

    BlockCompleted=0

    BlockCompleted=1

    ImageCompleted=1

    BlockCompleted=1

    ImageCompleted=1

    ImageCompleted=1

    ImageCompleted=0

    ImageCompleted=0

    BlockCompleted=0

    Start=0

    Select=1

    Start=1Start=1

    Select=0

    ImageCompleted=0

    (b) Controllerfor MergedDatapath

    Figure4: Architecture for the Proposed Processor

    chip is givenin Fig. 5(a)andthefloor planof thechip is pro-videdin Fig. 5(b). Table2 showstheoveralldesigndetailsofthechip andthecorrespondingpin diagramis shown in Fig.6. Thechip statisticsareobtainedusingHSPICEfor sÄu wy ªMOSISSCN3MSCMOStechnology.

    Thedatapathconstructioninvolvestheimplementationoftheproposedarchitecturein theprevioussection.Thefunc-tionalunitsare8-bit ripplecarryadders,8-bit multipliersand8-bit adder/subtractor. Theadder/subtractorunit is obtainedfrom theadderusingXOR gates[11]. An 8-bit parallelarraymultiplier is obtainedfrom full-addersandAND gatesto im-plementmultiplication operationswith reduceddelay [12].Thedivider is implementedusingtheshift andsubtractlogicfor thedivision [11]. Thecomparatorwasdesignedto com-parevaluesof two 8-bit numbersfor greater-than,equalto,or less-thanrelations.First, a single-bitcomparatorwasde-signedto comparethevaluesof two single-bitnumbers,andlater, instancesof thismodulewerecascadedto comparetwo8-bit numbers,startingfrom themost-significantbit positionandproceedingtowardstheleast-significantbit position.

    Theaccumulatoris implementedasa14-bit registerto ac-

    (a)Chip Layout

    αk

    andβk

    CalculationUnit

    Edge−Detection

    Unit

    Other ComponentsController

    (b) FloorPlan

    Figure5: Proposed Watermarking Chip

    Table2: Overall Statistics of the Watermarking Chip

    Area Ü�Ý Ü]Þ �ß Ý à8á �� 0Numberof gates

    ß à]Þ´â8áClock frequency

    ß á ß Ý ßã8äNåçæNumberof I/O pins

    ãßPower â�Ý á ß àâ � �

    commodatea maximumvalueof zièÚ yiz . The maximumvalueoccurswheneachpixel in a xÒÚJx block assumesthevalueof purewhite pixel grayvalue. The registerfile is anaddressablearrayof 8-bit registers(words) [12]. Basedonthe addressspecifiedand a Read/Writeselectline, at anytime, a valuecanbe eitherwritten to or readfrom the reg-ister file. Here,we useda 5-word registerfile to storethefive differentconstants,suchas

    °{K|VZ]\ Z , ^]\ |V{V_K^ , n^�\ |*{V_K^ , p^�\ |*{K_V^ ,and £^]\ |V{V_V^ , in Eqn. 3. Multiplexorsareusedat appropriateplacesin thedesignto selectoneof theincominglines.Eachof suchmultiplexor is implementedusinga combinationoftransmissiongates. Threeasynchronouslyresettableregis-tersaredesignedto encodethe five statesof the controllerdepictedin Fig. 4(b). The threeregisterscouldbe resetbytheuserto returnthecontrollerto its intial stateat any timeandfrom there,the watermarkingfunction could be startedafresh.

    5 Results and Conclusions

    Thefunctionalunitsaresimulatedindividuallybeforetheyareintegratedto developthewholechip. Thefunctionalveri-ficationof thewholechip is doneby performingwatermark-ing on varioustest images. The test imagesare borrowed

  • Second / First

    αminαmaxβ minβ max

    αI

    DataOut

    Visible

    {ImageDataInWatermarkDataIn

    Start

    Reset

    Clock

    Spatial Domain

    Watermarking

    Chip

    Busy

    DataReady

    Figure6: Pin diagram for the Proposed Chip

    (a)OriginalLena (b) WatermarkImage

    (c) UsingAlgorithm 1 (d) UsingAlgorithm 2

    Figure7: Original and Watermarked Images

    from [3, 1] andof dimension y�zéÚ yiz . Fig. 7 shows one

    test image,a watermarkimageused,andwatermarked im-ages.The watermarked imageis alsoshown in Fig. 7. Forfirst algorithm,the valuesof 4 d g , 4 d®�¯ , ¬ d g , and ¬ d®�¯areassumedas svu ¢ky = sÄu ¢�x = sÄu s , and sÄu skê , respectively, andfor secondalgorithm 4 5 is svu sw . The visual inspectionofthewatermarkedimagesprovesthatwatermarkingis abletopreservethequalityof theimagewhile explicitly proving theownership. Of the variousquantitative measuresavailableto quantify thequality of the watermarked images,we usedsignal-to-noiseratio

    9Rë1ìîíÊAassuggestedby [5, 3, 1]. We

    calculatedtheë1ìîí

    usingtheoriginal andthewatermarkedimageusinga softwaresimulator. Simulationresultsshowthatthe

    ë1ìífor variouswatermarkedimagesis in therange

    of swïwð to y�ïwð .

    In this paper, we havepresenteda watermarkingchip thatcanbeintegratedwithin a digital cameraframework for wa-termarkingimages.Thechip hastwo differenttypesof wa-termarkingcapabilities,both in spatialdomain. Out of thetwo watermarkingschemesimplemented,the first onedoespixel-by-pixel processingandthesecondoneis a block-by-block processingalgorithm. Additional work needsto bedoneto developblock-by-blockoperationfor the first algo-rithm so that high performancehardwarecan be designed.However, boththealgorithmsarecomparablefrom the

    ë1ìîípointof view.

    References[1] S. P. Mohanty, “Watermarkingof Digital Images,” M.S. the-

    sis,IndianInstituteof Science,Bangalore,India,1999.

    [2] N. MemonandP. W. Wong, “ProtectingDigital MediaCon-tent,” Comm.of theACM, vol. 41,no.7, pp.34-43,Jul 1998.

    [3] S. P. Mohanty, K. R. Ramakrishnan,andM. S. Kankanhalli,“A DualWatermarkingTechniquefor Images,” in Proc.of the7thACM Intl. MM Conf. (Vol. 2), 1999,pp.49-51.

    [4] L. D. Strycker, et.al., “Implementationof aReal-TimeDigitalWatermarkingProcessfor BroadcastMonitoring on TrimediaVLIW Processor,” IEE Proc. on Vision, Image and SignalProcessing, vol. 147,no.4, pp.371-376,Aug 2000.

    [5] N. J. Mathai,D. Kundur, andA. Sheikholeslami,“HardwareImplementationPerspectivesof Digital Video WatermarkingAlgortithms,” IEEETrans.onSignalProcessing, 2003.

    [6] T. H. TsaiandC. Y Lu, “A SystemLevel Designfor Embed-dedWatermarkTechniqueusingDSC System,” in Proc. oftheIEEE Intl. Workshopon IntelligentSignalProcessingandCommunicationSystem, 2001.

    [7] A. Garimella,et.al., “VLSI Impementationof OnlineDigitalWatermarkingTechniquesWith DifferenceEncodingfor the8-bit GrayScaleImages,” in Proc.of theIntl. Conf. on VLSIDesign, 2003,pp.792-796.

    [8] S. P. Mohanty, N. Ranganathan,andR. K. Namballa, “VLSIImplementationof InvisibleDigital WatermarkingAlgorithmsTowardsthe Developementof a SecureJPEGEncoder,” inProc. of the IEEE Workshopon Signal ProcessingSystems,2003,pp.183-188.

    [9] G. W. Braudaway, K. A. Magerlein,and F. Mintzer, “Pro-tectingPublicly Available Imageswith a Visible ImageWa-termark,” in Proc.of theSPIEConf. on Optical SecurityandCounterfietDeterrenceTechnique, 1996,pp.126-132.

    [10] J. MengandS. F. Chang, “EmbeddingVisible VideoWater-marksin theCompressedDomain,” in Proc.of theIntl. Conf.on Image Processing(Vol. 1), 1998,pp.474-477.

    [11] V. P. Nelson,et.al., Digial Logic AnalysisandDesign, Pren-tice Hall, UpperSaddleRiver, New Jersey, USA, 1995.

    [12] N. H. E. WesteandK. Eshraghian,Principlesof CMOSVLSIDesign: A SystemsPerspective, Addison Wesley, Boston,MA, USA, 1999.