VLSI Design for Yield on Chip Level

IBM Systems and Technology Group

DATE 2006 © 2006 IBM Corporation

VLSI Design for Yield on Chip Level

Markus BühlerJeanne Bickford Jason Hibbeler Jürgen Koehl

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

Outline

Catastrophic Failures

Defect Mechanisms

State of the Art

Novel Techniques

Conclusion

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

Catastrophic Failures

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

Defect Mechanisms: Random Defects

caused by particles

quantitative prediction by Critical Area Analysis (CAA)given defect size x

calculate area where a defect of size x is catastrophic

sum CA over all shapes of design

weighted integrate over all defect sizes: p(x)

shorts opens

x

CA

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

Defect Mechanisms: Systematic FailuresLithography issues

Things don't print as drawn

Design AnalysisLitho-SimulationExpert system approach

point to hot spots on designno quantitative yield prediction

Many other issues (e.g. with CMP)

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

State of the Art

Driven by short sensitivity on aluminumWire spreading increases net length

higher sensitivity to opens

Wire Spreading Redundant Vias

always a good thingslightly higher sensitivity to shorts

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

New Techniques for CopperChanging fail mechanisms

Aluminum: shorts/opens = 3:1 Copper: shorts/opens = 1:1Higher sensitivity to opens

Non-Tree Routing (Kang, 2004) Spreading + Wire Widening

Both approaches have significant timing impact

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

Local Loops• Not every via can be made redundant

68%77.5%88.5%% of redundant vias

Design 390 nm

Design 2130 nm

Design 1130 nm

• More redundancy: local loops

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

Advantages of Local LoopsSimple extension of redundant via approachCan be implemented w/o wrong way wiringLess fault correlation due to higher distance

Critical area reduction is higher than with redundant viasMinimal timing impact

0,0

0,2

0,4

0,6

0,8

1,0

1,2

1,4

1,6

Metal Open Via Open Metal Short

Rel

ativ

e C

ritic

al A

rea

Single viaRed viaRed via + LoopLoopLoop + red via

CAA: 5 ExperimentsSingle via onlyRedundant via onlyRedundant via + local loops Local loops onlyLocal loops + redundant vias

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

Global LoopsKang 2004: augment existing wiring

100%15%100

100%27%20

100%38%10

protectedoverhead*Pins

Traveling Salesman approach*

36%4%50

47%17%10

54%33%5

protectedoverhead*Pins

*P. Panitz, M. Olbrich, IMS, U. Hannover

* compared to minimum Steiner tree * compared to minimum spanning tree

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Global Loops cont.EfficiencyAccumulated Netlength over Pincount

0%

20%

40%

60%

80%

100%

120%

1 2 3 4 5 6 7 8 9 10

Sinks

NetsNet Length

Still some research required!

6%11%overhead

16%17%red. wiring

105pin limit

TSMTree links

Timing issuesTSM in generalboth in case of fault

Comparison is not fair!

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CAA on Library ElementsCAA has long runtimesCAA gives global yield number

no hints where problems arelate feedback

limited use for design tools

Critical area library characterizationperform CAA on each library elementcharacterize possible cell interactioncalculate fail probability for each cell

Possible short in adjacent cells

Perimeter failprobability

enables early yield estimationtools guidance

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

Feature VariationRelative feature variation increases with shrinking technology- dopant density- line width

Features vary independently- Example: wire width variation causes hardware failure

td=1.9nsTclock= 2ns

1.8

2.2

2.0

2.0

budget

-0.10.81.0fastslow

0.31.00.8slowfast

0.10.80.8fastfast

0.11.01.0slowslow

slackAT2AT1M5M4

Variation Aware TimingStatistical Timing

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VLSI Design for Yield on Chip Level © 2006 IBM Corporation

ConclusionDesign for yield is design for low cost and quality

Traditional techniques are not sufficient

Multiple aspects- redundancy- defect robustness- variation robustness

DfY doesn't come for free- timing issues- wiring congestion increase- noise issues

There is a lot to be gained but also a lot to do!