Virtex-6 FPGA GTX Transceiver - Xilinx · 2020. 9. 5. · Virtex-6 FPGA GTX Transceiver Report 7 RPT120 (v1.0) July 30, 2010 Chapter 1 Transceiver Characterization Methodology Test

Virtex-6 FPGA GTX Transceiver

Characterization Report

RPT120 (v1.0) July 30, 2010

Virtex-6 FPGA GTX Transceiver Report www.xilinx.com RPT120 (v1.0) July 30, 2010

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Revision HistoryThe following table shows the revision history for this document.

Date Version Revision

07/30/10 1.0 Initial Xilinx release.

http://www.xilinx.com

Virtex-6 FPGA GTX Transceiver Report www.xilinx.com 3RPT120 (v1.0) July 30, 2010

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 1: Transceiver Characterization MethodologyTest Setup and Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Transmitter Characterization Bench Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Receiver Characterization Bench Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9High Volume Characterization System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Custom Characterization System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ATE Characterization System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Methodology for Line Rate Dependent Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22TX Near-End Output Eye . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22TX Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23TX PLL Bandwidth (Phase Noise Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25TX Output Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27TX Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29TX Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30RX Sinusoidal Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32RX Sinusoidal Jitter Tolerance with CDR Frequency Offset . . . . . . . . . . . . . . . . . . . . . 33RX Input Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34RX CID Run Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Methodology for Line Rate Independent Tests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37TX OOB Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37RX OOB Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Return Loss Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Termination (DC Resistance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42TX Buffer Bypass Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43RX Buffer Bypass Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45TX Lane-to-Lane Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46TX Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47TX Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48RX Stressed Eye Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49RX Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50RX CDR Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Chapter 2: Line Rate Dependent Tests650 Mb/s Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

130 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table of Contents


4 www.xilinx.com Virtex-6 FPGA GTX Transceiver ReportRPT120 (v1.0) July 30, 2010

1250 Mb/s Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59125 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

2500 Mb/s Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63100 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63250 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3072 Mb/s Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7276.8 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72153.6 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74


4250 Mb/s Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86212.5 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86


6250 Mb/s Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98156.25 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98312.5 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

6500 Mb/s Line Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104325 MHz Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Chapter 3: Line Rate Independent TestsTX OOB Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112RX OOB Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118Return Loss Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Termination (DC Resistance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123TX Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125RX Buffer Bypass Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129TX Lane-to-Lane Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130TX Amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131TX Output Rise Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132TX Output Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133TX Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134TX Post-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135RX Stressed Eye Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137RX Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142RX CDR Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142RX Jitter Tolerance vs. REFCLK Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149



Preface

About This Guide

This document is a general characterization report for the Virtex®-6 FPGA GTX transceiver. The measurement results provide a detailed view of the behavior of the transceiver across process, voltage, and temperature (PVT) corners. Although the intent of this document is not to make statements on compliance to specific standards, reasonable inferences can be made based on the testing. Xilinx also produces protocol standard characterization reports that address specific standards.

This report provides a consistent framework for evaluating the various aspects of the PMA transmitter and receiver and not that of the physical coding sublayer (PCS). The same setups are used with the same settings wherever possible. Some tests require differing setups due to their nature. The test setups used for this report are different that those for the specific standards-based characterization reports. Results can differ between these reports due to the nature of the test setup and/or test conditions used in the creation of each report.

Refer to DS152, Virtex-6 FPGA Data Sheet: DC and Switching Characteristics and the Virtex-6 FPGA User Guide for complete information on the Virtex-6 FPGA platforms. For detailed information on the Virtex-6 FPGA GTX transceiver, refer to UG366, Virtex-6 FPGA GTX Transceivers User Guide.

Guide ContentsThis manual contains the following chapters:

• Chapter 1, Transceiver Characterization Methodology.

• Chapter 2, Line Rate Dependent Tests.

• Chapter 3, Line Rate Independent Tests.

Additional ResourcesTo find additional documentation, see the Xilinx website at:

http://www.xilinx.com/support/documentation/index.htm.

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

http://www.xilinx.com/support/documentation/index.htm

http://www.xilinx.com/support


http://www.xilinx.com/support/documentation/data_sheets/ds152.pdf

http://www.xilinx.com/support/documentation/user_guides/ug366.pdf


Preface: About This Guide

ConventionsThis document uses the conventions listed in this section. An example illustrates each convention.

TypographicalThese typographical conventions are used in this document:

Online DocumentThese conventions are used in this document:

Convention Meaning or Use Example

Courier fontMessages, prompts, and program files that the system displays

speed grade: - 100

Italic font

Variables in a syntax statement for which you must supply values

ngdbuild design_name

References to other manualsSee the Command Line Tools User Guide for more information.

Emphasis in textIf a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

Square brackets [ ]

An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required.

ngdbuild [option_name] design_name

Convention Meaning or Use Example

Blue textCross-reference link to a location in the current document

See the section “Additional Resources” for details.

Refer to “Title Formats” in Chapter 1 for details.

Blue, underlined text Hyperlink to a website (URL)Go to http://www.xilinx.com for the latest speed files.




Chapter 1

Transceiver Characterization Methodology

Test Setup and MethodologyCharacterization of a complex analog component requires a variety of test setups to cover all interesting parameters. Where possible, automated test setups are used to enhance the repeatability and the volume of measurements being made. In some instances, bench measurements are required to explore a particular parameter. Table 1-1 identifies how each test was conducted. Three different bench setups and two automatic test equipment (ATE) setups are used.

Table 1-1 shows which hardware setup is used for each of the characterization tests. Refer to each of the Test Setup Overview sections for a more detailed description.

Table 1-1: Characterization Test Setup

Characterization Test Setup

TX Near-End Output Eye RX Characterization Bench

TX Jitter Generation HVC System

TX PLL Bandwidth (Phase Noise Method) RX Characterization Bench

TX Output Rise and Fall Times TX Characterization Bench

TX Pre-Emphasis TX Characterization Bench

RX Sinusoidal Jitter Tolerance HVC System

RX Sinusoidal Jitter Tolerance with CDR Offset

HVC System

RX CDR Bandwidth RX Characterization Bench

RX Input Sensitivity HVC System

RX CID Run Length HVC System

TX Output Amplitude TX Characterization Bench

TX Output Amplitude, Squelched TX Characterization Bench

RX Stressed Eye jitter Tolerance HVC System, RX Characterization Bench

RX Equalization Custom Characterization System, RX Characterization Bench

RX OOB Signal Detect HVC System



Chapter 1: Transceiver Characterization Methodology

Transmitter Characterization Bench SetupThe test setup consists of these components:

• Agilent 86100A high-bandwidth oscilloscope (DCA)

• Agilent 8133A pulse generator

• Custom high-bandwidth (> 26 GHz) switch matrix

• Agilent E3631A/E2646A power supplies

• ML623 GTX transceiver characterization platform with I/O control (UG724, ML623 Virtex®-6 FPGA GTX Transceiver Characterization Board User Guide)

• Platform cable USB DLC9G to configure the DUT

• Host PC with GUI characterization program control

• Thermonics temperature forcing unit

DUT transmitter pairs (TXN/TXP) are connected to the inputs of a very high bandwidth switch matrix. The outputs of the switch matrix connect via DC blocks to the inputs of a 50 GHz DCA plug-in module. The inputs of the DCA module are terminated 50Ω to GND.

The 8133A pulse generator outputs provide GTX transceiver reference clocks and are connected to two MGTCLK pair inputs on the ML623 platform.

The E3631A and E3646A provide programmable power to the individual supplies on the ML623 platform. These supplies include AVTTTX, AVTTRX, AVCCPLL, MGTAVCC, and on-board regulators that provide voltage for VCCO, VCCINT, and VCCAUX of the configured DUT. The voltage of primary interest in this test is AVTTTX.

The ML623 platform has a platform USB cable connected to provide DUT configuration, and a ribbon cable of general I/Os that provides test logic control signals and dynamic reconfiguration port (DRP) read/write commands.

The host PC runs an automated test script that sends instructions to each of the instruments, the DUT, and the DCA, and then records measured values.

The test setup is shown in Figure 1-1. For clarity, only a representative number of cables are included in Figure 1-1.

RX Jitter Transfer Based on Data and Recovered Clock

HVC System, RX Characterization Bench

Termination DC Resistance Custom Characterization System

Return Loss Measurement Custom Characterization System

Power Consumption HVC System (PMA), ATE Test System (PCS)

Table 1-1: Characterization Test Setup (Cont’d)

Characterization Test Setup

http://www.xilinx.com/support/documentation/boards_and_kits/ug724.pdf



Test Setup and Methodology

Receiver Characterization Bench SetupThe receiver characterization bench setup consists of this equipment:

• Agilent J-BERT N4903A bit error rate tester

• Agilent 81133A pulse/pattern generator

• Agilent E3631A power supply

• ML623 GTX transceiver characterization platform with I/O control

• Platform cable USB DLC9G to configure the DUT

• Host PC with GUI characterization program control

The J-BERT provides differential data connected to the DUT RX-side input data. The J-BERT trigger output generates a differential clock used as a DUT TX-side reference clock. The Agilent 81133A pulse/pattern generator generates a DUT RX-side differential reference clock. The differential output data of the DUT is connected to the J-BERT error detector side to measure bit error rates of the DUT. Using two different reference clock sources allows the creation of a PPM offset between the RX- and TX-side reference clocks.

The J-BERT can stress the high-speed output data by injecting different kinds of jitter, such as random jitter, sinusoidal jitter, periodic jitter, bounded uncorrelated jitter, and inter symbol interference with different FR4s.

The E3631A provides programmable power to the individual supplies on the ML623 platform. These include AVTTTX, AVTTRX, AVCCPLL, MGTAVCC, and on-board regulators. The on-board regulators provide voltage for the VCCO, VCCINT, and VCCAUX of the configured DUT. The voltage of primary interest in this test is AVTTTX.

X-Ref Target - Figure 1-1

Figure 1-1: Transmitter Characterization Bench Setup

8133A

86100A

E3631A

ML623GPIO PC

DUT

Pulse Generator

Freq 325.0 MHz Ch:1

1.00V 0.723A 1.20V 0.317A

50 GHz

TXN P3TXP MGTCLKP

MGTCLKN

DCA

Switch Matrix

Power Supply Power Supply

RPT120_c1_01_042710




The ML623 platform has a platform USB cable connected to provide DUT configuration, and a ribbon cable of general I/Os that provide test logic control signals and DRP read/write commands. The host PC runs an automated test script that sends instructions to each of the instruments, the DUT, and the J-BERT, and then records measured values based on the test.

Figure 1-2 and Figure 1-3 show the receiver characterization bench setup and setup block diagram, respectively.X-Ref Target - Figure 1-2

Figure 1-2: Receiver Characterization Bench Setup

RPT120_c1_02_042710





Figure 1-3: Receiver Characterization Bench Setup Block Diagram

81133A81134A

RX REFCLK

TX REFCLK

RX DATA

TX DATA

J-BERT N4903A

ML623

RPT120_c1_03_042710




High Volume Characterization SystemFigure 1-4 and Figure 1-5 show the Agilent ParBERT ATE equipment setup. This equipment includes a fully programmable multi-channel BERT, clock sources, power supplies, and measurement equipment automated to sequence through various test setups and conditions, including reconfiguring the FPGA. The automated temperature forcing equipment is not shown. A DUT loadboard holds an FPGA under test. An FPGA is placed in the board, and the temperature-forcing equipment is placed over the top of the FPGA. The ATE equipment then sequences through the requested tests across voltage, temperature, and specified tests. FPGAs from various process corners are used to capture the process related variances in the GTX PMA transmitter and receiver.X-Ref Target - Figure 1-4

Figure 1-4: High Volume Characterization Setup

RPT120_c1_04_042710




The high volume characterization (HVC) system is a state-of-the-art test system designed specifically for PMA parametric testing. It is based on Agilent’s 81250 13.5 Gb/s ParBERT generator and provides a total of 12 generator and analyzer channels operating in parallel.

The ParBERT generators and analyzers are clocked from separate very low-jitter signal generators permitting both synchronous operation (TX and RX operating at the same data rate), and asynchronous operation (TX and RX operating at different frequencies with a data rate offset).

An arbitrary waveform generator (AWG) provides a modulation source for both sinusoidal jitter tolerance and jitter transfer testing. The AWG can be programmed up to an 80 MHz modulation frequency.

Two pairs of differential low-jitter reference clocks (MGTCLK) are provided from a 3.35 Gb/s data generator to clock the device. The data rate of the 3.35 Gb/s data generator is adjusted to generate the desired clock frequency. The 3.35 Gb/s data generator can be modulated with an AWG for jitter transfer testing.

The HVC system is programmed using Agilent’s VEE GPIB programming language. Use of a programming language offers many benefits including repeatable and efficient operation.

A custom test fixture interfaces the device’s high-speed I/O channels and REFCLK to the ParBERT, provides power, and programs the device. Device configuration is via the JTAG port. Test vectors can also be applied to the device through a 96-channel I/O interface.


Figure 1-5: High Volume Characterization Test Fixture

GPIO

Power

RPT120_c1_05_042710

JTAG

REFCLKTX and RX(12 Channels)

Power




The basic design used for all the test cases connects the device RX to the ParBERT generator and the device TX to the ParBERT analyzer. Output from the parallel RX port is connected to the parallel TX port using FPGA on-chip routing (FPGA loopback).

Configuration files (BIT) used for the HVC were developed using the Xilinx® ISE® design tools. A standard configuration was used in all test cases, as shown in Figure 1-6. The center tap of the RX terminator is connected to GND. The DRP changed the attributes of the device for a particular test.

The DUT was configured using JTAG, and external blocking capacitors were used on the RX pins in all cases.

Figure 1-7 shows the major components of the HVC system. The ParBERT generators and analyzers are clocked independently from very low-jitter signal generators. For composite jitter measurements (combination of SJ, DJ, and RJ), additional FR4 traces can be added to the RX path to provide the necessary Inter Symbol Interference (ISI). GPIB and FireWire from the PC control the equipment/instrument set.


Figure 1-6: Receiver Configuration Used for HVC Characterization

RX Front End~0.8V

RTERM

RPT120_c1_06_042710

GND




Custom Characterization System

Core Setup

Figure 1-8 shows the board configuration in standalone mode (no power module). Shorting the pogo pins across B1 uses the board regulators for the VCCINT, VCCO, and VCCAUX supplies. B2 jumpers disable the System ACE™ tool and complete the JTAG scan chain (through PC4). This allows the basic operation of downloading bitstreams, forcing voltage, and monitoring current. A PC controls the DUT (FPGA) and the temperature forcing unit. Because accessing the GTX transceiver’s DRP is common to all characterizations designs, an on-board oscillator is assigned for DCLK.


Figure 1-7: HVC System Block Diagram

DUTTest Fixture

ParBERT Analyzer(12 Channels)

ParBERT Generator (12 Channels)and MGTCLK

Power Supplies (8 Channels)

PC

MGTCLK

FR4

RX

TX

JTAG

GPIB

FireWire

DSRA

DSRA

DSRB

DSRB

DSRC

RPT120_c1_07_042710




Board Configuration:

• B1 – Board voltage regulators for VCCINT, VCCO, and VCCAUX.

• B2 – Completing the JTAG chain (DUT and System ACE controller).

• B3 – RREF termination calibration resistor.

Equipment:

• E1 – 5VDC brick for supplying the regulators.

• E2 – Agilent (34401A) digital multimeter.

• E3 – FPGA design and temperature control.

• E4 – GTX transceiver external supply. Voltage calibration point close to the part.

• E5 – Silicon Thermal temperature forcing unit and a pneumatic actuator.

• E6 – Oztec low-profile socket for interchanging different DUTs.

FPGA Design Interface:

• F1 – Single-Ended can oscillator for DRP clock.

• F2 – Dedicated REFCLK input.

• F3 – GTX_DUAL tile location.

Voltage and Current Calibration

Bypassing the board regulators provides flexibility on the voltage setting and monitoring of average current. GTX transceiver supply voltage calibrations are measured at the board


Figure 1-8: Custom Characterization System Block Diagram

5Vswitch

OFF ON5VDCPlug+

+VCCINT

1V

+VCCO

2.5V

+VCCAUX

2.5V

-GND

50MHz

DIFF

126RX1 TX1

126RX0 TX0

122TX1 RX1

122RX0 TX0

118118

RX0

TX0TX1 RX1116

116

RX1

TX1 RX0 TX0

114

114

RX1

TX1

RX0 TX0

112RX1

TX1112RX0

TX0

DIFF

120RX0 TX0

120TX1 RX1

124TX0 RX0

124TX1 RX1

OZTEC Socket

FF1136

126X0Y0

122X0Y1

118X0Y2

124X0Y7

120X0Y6

116X0Y5

112X0Y4

114X0Y3

+AVTTTX

1.2V

+AVTTRX

1.2V

-GND

+AVCC

1V

+AVCCPLL

1V

PROG DONE

INIT

ACEPC4

Poweredfrom Board

Regulator

DRPDCLK

34401A DVM

com

I

V+

5VBrick

GNB

GNB

E3631A

E3631A

SiliconThermal

TemperatureForcing Unit

-35oC to 105oC

ExternalGTX TransceiverPower Supplies

ML623

25V/1A

ch1

ch2

ch1

ch2

6V/5A com

GNB

E3631A

25V/1A6V/5A com

E3

E4

F2

F3

F1

E6

E5

E2E1

B2

B3

B1

Parallel

RPT120_c1_08_092710




power plane probe points (close to the DUT). After placing the DUT at its testing operating condition, a voltage calibration technique of force and sense must be applied at the probe point to account for voltage drop from the voltage supply to the probe points shown in Figure 1-9. The voltage should be recalibrated accordingly when additional current is drawn from the supply.

Voltage and Current Calibration Procedures:

1. Power-up the board with no DUT (extract the offset current readings from supply).

2. Download the FPGA test design to the DUT.

3. Place the DUT in its testing operating mode and appropriately calibrate the voltages.

4. Record the average current consumption of the supplies at its testing operating condition.

Synchronous System Setup

The synchronous system setup shown in Figure 1-10 consists of a pattern generator and error detector, an oscilloscope, and two frequency generators. Differential REFCLK generator E2 lacks frequency precision in hundreds of parts per million (PPM). Pulse


Figure 1-9: Custom Characterization System Block Diagram

RPT120_c1_09_042710

Vavccpll

Vavcc

Vtttx

Vttrx




generator E1 provides this tight frequency control. Its single-ended output is connected to the external clock input of E2, synchronizing the two boxes (frequency lock). The REFCLK is an AC link feeding differentially into the DUT. Synchronizing the J-BERT to the REFCLK requires a 10 MHz source from E3 to E1.

The J-BERT is a serial data rate instrument; bit transmission occurs at every rising edge of the high-speed clock. For this particular case, the period of the high-speed clock is the bit time; (1/bit time) is the line rate. The frequency of the high-speed clock is the line rate. The source of the high-speed clock is internally generated coming out of the pattern generator and into the error detector. The transmitter of the pattern generator is connected to the input of the interference channel, and the outputs are DC blocks going into the receiver of the DUT. DC blocks are inserted going the other direction from the DUT transmitter to the J-BERT error detector. The trigger output of the pattern generator is connected to the oscilloscope trigger. The oscilloscope is used for TX measurements and debugging the setup. A large number of GTX transceiver parameters (TX, PLL, and RX) can be extracted from this setup.

Equipment:

• Core setup

• E1 – HP8648 single-ended precision frequency generator

• E2 – HP81130A differential output frequency generator

• E3 – N4903A J-BERT pattern generator and error detector

• E4 – HP86100 DCA oscilloscope


Figure 1-10: Custom Characterization Synchronous System Setup Block Diagram

5Vswitch

OFF ON

5VDCPlug+

+VCCINT

1V

+VCCO

2.5V

+VCCAUX

2.5V

-GND

50MHz

DIFF

126RX1 TX1

126RX0 TX0

122TX1 RX1

122RX0 TX0

118118

RX0

TX0TX1 RX1116

116

RX1

TX1 RX0 TX0

114

114

RX1

TX1

RX0 TX0

112RX1

TX1112RX0

TX0

DIFF

120RX0 TX0

120TX1 RX1

124TX0 RX0

124TX1 RX1

OZTEC Socket

126X0Y0

122X0Y1

118X0Y2

124

X0Y7

120X0Y6

116

X0Y5

112

X0Y4

114X0Y3

+AVTTTX

1.2V

+AVTTRX

1.2V

-GND

+AVCC

1V

+AVCCPLL

1V

PROG DONE

INIT

ACEPC4

86100

trigger

DCA 50 GHz

83484A 54753A

50 GHz module TDR module

ch1

ch2

ch3

ch4

Oscilloscope

GP

IB

10M

Hz

Ref

inou

t

RF Out

C - 3.2GHzB - 2GHz

GP

IB

OUT OUTTriggerOUT OUT

Frequency

clkin

81130A 325.0 MHzPulse GeneratorMax 3GHz

GP

IB

J-BERT 12.5 Gb/s

N4903A

10M

Hz

Ref

inou

t

#J20P1 P1 P2 P2

Extclkin

dataclkin

Trigclk

OUT OUT

IN IN GP

IB

5Vswitch

OFF ON5VDCPlug+

+VCCINT

1V

+VCCO

2.5V

+VCCAUX

2.5V

-GND

50MHz

DIFF

126RX1 TX1

126RX0 TX0

122TX1 RX1

122RX0 TX0

118118

RX0

TX0TX1 RX1116

116

RX1

TX1 RX0 TX0

114

114

RX1

TX1

RX0 TX0

112RX1

TX1112RX0

TX0

DIFF

120RX0 TX0

120TX1 RX1

124TX0 RX0

124TX1 RX1

OZTEC Socket

FF1136

126X0Y0

122X0Y1

118X0Y2

124X0Y7

120X0Y6

116X0Y5

112X0Y4

114X0Y3

+AVTTTX

1.2V

+AVTTRX

1.2V

-GND

+AVCC

1V

+AVCCPLL

1V

PROG DONE

INIT

ACEPC4

RPT120_c1_10_042710

E2

E1

E4

E3

ML623

Pulse Generator

8648 B/C

Pattern Generator

Error Detector

REFCLK

ChannelGore 4 ft.

Cable

DC Block

Reference point of TX measurementsat the end of Gore cable

Core Setup




Figure 1-11 shows a variation of the synchronous setup with flexibility on the USRCLKs frequency. Pulse generators (E1) can independently control the frequency of REFCLK and the GTX transceiver USRCLKs of the DUT.

Asynchronous RX Setup

The setup shown in Figure 1-12 targets the RX circuits (linear equalizer, clock data recovery, and decision feedback equalizer). The internal PRBS checker checks for the validity of the received data. As shown in Figure 1-12, the transmitter (J-BERT) can connect directly to the RX DUT or through the FR4 channel. Figure 1-13 is a variation of Figure 1-12 in which the transmitter comes from the GTX transceiver. The flexibility of Figure 1-13 (board-to-board) allows testing of multiple GTX_DUAL tiles.

Equipment:

• Core setup

• E1 – HP8648 single-ended precision frequency generator

• E2 – HP81130A differential output frequency generator

• E3 – N4903A J-BERT pattern generator and error detector

• E4 – FR4 trace length


Figure 1-11: Custom Characterization Synchronous System with External USRCLK Setup Block Diagram

86100

trigger

DCA 50 GHz

83484A 54753A

50 GHz module TDR module

ch1

ch2

ch3

ch4

Oscilloscope

GP

IB

Pulse Generator

8648 B/C

10 M

Hz

Ref

inou

t

RF Out

C - 3.2 GHzB - 2 GHz

GP

IB


Frequency

clkin

81130A 325.0 MHzPulse GeneratorMax 3 GHz

GP

IB

J-BERT 12.5 Gb/s

Pattern GeneratorN4903A

10M

Hz

Ref

inou

t

Error Detector

#J20P1 P1 P2 P2

Extclkin

dataclkin

Trigclk

OUT OUT

IN IN GP

IB

Pulse Generator

8648 B/C

10 M

Hz

Ref

inou

t

RF Out


GP

IB


Frequency

clkin

81130A 325.0 MHzPulse GeneratorMax 3 GHz

GP

IB

USRCLKs REFCLK

5Vswitch

OFF ON5VDCPlug+

+VCCINT

1V

+VCCO

2.5V

+VCCAUX

2.5V

-GND

50MHz

DIFF

126RX1 TX1

126RX0 TX0

122TX1 RX1

122RX0 TX0

118118

RX0

TX0TX1 RX1116

116

RX1

TX1 RX0 TX0

114

114

RX1

TX1

RX0 TX0

112RX1

TX1112RX0

TX0

DIFF

120RX0 TX0

120TX1 RX1

124TX0 RX0

124TX1 RX1

OZTEC Socket

FF1136

126X0Y0

122X0Y1

118X0Y2

124X0Y7

120X0Y6

116X0Y5

112X0Y4

114X0Y3

+AVTTTX

1.2V

+AVTTRX

1.2V

-GND

+AVCC

1V

+AVCCPLL

1V

PROG DONE

INIT

ACEPC4

RPT120_c1_11_042710

E2

E1

E4

E3

ML623

ChannelGore 4 ft.

Cable

Core Setup





Figure 1-12: Custom Characterization System: RX Setup with TX from the J-BERT

10M

Hz

Ref

inou

t

RF Out

C - 3.2GHzB - 2GHz

GP

IB


Frequency

clkin

325.0 MHzPulse GeneratorMax 3GHz

GP

IB

10M

Hz

Ref

inou

t

#J20P1 P1 P2 P2

Extclkin

dataclkin

Trigclk

OUT OUT

IN IN GP

IBOUT

OUT

IN

IN

-6

26" 36" 56"

-13 -13si

16"

OUT

OUT

IN

IN

10" 15" 20" 30"40"

5Vswitch

OFF ON

5VDCPlug+

+VCCINT

1V

+VCCO

2.5V

+VCCAUX

2.5V

-GND

50MHz

DIFF

126RX1 TX1

126RX0 TX0

122TX1 RX1

122RX0 TX0

118118

RX0

TX0TX1 RX1116

116

RX1

TX1 RX0 TX0

114

114

RX1

TX1

RX0 TX0

112RX1

TX1112RX0

TX0

DIFF

120RX0 TX0

120TX1 RX1

124TX0 RX0

124TX1 RX1

OZTEC Socket

126X0Y0

122X0Y1

118X0Y2

124

X0Y7

120X0Y6

116

X0Y5

112

X0Y4

114X0Y3

+AVTTTX

1.2V

+AVTTRX

1.2V

-GND

+AVCC

1V

+AVCCPLL

1V

PROG DONE

INIT

ACEPC4

REFCLK

RPT120_c1_12_042710

E2

E1

E4

E3

Core Setup

ToDUTRX

2-inch RX Board Trace

ML623

Gore4 Ft.

Cable

FF1136

Channel

3.5-inch J-BERT InternalTrace Default

Pulse Generator

8648 B/C

81130A

Pattern Generator

Error Detector

N4903A

JBERT12.5 Gb/s

Nelco 4000 - FR4

Conexant - FR4


Figure 1-13: Custom Characterization System: RX Setup with TX from GTX Transceiver

10M

Hz

Ref

inou

t

RF Out


GP

IB


Frequency

clkin

325.0 MHzPulse GeneratorMax 3 GHz

GP

IB

OUT

OUT

IN

IN

-6

26" 36" 56"

-13 -13si

16"

OUT

OUT

IN

IN

10" 15" 20" 30"40"

5Vswitch

OFF ON

5VDCPlug+

+VCCINT

1V

+VCCO

2.5V

+VCCAUX

2.5V

-GND

50MHz

DIFF

126RX1 TX1

126RX0 TX0

122TX1 RX1

122RX0 TX0

118118

RX0

TX0TX1 RX1116

116

RX1

TX1 RX0 TX0

114

114

RX1

TX1

RX0 TX0

112RX1

TX1112RX0

TX0

DIFF

120RX0 TX0

120TX1 RX1

124TX0 RX0

124TX1 RX1

OZTEC Socket

126X0Y0

122X0Y1

118X0Y2

124

X0Y7

120X0Y6

116

X0Y5

112

X0Y4

114X0Y3

+AVTTTX

1.2V

+AVTTRX

1.2V

-GND

+AVCC

1V

+AVCCPLL

1V

PROG DONE

INIT

ACEPC4

REFCLK

RPT120_c1_13_042710

Core Setup

ToDUTRX

2-inch RX Board Trace

ML623

Gore4 Ft.

Cable

FF1136

Channel

TX Test Fixture DUT

Pulse Generator

8648 B/C

81130A

10M

Hz

Ref

inou

t

RF Out


GP

IB


Frequency

clkin

325.0 MHzPulse GeneratorMax 3 GHz

GP

IB

5Vswitch

OFF ON

5VDCPlug+

+VCCINT

1V

+VCCO

2.5V

+VCCAUX

2.5V

-GND

50MHz

DIFF

126RX1 TX1

126RX0 TX0

122TX1 RX1

122RX0 TX0

118118

RX0

TX0TX1 RX1116

116

RX1

TX1 RX0 TX0

114

114

RX1

TX1

RX0 TX0

112RX1

TX1112RX0

TX0

DIFF

120RX0 TX0

120TX1 RX1

124TX0 RX0

124TX1 RX1

OZTEC Socket

126X0Y0

122X0Y1

118X0Y2

124

X0Y7

120X0Y6

116

X0Y5

112

X0Y4

114X0Y3

+AVTTTX

1.2V

+AVTTRX

1.2V

-GND

+AVCC

1V

+AVCCPLL

1V

PROG DONE

INIT

ACEPC4

REFCLK

Core Setup

2-inch TX Board Trace

ML623

FF1136

Pulse Generator

8648 B/C

81130A

Nelco 4000 - FR4

Conexant - FR4

E2

E1

E2

E1




ATE Characterization SystemAn ATE system manufactured by Verigy Technology (Figure 1-14) was the primary test system for physical coding sublayer (PCS) characterization. The high-speed channels, clocking, and power resources provided by the 93000 ATE are well suited for this characterization.

Figure 1-15 shows the production loadboard used to interface the DUT to the ATE. The loadboard contains a device socket and controlled impedance connections to the 93000 PS3600 differential clocks. The board contains decoupling capacitors for the FPGA logic supplies (VCCINT/VCCAUX/VCCIO) and L/C filters for the GTX transceiver supplies (AVCC/AVCC_PLL/AVTTTX/AVTTRX).

The test cases extensively use the on-chip FPGA resources and loopback capability in the GTX transceiver. The test case designs were implemented, using a built-in self test (BIST) methodology, to achieve optimal performance using customer available resources.

A custom ATE test program executes the PCS test cases with increasing USRCLK frequency and duty cycle from pass to failure. The results from each of the frequency sweeps were recorded and entered into the characterization database.


Figure 1-14: Verigy 93000 ATE System

RPT120_c1_14_042710




Methodology for Line Rate Dependent Tests

TX Near-End Output Eye

Test Description

This test provides an overall evaluation of the near-end (close to the package) performance of the TX. The device is programmed to output data rates from 750 Mb/s to 6.50 Gb/s. Oversampling is used for data rates below 1.00 Gb/s. The screen captures are provided as representative diagrams only for each of the data rates and are not intended to quantify the device performance.

Test Setup

The RX characterization bench is used for this test with screen captures acquired using the Agilent DCA-J 86100C wide-band oscilloscope, as shown in Figure 1-1, page 9. PRBS data and the trigger for the DCA-J is provided from a 12.5 Gb/s Serial BERT (Agilent J-BERT N4903A).

The device is configured using JTAG to output a PRBS31 pattern on each of the TX data pins, and the resulting eye is captured on the DCA-J for 1000 samples at VNOM and room temperature conditions using TT (typical) device. The automatic alignment feature on the DCA86100B provides a consistent 1.5 UI display for the screen capture.

Table 1-2 lists the setup and conditions for the TX near-end output eye test.


Figure 1-15: Production Loadboard used for PCS Characterization with Thermonics Temperature Controller over DUT

RPT120_c1_15_042710




Test Method

A program stored on the PC provides master control over instruments. It contains the conditions, rates, attributes, and settings at which data is taken. The program executes these steps in order:

1. The supply voltage levels are programmed.

2. The device is configured to transmit the PRBS31 pattern during the measurement at the desired data rate by setting the data rate on the N4904A J-BERT and DUT PLL parameters using the DRP.

3. The transceiver is reset.

4. The DCA-J thresholds and limits are programmed to capture the TX waveform. The TX waveform is accumulated for 1000 samples and stored locally on the DCA-J 86100C.

TX Jitter Generation

Test Description

This test determines the jitter at the near-end of the TX. The total jitter (TJ) comprises two components of jitter: deterministic jitter (DJ) and random jitter (RJ). TJ, DJ, and RJ are related by Equation 1-1.

Equation 1-1

RJ is Gaussian and is specified for a BER < 10E-12 at 95% confidence. RJ can either be specified as a root mean square (RMS) value, also called peak-to-peak (pk-pk). The pk-pk value can be calculated from the RMS value as shown in Equation 1-2.

Equation 1-2

The industry-standard Bathtub Method is used to estimate RJ to BER < 10E-12. Some standards allow for the use of band-pass filtering to remove some of the jitter energy. All

Table 1-2: TX Near-End Output Eye Test Setup and Conditions

Parameter Value

Measurement Instrument DCA-J 86100C wide-band oscilloscope using the 86118A 70 GHz remote sampling module plug-in. The DCA-J is triggered from the trigger output of the J-BERT (N4903A).

TX Coupling/Termination AC coupled, using a DC blocker into 100Ω differential (50Ω single ended to GND) termination (DCA-J 86100C).

Process, Voltage, and Temperature (PVT)

Typical/Nominal.

Pattern PRBS31 generated from the J-BERT (N4903A).

Loadboard ML623 (FF1156).

TX Amplitude/Pre-Emphasis

Maximum amplitude: TXDIFFCTRL = 111.

REFCLK Sourced from J-BERT, AC coupled to MGTCLK_116 and MGT_CLK_118 using a splitter. The amplitude is 945 mVp-p (measured at the REFCLK inputs).

TJ DJ RJ pk-pk( )+=

pk-pk 14 RMS×=




data in this report is collected with the Agilent Parallel BERT (ParBERT) analyzer in broadband (no filtering applied).

The test system itself introduces both DJ and RJ, which increases the overall total jitter measured at the TX. The reported value for TX jitter generation includes a small offset for these additional components. Because of the random nature of RJ, the values must be calculated using RMS methods.

Test Setup

TX jitter data was collected using the HVC system. Data for 12 GTX transceiver channels was collected simultaneously. The primary instrument used to collect the data was an Agilent ParBERT analyzer. The instrument determines the BER at various sample points across the TX eye. The data was analyzed in the ParBERT, and the resulting DJ and RJ were reported back to the controlling test program.

The overall design of the configuration is shown in Figure 1-16. The RX input of the GTX transceiver is driven by the ParBERT generator. The data is recovered on the RX parallel port and applied to the TX parallel port. The connections between the GTX transceiver parallel ports are made through the FPGA logic. The parallel data is serialized in the TX section of the GTX transceiver and appears at the TX output.

The device is configured using JTAG. Power is supplied from eight programmable power supplies through connectors on the side of the test fixture.

Table 1-3 lists the setup and conditions for the TX jitter generation test.


Figure 1-16: TX Jitter Generation Test Setup Block Diagram

Table 1-3: TX Jitter Generation Test Setup and Conditions

Parameter Value

Measurement Instrument HVC ParBERT Analyzer

TX Coupling/Termination AC coupled into 100Ω differential

GTX Transceiver

TX

RX

REFCLK

DataAnalyzer

DataGenerator

ParBERT

SerialData

ParallelData

FPGA HVCRPT120_c1_16_042710




Test Method

A VEE program running on the PC provides master control over instruments through the GPIB. It contains the conditions, rates, attributes, and settings at which data is taken. The program executes these steps in order:

1. The supply voltage levels are programmed, and the Thermonics temperature controller adjusts the ambient until the desired junction temperature is achieved.

2. The device is configured to transmit a PRBS7 pattern and a PRBS31 pattern during the measurement at the desired data rate by setting the data rate on the ParBERT generator and DUT PLL parameters using the DRP.


4. Under program control, the ParBERT scans across the TX Eye (time) and determines BER at each point. The entire data set is analyzed by the ParBERT and reports DJ and RJ (at BER=10E-12) back to the program.

TX PLL Bandwidth (Phase Noise Method)

Test Description

This test characterizes TX jitter using a spectrum analyzer (phase noise meter). The spectrum analyzer is a powerful tool that can quickly and accurately determine TX jitter, both Broadband and Filtered, and determine the PLL bandwidth. In previous transceiver generations, this parameter was characterized using the TX reference clock to TX output jitter transfer.

Test Setup

The measurement method used for the TX PLL bandwidth uses the RX characterization bench in addition to the Agilent E4448A spectrum analyzer. Use of a spectrum analyzer allows improved accuracy measurements of the –3 dB transition frequency of the PLL without the need of an external reference.

The intrinsic noise in the GTX transceiver is used to make the measurements, so no external jitter source is required. The test setup is shown in Figure 1-17. The N4901A serial BERT is used only as a low-jitter clock source for the GTX transceiver REFCLKs.

The E4448A spectrum analyzer is connected directly to the TX output through a DC blocker.

PVT All corners

Pattern PRBS7 and PRBS31 from HVC ParBERT Data Generator

Test Fixture Custom FF1136 HVC test fixture using a low-profile Zero Insertion Force (ZIF) socket

TX Amplitude/Pre-Emphasis

Maximum amplitude: TXDIFFCTRL = 111, Pre-Emphasis = 000 (no pre-emphasis)

REFCLK Differential low-jitter clocks sourced from dedicated ParBERT channel programmed with a clock pattern (101010…)

Table 1-3: TX Jitter Generation Test Setup and Conditions (Cont’d)

Parameter Value




Table 1-4 lists the setup and conditions for the TX PLL bandwidth test.


Figure 1-17: TX PLL Bandwidth Setup Block Diagram

ML623

N4901A

E4448A

REFCLKSplitter

TX Monitor

LowJitterClock

Source

RPT120_c1_17_042710




Test Method

A Perl program running on the PC provides master control over instruments through the GPIB. It contains the conditions, rates, attributes, and settings at which data is to be taken. The program executes these steps in order:


2. The device is configured to transmit a clock pattern (0101010…) during the measurement at the desired data rate by setting the data rate on the Serial BERT generator and the DUT PLL parameters using the DRP.


4. The built-in features of the E4448A spectrum analyzer collect the TX spectrum. A Perl script processes the spectrum to determine PLL loop bandwidth (–3 dB) and the equivalent jitter across the frequency spectrum.

TX Output Rise and Fall Times

Test Description

This test measures the TX rise time (TRTX) and TX fall time (TFTX) of the waveform generated by the GTX transmitter output for various TX amplitude settings and data rates. TRTX and TFTX are measured from the 20% to 80% and 80% to 20% points of the transmitter amplitude, respectively. Rise and fall times are measured in picoseconds.

Test Setup

TRTX and TFTX measurements are made on the TX bench. The device is configured to output a low-frequency clock pattern using five 1s and five 0s (1111100000…). A DCA 86100A high-speed oscilloscope takes the measurements. A wide-band 20 GHz plug-in amplifier, Agilent 86112A, ensures accurate measurements.

Table 1-5 lists the setup and conditions for the TX output rise and fall times test. Figure 1-18 shows the bench setup.

Table 1-4: TX PLL Bandwidth Test Setup and Conditions

Parameter Value

Measurement Instrument E4448A Spectrum Analyzer.

TX Coupling/Termination Single ended, AC coupled into 50Ω to GND.

PVT All corners.

Pattern Clock pattern (10101…) generated internally in the FPGA logic.

Test Fixture ML623 FF1156 test fixture using a low-profile socket.

TX Amplitude/Pre-Emphasis Maximum amplitude: TXDIFFCTRL = 111. Pre-Emphasis = 000 (no pre-emphasis).

REFCLK Differential low-jitter clocks sourced from Serial BERT.




Table 1-5: TX Output Rise and Fall Times Test Setup and Conditions

Parameter Value

Measurement Instrument Agilent 86100A DCA mainframe, Agilent 86112A 20 GHz plug-in amplifier

TX Coupling/Termination Differential, AC coupled into 50Ω to GND

PVT All corners

Pattern Five 1s and five 0s clock pattern (1111100000…) generated internally in the FPGA logic

Test Fixture ML623 FF1156 test fixture using a low-profile ZIF socket

TX Amplitude/Pre-Emphasis Three TX amplitude settings: TXDIFFCTRL = 000, 100, and 111. Pre-Emphasis = 000 (no pre-emphasis)

REFCLK Differential low-jitter clocks sourced from the Agilent 8133A pulse generator


Figure 1-18: TX Bench Setup for TX Output Rise and Fall Times

8133A

86100A DCA

Signal Generator

Trigger

REFCLK

RPT120_c1_18_042710

ML623




Test Method

A Perl program running on the PC provides master control over instruments through GPIB. It contains the conditions, rates, attributes, and settings at which data is to be taken. The program executes these steps in order:

1. The supply voltage levels are programmed and the Thermonics temperature controller adjusts the ambient until the desired junction temperature is achieved.

2. The device is configured to transmit a five 1s and five 0s clock pattern (1111100000…) during the measurement at the desired operating conditions and DUT PLL parameters using the DRP.


4. The built-in features of the 86100A DCA are used to collect the TX rise time (20%–80%) and fall time (80%–20%) data.

TX Amplitude

Test Description

This test measures the TX amplitude across data rates without any TX pre-emphasis, and with a 111110000 binary pattern to observe the effects of the data rate.

Test Setup

The setup used is the TX characterization bench in the most common configuration, as described in Transmitter Characterization Bench Setup, page 8.

Table 1-6 lists the setup and conditions for the TX amplitude test.

Test Method

These steps are executed in order:

1. The DUT is soaked until the temperature sensor reads the required temperature.

2. The FPGA is configured via iMPACT.

Table 1-6: TX Amplitude Test Setup and Conditions

Parameter Value



PVT All corners



TX Amplitude/Pre-Emphasis All TX amplitude settings: TXDIFFCTRL = 0000 through 1111. Pre/post-emphasis = 000 (no pre-emphasis)





3. The pattern generated by the Serial BERT is transmitted at the specified data rate to the RX input of the device.

4. The TX differential pk-pk output amplitude is measured using the Agilent 86100A high-bandwidth oscilloscope.

TX Pre-Emphasis

Test Description

This test measures the TX eye amplitude at all data rates. Losses in the channel can be modeled as a low-pass filter. Pre-emphasis adds high-frequency components to the TX eye to minimize the effect of these losses. The test uses the built-in features of the 86100A DCA to measure the outer and the inner eye of the TX waveform and calculate pre-emphasis in decibels. The outer and inner eye for this test is shown in Figure 1-19.

Pre-emphasis is calculated as shown in Equation 1-3.

Equation 1-3

Test Setup

TX pre-emphasis measurements are made on the TX bench. The device is configured to output a low-frequency clock pattern using five 1s and five 0s (1111100000…). A DCA 86100A high-speed oscilloscope makes the measurements. A wide-band 20 GHz plug-in amplifier, Agilent 86112A, ensures accurate measurements.

Table 1-7 lists the setup and conditions for the TX eye pre-emphasis test. Figure 1-20 shows the bench setup.


Figure 1-19: Inner and Outer TX Eye Used for Pre-Emphasis Calculation

RPT120_c1_19_042710

OUTER INNER

dB 20 inner outer⁄( )log=




Table 1-7: TX Eye Pre-Emphasis Test Setup and Conditions

Parameter Value



PVT All corners



TX Amplitude/Pre-Emphasis TX amplitude MAX setting: TXDIFFCTRL = 1111. All TX Pre-Emphasis settings from 00000 through 11111.



Figure 1-20: TX Pre-Emphasis Bench Setup Block Diagram

8133A

86100A DCA

Signal Generator

Trigger

REFCLK

RPT120_c1_20_042710

ML623




Test Method

A Perl program, running on the PC, provides master control over instruments through GPIB. It contains the conditions, rates, attributes, and settings at which data is taken. The program executes these steps in order:


2. The device is configured to transmit a five 1s and five 0s clock pattern (1111100000…) during the measurement at the desired data rate by setting the data rate on the serial BERT generator and DUT PLL parameters using the DRP.


4. The built-in features of the 86100A DCA are used to collect the TX outer and inner eye. The outer eye is measured using the Vpk-pk built-in function of the DCA, and the inner eye is measured using the VAMP built-in function.

Following data collection of the outer and inner eye, the pre-emphasis is calculated in decibels.

RX Sinusoidal Jitter Tolerance

Test Description

This test determines the tolerance of the receiver to high-frequency sinusoidal jitter (SJ). PRBS data with added SJ provides a good metric for the CDR’s ability to recover data. For lower jitter frequencies, the RX PLL can track the jitter and make the jitter tolerance look very good. Applying the jitter at high frequency, in this case 80 MHz, is beyond the loop bandwidth of the RX PLL so the reported jitter tolerance does not include any tracking by the PLL.

Test Setup

This test uses the HVC in the standard configuration. SJ is applied to the RX data by modulating the ParBERT data generator with an 80 MHz sine wave. 80 MHz was chosen because it is greater than the RX PLL loop bandwidth, resulting in no jitter tracking by the PLL.

Table 1-8 lists the setup and conditions for the RX sinusoidal jitter tolerance test.

Table 1-8: RX Sinusoidal Jitter Tolerance Test Setup and Conditions

Parameter Value



PVT All corners

Pattern PRBS7 and PRBS31

Test Fixture Custom FF1156 HVC test fixture using a low-profile ZIF socket




Test Method

A VEE program running on the HVC PC provides master control over instruments through GPIB. It contains the conditions, rates, attributes, and settings at which data is taken. The program executes these steps in order:


2. The device is configured with JTAG using loopback configuration.


4. PRBS7 and PRBS31 data is applied to the RX with increasing SJ until errors are detected at the TX output. The test is run for sufficient time so the results can be specified to BER < 1E-12.

RX Sinusoidal Jitter Tolerance with CDR Frequency Offset

Test Description

This test determines the tolerance of the RX to a combination of high-frequency SJ and asynchronous data (frequency offset). Under these conditions, the RX CDR is stressed simultaneously by both the SJ and the CDR frequency offset. The test is very similar to the RX sinusoidal jitter tolerance test (see RX Sinusoidal Jitter Tolerance), but in addition to applying SJ, the RX data is also offset from the normal data rate by ±100 ppm and ±1000 ppm.

A data pattern with added SJ provides a good metric for the CDR’s ability to recover data. For lower jitter frequencies, the RX PLL can track the jitter and make the jitter tolerance look very good. Applying the jitter at high frequency, in this case 80 MHz, is beyond the loop bandwidth of the RX PLL, so the reported jitter tolerance does not include any tracking by the PLL. Adding frequency offset to the RX data requires the CDR to constantly track the PPM offset.

Test Setup

This test uses the HVC in the standard configuration. SJ is applied to the RX data by modulating the ParBERT data generator with an 80 MHz sine wave. 80 MHz was chosen because it is greater than the RX PLL loop bandwidth, resulting in no jitter tracking by the PLL. The ParBERT system has separate very low-jitter signal generators for the REFCLK and the RX data. These signal generators are programmed through VEE to apply an offset between the TX and the RX data. The resulting combination (SJ + frequency offset) is applied to the data test pattern to stress the receiver under test to failure.

Table 1-9 lists the setup and conditions for the TX PLL bandwidth test.

RX Configuration/Amplitude RX configured for 100Ω differential termination (center tap to GND), AC coupled using both internal and external capacitors

REFCLK ParBERT E48160B 3.35 Gb/s generator

Table 1-8: RX Sinusoidal Jitter Tolerance Test Setup and Conditions (Cont’d)

Parameter Value




Test Method

A VEE program, running on the HVC’s PC, provides master control over instruments through GPIB. It contains the conditions, rates, attributes, and settings at which data is to be taken. The program executes these steps in order:

1. The supply voltage levels are programmed and the Thermonics temperature controller adjusts the ambient until the desired junction temperature is achieved.



4. COMMA data is applied to the RX with increasing SJ and ±100 ppm and ±1000 ppm frequency offsets until errors are detected at the TX output. The test is run for sufficient time so that the results can be specified to BER < 1 < 1E-12.

RX Input Sensitivity

Test Description

This test determines the minimum amplitude that must be applied at the RX pins to achieve reliable operation at BER < 1E-12.

Table 1-10 lists the setup and conditions for the RX input sensitivity test.

Table 1-9: RX SJ Tolerance with CDR Frequency Offset Test Setup and Conditions

Parameter Value



PVT All corners

Pattern COMMA data with SJ and frequency offset (±100 and ±1000 ppm)

Test Fixture Custom FF1156 HVC test fixture using a low-profile ZIF socket



Table 1-10: RX Input Sensitivity Test Setup and Conditions

Parameter Value



PVT All corners


Test Fixture Custom FF1156 test fixture using a low-profile ZIF socket




Test Setup

This test uses the HVC in the standard configuration.

Test Method

A VEE program, running on the HVC’s PC, provides master control over instruments through GPIB. It contains the conditions, rates, attributes, and settings at which data is to be taken. The program executes these steps in order:




4. The amplitude of the PRBS data applied to the RX is set to 400 mV pk-pk and monitored on the TX. The auto-alignment feature of the ParBERT synchronizes the RX and TX data. All 12 channels available on the HVC should be operating.

5. The amplitude of the PRBS data is reduced by 15 mV, and the TX is monitored for errors. The test is exited on fail.

RX CID Run Length

Test Description

This test determines the maximum number of consecutive identical digits (CID) that can be sent to the RX without error. The test stresses the RX PLL, which requires transitions in the RX data to recover clock and data.

Test Setup

This test uses the HVC in the standard configuration. The ParBERT data generator provides the CID pattern. The pattern was developed to be DC balanced (same number of 0s and 1s), and padded to fit on a memory boundary. Figure 1-21 shows the format of the pattern.

Increasing the CID run length eventually causes the RX PLL to become unstable, resulting in single-bit errors. For devices that use a digital CDR (interpolator), the RX CID performance is very good and far exceeds the requirements (80 consecutive 0s or 1s).



Table 1-10: RX Input Sensitivity Test Setup and Conditions (Cont’d)

Parameter Value


Figure 1-21: RX CID Run Length Pattern

PRBS31 All 1s forRun Length

All 0s forRun Length

PRBS31 PAD

RPT120_c1_21_071210




The pattern has PRBS31 training sections before the consecutive 0s and 1s, which allows the CDR to lock onto the data. The training sections are followed by a stress test with increasing numbers of 0s and 1s. RX patterns are developed for each CID run length, so the granularity on the test is coarse. The longest CID run length is 800,000 consecutive 0s and 1s.

Pattern formats are available for these run lengths: 36, 80, 128, 256, 512, 750, 1024, 1200, 1500, 2000, 4000, 6000, 8000, 10000, 30000, 50000, 70000, 100000, 125000, 150000, 175000, 200000, 250000, 400000, and 800000.

Table 1-11 lists the setup and conditions for the RX CID run length test.

Test Method

A VEE program, running on the HVC’s PC, provides master control over instruments through the GPIB. It contains the conditions, rates, attributes, and settings at which data is to be taken. The program executes these steps in order:




4. The amplitude of the PRBS data applied to the RX is set to 400 mV pk-pk and monitored on the TX. The auto-alignment feature of the ParBERT synchronizes the RX and TX data. All 12 channels available on the HVC should be operating.

5. Separate RX data patterns, with increasing CID run length, are applied to the device and the BER is determined. The test exits on first fail.

Table 1-11: RX CID Run Length Test Setup and Conditions

Parameter Value



PVT All corners

Pattern CID with increasing 0s and 1s

Test Fixture Custom FF1156 test fixture using a low-profile ZIF socket





Methodology for Line Rate Independent Tests


TX OOB Signal

Test Description

The TXOOB circuitry has two parameters of interest that are measured in this test:

1. TTXOOBTRANS: This is the delay time from assertion of the TXELECIDLE signal to squelch.

2. VTXOOBVDPP: This is the amplitude of the squelch signal.

Test Setup

The TXOOB testing was performed on the TX bench setup. One notable change to the setup was the inclusion of a real-time oscilloscope (Tektronix model TDS5104) instead of the DCA. The real-time scope directly connected to the TXN and TXP outputs of the GTX transceivers under test. An additional signal important to the test is the TXELECIDLE signal that enters the DUT and simultaneously arrives at the PCS port TXELECIDLE and the trigger for the real-time scope. In this way, the delay time TTXOOBTRANS can be accurately measured, as can the VTXOOBVDPP of the squelched signal.

Table 1-12 lists the setup and conditions for the TX OOB signal test.

Test Method

The device is configured to transmit a comma pattern. The TXELECIDLE signal is applied, and the amplitude and delay of the resultant squelched output are measured.

RX OOB Signal Detect

Test Description

The RX OOB signal detect circuitry has two parameters of interest that are measured in this test:

1. VRXOOBVDPP: This is the receiver input threshold that trips the peak-detector and causes the RXELECIDLE signal to transition.

Table 1-12: TX OOB Signal Test Setup and Conditions

Parameter Value

Measurement Instrument Tektronix model TDS5104 oscilloscope


PVT All corners

Pattern Comma


RX Configuration/Amplitude N/A

REFCLK Differential low-jitter clocks sourced from the 81133A Signal Generator




2. TRXELECIDLE: This is the latency for the RX input to receive an electrical idle and the signal detect signal to transition out of the PCS.

Test Setup

VRXOOBVDPP and TRXELECIDLE are measured on two separate setups. The RXOOB thresholds are measured on the HVC system as described in High Volume Characterization System, page 12. The ParBERT channels are connected to the RX under test. The high bandwidth of the HVC setup allows for calibrated inputs into the 12 RX channels that are tested at once.

The TRXELECIDLE is measured in close conjunction with the TTXOOBTRANS with the TX characterization bench configured with the real-time scope in place of the DCA. One of the DUT transmitters acts as the stimulus and feeds, via a splitter, into the RX under test and the real-time scope.

Table 1-13 lists the setup and conditions for the RX OOB signal detect test.

Test Method

VRXOOBVDPP is measured as follows:

1. The device is configured with the HVC providing data to 12 GTX transceivers and all 12 RXOOB electrical idles are individually monitored.

2. The input data pattern and data rate are provide to the RX under test. Typically, this is a COMMA or PRBS7 pattern at PCI Express® specification or SATA protocol rates.

3. The amplitude of the stimulus signal is lowered from 400 mV while RXOOB electrical idle is monitored. The trigger point is recorded.

4. Optionally, the test is repeated in reverse to check for hysteresis.

5. The test is repeated across OOBDETECT_THRESHOLD settings.

TRXELECIDLE is measured as follows:

1. The device is configured on the ML623 platform with a GTX TX connected, via a splitter, to both the RX under test and a real-time oscilloscope.

2. The TXELECIDLE is asserted, the TX amplitude squelches, and the RXELECIDLE port is asserted.

Table 1-13: RX OOB Signal Detect Test Setup and Conditions

Parameter Value

Measurement Instrument Tektronix model TDS5104 oscilloscope


PVT All corners

Pattern Comma







3. The delay between the two events in step 2 is captured on the real-time oscilloscope.

4. The OOB threshold and the TX pre-squelch amplitude are varied to see if there is any dependence on the delay time.

Figure 1-22 shows the input on the lower trace, and the RXELECIDLE port on the upper trace. The response time TRXELECIDLE is the difference between the two.

Power Consumption

Test Description

The dynamic power consumption of the various GTX transceiver supplies are measured as the GTX transceiver operates in different modes, with different attributes, at different data rates, at different voltages, and at different temperatures.

The power for GTX transceivers is generally given on a GTX_DUAL tile basis as indicated in Equation 1-4.

Equation 1-4

where N is the number of GTX transceivers in a test case. The data is fed into the XPE for accuracy and ease of unique customer design prediction.

Test Setup

Several test fixtures are used. The supplies on the ATE can accurately force a voltage and measure the current. A feedback sense line returns to each individual supply to ensure that the proper voltage is applied.

Table 1-14 lists the setup and conditions for the power consumption test.


Figure 1-22: RX OOB Signal Detect Transition Delay (TRXELECIDLE)RPT120_c1_22_042710

PGTX_Dual_PMA 2 PAVCCPLL N⁄× PAVCC PAVTTTX PAVTTRX+ +( ) N⁄+=




Test Method


1. The device is powered up, configured, and baseline current measurements are taken.

2. The device begins operating, but not the GTX transceivers while more baseline measurements are taken.

3. The selected reference clock frequency for the appropriate line rate is applied and current measurements are taken.

4. Attributes of interest are changed.

Return Loss Measurements

Test Description

Many existing and emerging signaling standards require S-parameter measurements to ensure interoperability. The return loss (S11), a measure of the transmitted versus reflected power, is measured on both the TX and RX.

Test Setup

The vector network analyzer (VNA) interfaces to the host PC through the GPIB. After the measurement parameters are set, calibration begins. Four cables are included in the calibration process. VNA measurements are independent of voltage and are accurate up to 11 GHz. The ML62x test fixture requires an on-board oscillator for overriding the termination value. A digital multimeter (DVM) confirms that the differential resistance is 100Ω before the measurement.

Table 1-15 lists the setup and conditions for the return loss measurements test.

Table 1-14: Power Consumption Test Setup and Conditions

Parameter Value

Measurement Instrument Verigy 93000 DPS (digital power supplies)

TX Coupling/Termination DC Coupled to RX

PVT All corners

Pattern PRBS31

Test Fixture Verigy 93000 Loadboard

RX Configuration/Amplitude DC Coupled from TX

REFCLK Verigy P3600 Differential Clock Cards

Table 1-15: Return Loss Measurements Setup and Conditions

Parameter Value

Measurement Instrument HP8720ES Vector Network Analyzer

TX Coupling/Termination Differential, DC coupled into 50Ω to GND

PVT Process corners, typical voltage, room temperature

Frequency Sweep 50 MHz to 11 GHz (10 MHz steps)




The return loss measurement test setup block diagram is shown in Figure 1-23.

Test Fixture ML623 test fixture with 1-inch board trace using a low-profile ZIF socket


REFCLK N/A

Source Power 0 dBm

Averaging Calibration 1

Intermediate Frequency (IF) 100 Hz

Table 1-15: Return Loss Measurements Setup and Conditions (Cont’d)

Parameter Value


Figure 1-23: Return Loss Measurement Setup Block Diagram

20 GHzVector

NetworkAnalyzer

RX - Pair

TX - Pair

8720ES

GP

IB

port 1

port 2

port 3

port 4

2 Ft. Green Cable 5Vswitch

OFF ON5VDCPlug+

+VCCINT

1V

+VCCO

2.5V

+VCCAUX

2.5V

-GND

50MHz

DIFF

126RX1 TX1

126RX0 TX0

122TX1 RX1

122RX0 TX0

118118

RX0

TX0TX1 RX1116

116

RX1

TX1 RX0 TX0

114

114

RX1

TX1

RX0 TX0

112RX1

TX1112RX0

TX0

DIFF

120RX0 TX0

120TX1 RX1

124TX0 RX0

124TX1 RX1

OZTEC Socket

FF156

126X0Y0

122X0Y1

118X0Y2

124X0Y7

120X0Y6

116X0Y5

112X0Y4

114X0Y3

+AVTTTX

1.2V

+AVTTRX

1.2V

-GND

+AVCC

1V

+AVCCPLL

1V

PROG DONE

INIT

ACEPC4

SerialGPIBUSB

PCChipScope

34401A DVM

com

I

V+ GPIB

TE: 1-inch 114ML623

E2

E1

RPT120_c1_23_042710




Test Method


1. The VNA is calibrated.

2. The FPGA is configured.

3. The differential resistance on the RX is set to 100Ω.

4. The DVM is used to measure the RX channel to confirm the termination resistance.

5. The results for the RX are measured and saved.

6. The FPGA is configured.

7. The differential resistance on the TX is set to 100Ω.

8. The DVM is used to measure the TX channel to confirm the termination resistance.

9. The results for the TX are measured and saved.

Termination (DC Resistance)

Test Description

The DC termination across the TXN – TXP pins is measured when the TX is powered down. The DC termination across the RXN – RXP pins is measured when the RX is configured to be AC coupled and GND terminated (PCIe mode). The REFCLKN – REFCLKP differential termination is measured when configured for use.

Test Setup and Test Method

The TX termination is measured with a DVM under condition (1) as shown in Figure 1-24.

The RX termination is measured with a DVM under condition (1) as shown in Figure 1-25.


Figure 1-24: TX Termination (DC Resistance) Test Setup Block Diagram

34401A

DVM

TXP

TXN

ROUT

ROUT = (RDRVR

RDRVR >> RTERM

RDRVR

RTERM) + (RDRVR

RDRVR

RDRVR

5-bit Resistor Code

MeasurementPath

TestConditions

TX drvr pdown

5 txrx Termprog

RTERM

RTERM

RTERM)

com

I

V+

1

RDRVR < RTERMTX ELECIDLE2

RDRVR << RTERMTX ELECIDLE

TXDIFFCTRL = 111

TXDIFFCTRL = 000

3

RPT120_c1_24_042710




The REFCLK termination is measured with a DVM under condition (2) as shown in Figure 1-26.

TX Buffer Bypass Margin

Test Description

Some applications require a deterministic or lower latency in the GTX TX datapath. Deterministic or lower latency is obtained by bypassing the TX buffer. While this offers some advantages, there is a maximum amount of timing margin when bypassing the TX buffer. The amount of timing margin on TXUSRCLK after phase alignment is measured and referred to as the TX buffer bypass margin.


Figure 1-25: RX Termination (DC Resistance) Test Setup Block Diagram


Figure 1-26: REFCLK Termination (DC Resistance) Test Setup Block Diagram

34401A

DVM

RXP

CommonMode

Generator

RXN

RIN

Smallest Ground

Moderate 2/3 Supply

Small 5/6 Supply

RIN = 2RTERM + RCMGRCMG VCM

5 bit Resistor Code

MeasurementPath

TestConditions

Gnd Termination

5 txrx Termprog

RTERM

RCMG

RTERM

com

I

V+

1

2/3 Termination2

VTTRX Termination3

RPT120_c1_25_042710

34401A

DVM

REFCLKP

CommonMode

Generator

REFCLKN

RIN

Adds ParasiticResistance in

Series

2/3MGTAVTTX

NegligiblySmall

Ground

RIN = 2RCLKERM + 2ro + RCMG

RCMG VCM

MeasurementPath

TestConditions

AC-Link

RCLKERM

ro

ro

RCMG

RCLKERM

com

I

V+

1

DC-Link2

RPT120_c1_26_042710

FixedResistors

Switches




Test Setup

The TX buffer bypass margin is measured through proprietary self-testing techniques. At a high level, the GTX transceiver is configured in near-end PMA loopback mode with the TX buffer bypassed. Using the ATE system, power for the various power supplies and clean external reference clocks are provided.

Table 1-16 lists the setup and conditions for the TX buffer bypass margin test.

The DUT is configured with the design shown in Figure 1-27. This configuration mode is similar to that recommended in UG366, Virtex-6 FPGA GTX Transceivers User Guide. Figure 1-27 provides a visual definition for advance and delay with respect to the TXUSRCLK immediately after the TX phase alignment operation.

Test Method


1. The DUT is brought to the desired voltage and temperature corner.

2. The device is configured with all GTX transceivers operating PRBS31 data in near-end PMA loopback mode.

Table 1-16: TX Buffer Bypass Margin Test Setup and Conditions

Parameter Value

Measurement Instrument Verigy 93000 ATE

TX Coupling/Termination N/A

PVT All corners

Pattern PRBS31





Figure 1-27: TX Buffer Bypass Margin Test Setup Block Diagram

REFCLKOUTTXUSRCLKTXUSRCLK2

RXRECCLKRXUSRCLK

GTX Transceiver

RXUSRCLK2

CLKN

CLK0

CLKFB

DCM

BUFG

BUFG

BUFG

RPT120_c1_27_042710

Advance

Delay

AdvancedTXUSRCLK

TXUSRCLKAfter Set Phase

Time

DelayedTXUSRCLK

TXUSRCLKAfter Set Phase

Time





3. The phase alignment is performed as recommended in the Virtex-6 FPGA GTX Transceivers User Guide.

4. The timing margin between clock domains is measured.

5. The frequency is increased to the next test point, and step 3 and step 4 are repeated.

RX Buffer Bypass Margin

Test Description

Some applications require a deterministic or lower latency in the GTX RX datapath. Deterministic or lower latency is obtained by bypassing the RX buffer. While this offers some advantages, there is a maximum amount of timing margin when bypassing the RX buffer. The amount of timing margin on RXUSRCLK after phase alignment is measured and referred to as the RX buffer bypass margin.

Test Setup

The RX buffer bypass margin is measured through proprietary self-testing techniques. At a high level, the GTX transceiver is configured in near-end PMA loopback mode with the RX buffer bypassed. Using the ATE system, power for the various power supplies and clean external reference clocks are provided.

Table 1-17 lists the setup and conditions for the RX buffer bypass margin test.

The DUT is configured with the design shown in Figure 1-28. This configuration mode is similar to that recommended in UG366, Virtex-6 FPGA GTX Transceivers User Guide. Figure 1-28 provides a visual definition for advance and delay with respect to the RXUSRCLK immediately after the RX phase alignment operation.

Table 1-17: RX Buffer Bypass Margin Test Setup and Conditions

Parameter Value

Measurement Instrument Verigy 93000 ATE

TX Coupling/Termination N/A

PVT All corners

Pattern PRBS31








Test Method


1. The DUT is brought to the desired voltage and temperature corner.

2. The device is configured with all GTX transceivers operating PRBS31 data in near-end PMA loopback mode.

3. The phase alignment is performed as recommended in UG366, Virtex-6 FPGA GTX Transceivers User Guide.

4. The timing margin between clock domains is measured.

5. The frequency is increased to the next test point, and step 3 and step 4 are repeated.

TX Lane-to-Lane Skew

Test Description

The skew between transmitter lanes across the FPGA is measured. There is some skew on the TXUSRCLK clock, clock jitter, finite resolution in the alignment circuitry, and different electrical flight delays between channels in the package. All of this contributes to the TX lane-to-lane skew being non-zero.

Test Setup

The test setup used is the TX characterization bench. Several different transmitters are used to attempt to locate the worst-case locations. A GTX transceiver at the top of a column versus a GTX transceiver in the middle of a column generally has the worst-case skew.

Table 1-18 lists the setup and conditions for the TX lane-to-lane skew test.


Figure 1-28: RX Buffer Bypass Margin Test Setup Block Diagram

RPT120_c1_28_042710

REFCLKOUTTXUSRCLKTXUSRCLK2

RXRECCLK

BUFG

BUFG

CLKN

CLK0

CLKFB

DCM

BUFG

RXUSRCLK

GTX Transceiver

RXUSRCLK2

Advance

Delay

AdvancedRXUSRCLK

RXUSRCLKAfter Set Phase

Time

DelayedRXUSRCLK

RXUSRCLKAfter Set Phase

Time





Test Method


1. The device is configured to transmit a repeating pattern of 160 0s followed by 160 1s.

2. TX phase alignment is performed as described in UG366, Virtex-6 FPGA GTX Transceivers User Guide on all lanes being measured.

3. The delay between rising edges on all transmitters under test is measured.

TX Amplitude

Test Description

The TXDIFFCTRL GTX transceiver provides variable amplitude control to the transmitter. This test measures the varying amount of TX amplitude with each setting. It is done at a single line rate without any TX pre-emphasis, and with a 111110000 binary pattern to observe exclusively the effects of varying the TXDIFFCTRL.

Test Setup

The setup used is the TX bench in the most common configuration, as described in Transmitter Characterization Bench Setup, page 8.

Table 1-19 lists the setup and conditions for the TX amplitude test.

Table 1-18: TX Lane-to-Lane Skew Test Setup and Conditions

Parameter Value



PVT All corners

Pattern 160 0s followed by 160 1s




Table 1-19: TX Amplitude Test Setup and Conditions

Parameter Value



PVT (Process, Voltage, and Temperature)

All corners






Test Method





4. The TX differential peak-to-peak output amplitude is measured using the Agilent 86100A high-bandwidth oscilloscope.

TX Emphasis

Test Description

The TXEMPHASIS port provides variable emphasis control to the transmitter. This test measures the varying amount of TX emphasis with each setting. It is done at a single line rate, at a single TXDIFFCTRL setting, and with a 111110000 binary pattern to observe exclusively the effects of varying the TXEMPHASIS.

Test Setup

The setup used is the TX bench in the most common configuration, as described in Transmitter Characterization Bench Setup, page 8.

Table 1-20 lists the setup and conditions for the TX emphasis test.


TX Amplitude/Pre-Emphasis All TX amplitude settings (TXDIFFCTRL = 0000 through 1111)


Table 1-19: TX Amplitude Test Setup and Conditions (Cont’d)

Parameter Value

Table 1-20: TX Emphasis Test Setup and Conditions

Parameter Value



PVT All corners






Test Method





4. The TX differential peak-to-peak output amplitude is measured using the Agilent 86100A high-bandwidth oscilloscope at two points in the resultant waveform. The ratio of the two is the emphasis as –20*log(VBIG/VSMALL).

RX Stressed Eye Tolerance

Test Description

The RX of a transceiver generally operates under a stressed condition. This test increases the amount of stress and measures the balance of the link margin. Typically, a channel, jitter, and a data pattern in certain combinations are used to create stress, and various RX attributes are changed to observe if margin increases or decreases. For GTX transceivers, bounded uncorrelated jitter (BUJ) is used to measure margin.

Test Setup

The RX J-BERT setup is configured such that the ML623 platform is connected to the RX under test. The J-BERT with jitter option and the jitter board option provide a calibrated stress level.

Table 1-21 lists the setup and conditions for the RX stressed eye tolerance test.

TX Amplitude/Emphasis All TX emphasis settings (TXEMPHASIS = 0000 through 1111)


Table 1-20: TX Emphasis Test Setup and Conditions (Cont’d)

Parameter Value

Table 1-21: RX Stressed Eye Tolerance Test Setup and Conditions

Parameter Value

Measurement Instrument Agilent J-BERT N4903A bit error rate tester


PVT All corners


Test Fixture ML623 FF1156 HVC test fixture using a low-profile ZIF socket





Test Method


1. The device is configured with the J-BERT sending 6.5 Gb/s PRBS7 data to the RX under test.

2. The device deserializes the incoming data stream, loops it back in FPGA logic, and transmits back synchronous data to the analyzer of the J-BERT.

3. The RX under test has attribute RXEQMIX = 10. A loop is constructed that performs these steps:

• The length of FR4 is swept from 9 inches to 44 inches.

• The DFETAP1 settings are set in manual mode and cycled from 0 to 31.

• BUJ sweeps from 0 UI of tolerance to 0.6 UI. As a calibration point, BUJ typically measured approximately 0.1 UI lower than 20 MHz SJ.

This test was performed on several devices across process; all exhibited similar performance. For presentation purposes, the results show the amount of BUJ that can be injected across different FR4 channel lengths into a typical RX device operating at approximately 55°C and VNOM while maintaining a BER of less than 1e-12. In a stressed eye condition, RXEQMIX is expected to be either 10 (6 dB) or 00 (10 dB). The data pattern is expected to be similar to PRBS7 or PRBS31, so this data is shown. Only typical, nominal, and 55°C conditions are presented.

RX Equalization

Test Description

This test characterizes the effectiveness of the GTX receiver linear equalizer to equalize the channel loss related ISI component of deterministic jitter.

Test Setup

This test used the Agilent Serial J-BERT with the interference channel option. The Agilent J-BERT interference channel has several FR4 trace length options that can be inserted in the receive datapath into the DUT.

The GTX RX equalizer is tested for each of the possible equalization settings and when the equalization is disabled. The Agilent Serial J-BERT generates data that is passed through the selected trace length from the interference channel, looped RX to TX through the GTX transceiver under test, and bit errors are monitored at the J-BERT error detector. For each of the equalization settings, the interference channel trace length is increased in 4-inch steps until errors are detected. When errors are detected, the interference channel length is reverted back to the previous passing length, and the test is run for five minutes to ensure that the link is solid and is passing with no errors. The test is repeated for each of the possible equalization settings and when the equalizer is disabled. The complete set of tests is repeated at one high-end, one mid-range, and one lower data range frequency.

REFCLK Agilent J-BERT N4903A Differential Trigger Out

RXEQMIX Settings 00, 10

Table 1-21: RX Stressed Eye Tolerance Test Setup and Conditions (Cont’d)

Parameter Value




After passing trace length data is collected for each case, trace length dB loss is measured at one-half the frequency of each data rate tested. The ISI-related DJ component of each passing trace length at each tested data rate is measured using the Agilent DCA-J communications analyzer. The PRBS 2E7 data pattern is used, which the DCA-J communications analyzer can resolve into jitter components more easily and accurately.

Table 1-22 lists the setup and conditions for the RX equalization test.

Test Method


1. The device is configured with the J-BERT, sending 4.5 to 6.5 Gb/s data to the RX under test.

2. The device deserializes the incoming data stream and checks the FPGA logic for errors.

3. A loop is constructed that performs these steps:

• RXEQMIX is swept from 00 to 11.

• The FR4 length is swept from 9 inches to 44 inches.

• The DFETAP1 settings are set in manual mode and cycled from 0, 7, 15, and 31.

RX CDR Bandwidth

Test Description

The CDR PPM test verifies the clock data recovery (CDR) unit performance of GTX transceivers when a PPM frequency offset exists between the incoming data rate and reference clock (asynchronous operation).

This test quantifies the maximum PPM tolerance under various CDR configurations and supplies the jitter tolerance frequency profile for a given PPM. The CDR has first- and second-order feedback loops, which let the CDR track the incoming data with wider frequency differences. To achieve the best CDR performance, these loop settings should be optimized based on the PPM offsets and incoming data jitter frequency and amplitude.

Table 1-22: RX Equalization Test Setup and Conditions

Parameter Value

Measurement Instrument Agilent J-BERT N4903A bit error rate tester


PVT All corners


Test Fixture ML623 FF1156 HVC test fixture using a low-profile ZIF socket


REFCLK HP 81130A Differential Output Frequency Generator

RXEQMIX Settings 00, 01, 10, 11




This test was performed in user-selectable PPM offset modes and CDR step sizes. Currently, those are any combination of synchronous mode with 0 ppm offset to asynchronous mode with ±6000 ppm offset.

Test Setup

The three important components of this test are:

1. J-BERT bench setup

2. Programmable clock source

3. Device configuration

In the first component, the J-BERT performs the CDR PPM test. It generates data for the RX side and can modulate the data with jitter to determine margin by frequency. The J-BERT compares the returned data and determines the BER of the RX under test. The J-BERT also provides the reference clock for the TX-side transmitter used as the return path to the J-BERT. This is key, because it allows the J-BERT to generate and analyze data synchronously even though the RX can have a large PPM offset.

The second component, the Agilent 81133A clock source, generates the reference clock for the RX-side receiver with the desired PPM offset, as given by Equation 1-5.

Equation 1-5

The use of the 81133A as the REFCLK source for the RX under test causes a nearly 0.1 UI drop in jitter tolerance. This drop results from the increased noise RJ of the REFCLK compared to the J-BERT trigger out.

To correct the phase difference between the incoming data and reference clock, and to cross the RX-side to TX-side clock domains, the device configuration shown in Figure 1-29 is implemented.

RX REFCLK Frequency Data Rate Gbs[ ] 1.0e6⁄( ) PPM Offset 1.0e6⁄( )+=




Table 1-23 lists the setup and conditions for the RX CDR frequency tolerance test.

As shown in Figure 1-29, the incoming data is sampled and written to the RX buffer in the RXRECCLK domain. This time domain (indicated by the dashed lines) is frequency offset by the amount programmed on the 81133A, as mentioned earlier. The data is then read from the RX FIFO with the TXOUTCLK clock, which is in the TX reference clock domain. This clock domain (indicated by the dotted lines) is frequency-locked to the J-BERT. In this way, the RX CDR tracks out the PPM delta and, using the RX FIFO, allows for the injection of high amounts of UI at low frequency. Using a separate GTX transceiver for data return from the GTX RX under test, the PPM offset has been maintained, jitter is injected, and the J-BERT is left as the test controller (generator and checker).


Figure 1-29: RX CDR Bandwidth Test Setup FPGA Block Diagram

Table 1-23: RX CDR Frequency Tolerance Test Setup and Conditions

Parameter Value

Measurement Instrument Agilent J-BERT N4903A Bit Error Rate Tester


PVT Typical Process, Nominal Voltage, 55°C Temperature

Pattern PRBS7 and PRBS31 data with increasing frequency (PPM) offset


RX Configuration/Amplitude RX configured for 100Ω differential termination (center tap to GND), AC coupled

REFCLK Agilent J-BERT N4903A Differential Trigger Out

PISO

SIPO

XCL

XCL

TXUSRCLK

TXUSRCLK

RXUSRCLK

RXUSRCLK

Phase Adjust FIFO

RX Elastic Buffer

FPGATX

Interface

FPGARX

Interface

TXOUTCLK

RXRECCLK

RX

RX REFCLKfrom Agilent81133A

TX REFCLKfrom J-BERT

TXTX Driver

RX CDR

Shared PMAPLL Divider

Shared PMAPLL Divider

RPT120_c1_29_042710




Test Method


1. The device is configured with the J-BERT sending 4.25, 5.0, and 6.5 Gb/s data to the RX under test.

2. Attributes are written via the DRP:

• PMA_RX_CFG [0]: Enable/disable the second-order loop filter.

• PMA_RX_CFG [5:2]: Set the first-order loop filter.

• PMA_RX_CFG [10:6]: Set the second-order loop filter.

3. The PPM frequency offset is increased.

4. The J-BERT sweeps SJ from 23 KHz to 10 MHz.

5. The CDR bandwidth is measured.



Chapter 2

Line Rate Dependent Tests

The descriptions, setups, and methods for the tests in this chapter are described in Methodology for Line Rate Dependent Tests, page 22.

This chapter contains the following sections:

• 650 Mb/s Line Rate, page 56











Chapter 2: Line Rate Dependent Tests

650 Mb/s Line Rate

130 MHz Reference Clock

TX Jitter Generation Measurement

The test conditions are described in TX Jitter Generation, page 23.

RX Sinusoidal Jitter Tolerance (SJ = 20 MHz)

The test conditions are described in RX Sinusoidal Jitter Tolerance, page 32.

Table 2-1: 650 Mb/s Line Rate PLL Settings

Data Rate (Mb/s)

PLL Frequency (Mb/s)

REFCLK Frequency (MHz)

PLL_DIVSEL_REFPLL_DIVSEL_FB

and DIVPost

DividerOversample

650 1200 130 1 2 * 5 = 10 4 1


Figure 2-1: TX Jitter Generation Measurement (650 Mb/s, 130 MHz)

TJ

0

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.

3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.57

0

100

200

300

400

500

600

Num

ber

of D

ata

Poi

nts

RPT120_c2_01_071410(UI)

Table 2-2: TX Jitter Generation Measurement (650 Mb/s, 130 MHz)

Parameter Min Max Avg Stdev Units

TX Jitter Generation Measurement_650_130_TJ 0.04 0.07 0.05 0.01 UI



650 Mb/s Line Rate




Figure 2-2: RX Sinusoidal Jitter Tolerance (650 Mb/s, 130 MHz)

Table 2-3: RX Sinusoidal Jitter Tolerance (650 Mb/s, 130 MHz)


RX Sinusoidal Jitter Tolerance (SJ = 20 MHz) 0.17 0.17 0.17 0 UI

Notes: 1. All measurements are instrument limited.

JT20M_0PPM

0

0.05 0.1

0.15 0.2

0.25 0.

3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.95

0

100

200

300

400

500

600

RPT120_c2_02_071410

Num

ber

of D

ata

Poi

nts

(UI)



JT80M_0PPM

0

0.05 0.1

0.15 0.2

0.25 0.

3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.95

0

100

200

300

400

500

600

RPT120_c2_03_071410

Num

ber

of D

ata

Poi

nts

(UI)





The test conditions are described in RX Input Sensitivity, page 34.

RX CID Run Length

The test conditions are described in RX CID Run Length, page 35.






Figure 2-4: RX Input Sensitivity (650 Mb/s, 130 MHz)

Table 2-5: RX Input Sensitivity (650 Mb/s, 130 MHz)


RX Input Sensitivity 22.5 90 44.5 15.93 mV

RXSEN

0 35 70 105

140

175

210

245

280

315

350

385

420

455

490

525

560

595

630

665

0

50

150

100

200

250

350

300

400

RPT120_c2_04_071410

Num

ber

of D

ata

Poi

nts

(mV)



1250 Mb/s Line Rate

1250 Mb/s Line Rate



The test conditions are described in TX Near-End Output Eye, page 22.


Figure 2-5: RX CID Run Length (650 Mb/s, 130 MHz)

Table 2-6: RX CID Run Length (650 Mb/s, 130 MHz)


RX CID Run Length On 25 280 119.5 40.2 UI

RX CID Run Length Off 8000 14000 10612.44 1500.77 UI

400

350

300

250

200

150

100

50

00 10 102 103

Run Length (UI)

Num

ber

of D

ata

Poi

nts

104 105

RUNLENGTH_CAPONRUNLENGTH_CAPOFF

RPT120_c2_05_061610


Data Rate (Mb/s)

PLL Frequency(Mb/s)

REFCLK Frequency(MHz)


and DIVPost

DividerOversample

1250 2500 125 1 4 * 5 = 20 4 1







Figure 2-6: TX Near-End Output Eye (1250 Mb/s, 125 MHz)

RPT120_c2_06_060610



TJ250

300

350

200

150

100

50

0

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570

Num

ber

of D

ata

Poi

nts

RPT120_c2_07_071410(UI)



1250 Mb/s Line Rate








TX Jitter Generation Measurement_1250_125_DJ 0.01 0.06 0.04 0.01 UI

TX Jitter Generation Measurement_1250_125_RJ 0.04 0.08 0.05 0.01 UI







JT20M_OPPM

500

600

400

300

200

100

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.

4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_08_071410(UI)












JT80M_OPPM

600

500

400

300

200

100

00.

05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_09_071410(UI)



RXSEN

400

350

300

250

200

150

100

50

0

35 105

175

245

315

385

455

525

595

6650 70 140

210

280

350

420

490

560

630

Num

ber

of D

ata

Poi

nts

RPT120_c2_10_071410(UI)



2500 Mb/s Line Rate

2500 Mb/s Line Rate










Data Rate (Mb/s)

PLL Frequency(Mb/s)

REFCLK Frequency(MHz)


and DIVPost

DividerOversample

2500 2500 100 1 5 * 5 = 25 2 1

2500 2500 250 1 2 * 5 = 10 2 1



RPT120_c2_11_060610








TJ

250

200

150

100

50

00.

03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.38

0.39

0.42

0.45

0.48

0.51

0.54

0.570

Num

ber

of D

ata

Poi

nts

RPT120_c2_12_071410(UI)




TX Jitter Generation Measurement_2500_100_DJ 0 0.14 0.03 0.03 UI




JT20M_OPPM

500

600

400

300

200

100

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_13_071410(UI)



2500 Mb/s Line Rate



RX Sinusoidal Jitter Tolerance with +2000 PPM CDR Offset (SJ = 80 MHz)

The test conditions are described in RX Sinusoidal Jitter Tolerance with CDR Frequency Offset, page 33.











JT80M_0PPM

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.95

0

100

200

300

400

500

600

RPT120_c2_14_071410

Num

ber

of D

ata

Poi

nts

(UI)




RX Sinusoidal Jitter Tolerance with –2000 PPM CDR Offset (SJ = 80 MHz)



Figure 2-15: RX Sinusoidal Jitter Tolerance with +2000 PPM CDR Offset (2500 Mb/s, 100 MHz)

JT80M_POSMPPM

160

140

120

100

80

60

40

20

00.

05

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85

0.950

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

Num

ber

of D

ata

Poi

nts

RPT120_c2_15_071410(UI)

Table 2-16: RX Sinusoidal Jitter Tolerance with +2000 PPM CDR Offset (2500 Mb/s, 100 MHz)


RX Sinusoidal Jitter Tolerance with +2000 PPM CDR Offset (SJ = 80 MHz) 0.48 0.52 0.52 0 UI


Figure 2-16: RX Sinusoidal Jitter Tolerance with –2000 PPM CDR Offset (2500 Mb/s, 100 MHz)

JT80M_NEGMPPM

160

140

120

100

80

60

40

20

00.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95

Num

ber

of D

ata

Poi

nts

RPT120_c2_16_071410(UI)

Table 2-17: RX Sinusoidal Jitter Tolerance with –2000 PPM CDR Offset (2500 Mb/s, 100 MHz)


RX Sinusoidal Jitter Tolerance with –2000 PPM CDR Offset (SJ = 80 MHz) 0.51 0.52 0.52 0 UI



2500 Mb/s Line Rate











RXSEN

450

400

350

300

250

200

150

100

50

0

35 70 105

140

175

210

245

280

315

350

385

420

455

490

525

560

595

630

6650

Num

ber

of D

ata

Poi

nts

RPT120_c2_17_071410(mV)








RPT120_c2_18_060610



TJ

250

200

150

100

50

0

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570

Num

ber

of D

ata

Poi

nts

RPT120_c2_19_071410(UI)



2500 Mb/s Line Rate















JT20M_OPPM

600

500

400

300

200

100

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.

4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_20_071410(UI)











JT80M_0PPM

0

0.05 0.1

0.15 0.2

0.25 0.

3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.95

0

100

200

300

400

500

600

RPT120_c2_21_071410

Num

ber

of D

ata

Poi

nts

(UI)



JT80M_POSMPPM

160

140

120

100

80

60

40

20

00.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95

Num

ber

of D

ata

Poi

nts

RPT120_c2_22_071410(UI)



RX Sinusoidal Jitter Tolerance with +2000 PPM CDR Offset (SJ = 80 MHz) 0.48 0.52 0.52 0 UI



2500 Mb/s Line Rate







JT80M_NEGMPPM

160

140

120

100

80

60

40

20

00.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95

Num

ber

of D

ata

Poi

nts

RPT120_c2_23_071410(UI)



RX Sinusoidal Jitter Tolerance with –2000 PPM CDR Offset (SJ = 80 MHz) 0.5 0.52 0.52 0 UI



RXSEN

450

400

350

300

250

200

150

100

50

0

35 70 105

140

175

210

245

280

315

350

385

420

455

490

525

560

595

630

6650

Num

ber

of D

ata

Poi

nts

RPT120_c2_24_071410(mV)




3072 Mb/s Line Rate

76.8 MHz Reference Clock









Data Rate (Mb/s)




and DIVPost

DividerOversample

3072 3072 76.8 1 5 * 4 = 20 2 1

3072 3072 153.6 1 5 * 4 = 20 2 1


Figure 2-25: TX Near-End Output Eye (3072 Mb/s, 76.8 MHz)

TJ

250

200

150

100

50

0

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570

Num

ber

of D

ata

Poi

nts

RPT120_c2_25_071410(UI)

Table 2-26: TX Near-End Output Eye (3072 Mb/s, 76.8 MHz)


TX Near-End Output Eye_3072_76.8_TJ 0.14 0.32 0.21 0.03 UI

TX Near-End Output Eye_3072_76.8_DJ 0 0.16 0.05 0.04 UI

TX Near-End Output Eye_3072_76.8_RJ 0.12 0.23 0.17 0.02 UI



3072 Mb/s Line Rate




Figure 2-26: RX Sinusoidal Jitter Tolerance (3072 Mb/s, 76.8 MHz)

Table 2-27: RX Sinusoidal Jitter Tolerance (3072 Mb/s, 76.8 MHz)


RX Sinusoidal Jitter Tolerance (SJ = 80 MHz) 0.45 0.64 0.64 0.01 UI

JT80

450

400

350

300

250

200

150

100

50

00.

05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_26_071410(UI)


Figure 2-27: RX Input Sensitivity (3072 Mb/s, 76.8 MHz)

Table 2-28: RX Input Sensitivity (3072 Mb/s, 76.8 MHz)



RXSEN

350

300

250

200

150

100

50

0

35 70 105

140

175

210

245

280

315

350

385

420

455

490

525

560

595

630

6650

(mV)

Num

ber

of D

ata

Poi

nts

RPT120_c2_27_071410











TJ

250

200

150

100

50

0

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570

Num

ber

of D

ata

Poi

nts

RPT120_c2_26_071410(UI)

Table 2-29: TX Near-End Output Eye (3072 Mb/s, 153.6 MHz)


TX Near-End Output Eye _3072_153.6_TJ 0.06 0.19 0.11 0.02 UI

TX Near-End Output Eye _3072_153.6_DJ 0.05 0.14 0.07 0.01 UI

TX Near-End Output Eye _3072_153.6_RJ 0.03 0.15 0.04 0.03 UI



3072 Mb/s Line Rate








JT80M_0PPM

450

400

350

300

250

200

150

100

50

00.

05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_29_071410





RX Input Sensitivity 9 130.5 58.88 15.86 mV

RXSEN

350

300

250

200

150

100

50

0

35 70 105

140

175

210

245

280

315

350

385

420

455

490

525

560

595

630

6650

(mV)

Num

ber

of D

ata

Poi

nts

RPT120_c2_30_071410




3200 Mb/s Line Rate







Data Rate (Mb/s)




and DIVPost

DividerOversample

3200 1600 160 1 2 * 5 = 10 1 1

3200 3200 320 1 2 * 5 = 10 2 1



RPT120_c2_31_061610



3200 Mb/s Line Rate





TJ

300

250

200

150

100

50

0

Num

ber

of D

ata

Poi

nts

RPT120_c2_32_071410

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570

(UI)








JT20M_OPPM

180

160

140

120

100

80

60

40

20

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.90

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85

0.95

0.05

Num

ber

of D

ata

Poi

nts

RPT120_c2_33_071410(UI)
















JT80M_OPPM

450

400

350

300

250

200

150

100

50

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_34_071410(UI)



3200 Mb/s Line Rate





JT80M_POSMPPM

70

60

50

40

30

20

10

00.

05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_35_071410(UI)



RX Sinusoidal Jitter Tolerance with +2000 PPM CDR Offset (SJ = 80 MHz) 0.39 0.6 0.52 0.04 UI



JT80M_NEGMPPM

90

80

70

60

50

40

30

20

10

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_36_071410(UI)



RX Sinusoidal Jitter Tolerance with –2000 PPM CDR Offset (SJ = 80 MHz) 0.4 0.6 0.51 0.03 UI













RX Input Sensitivity 22.5 103.5 52.7 16.41 mV

RXSEN

450

400

350

300

250

200

150

100

50

0

Num

ber

of D

ata

Poi

nts

RPT120_c2_37_071410

35 70 105

140

175

210

245

280

315

350

385

420

455

490

525

560

595

630

6650

(mV)



3200 Mb/s Line Rate





RPT120_c2_38_061610



TJ

250

200

150

100

50

0

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570

Num

ber

of D

ata

Poi

nts

RPT120_c2_39_071410(UI)


















JT20M_OPPM

400

350

300

250

200

150

100

50

0

Num

ber

of D

ata

Poi

nts

RPT120_c2_40_071410

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

(UI)



3200 Mb/s Line Rate








JT80M_OPPM

500

600

400

300

200

100

00.

05 0.1

0.15 0.2

0.25 0.3

0.35 0.

4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_41_071410(UI)



JT80M_POSMPPM

80

70

60

50

40

30

20

10

0

0.05

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85

0.950

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Num

ber

of D

ata

Poi

nts

RPT120_c2_42_071410(UI)













JT80M_NEGMPPM

120

100

80

60

40

20

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_43_071410(UI)






RXSEN

400

350

300

250

200

150

100

50

0

35 105

175

245

315

385

455

525

595

6650 70 140

210

280

350

420

490

560

630

Num

ber

of D

ata

Poi

nts

RPT120_c2_44_071410(mV)



4250 Mb/s Line Rate

4250 Mb/s Line Rate










Data Rate (Mb/s)




and DIVPost

DividerOversample

4250 2125 212.5 1 2 * 5 = 10 1 1



RPT120_c2_45_061610







Figure 2-46: TX Jitter Generation Measurement (4250 Mb/s, 212.5 MHz)

TJ

300

250

200

150

100

50

0

Num

ber

of D

ata

Poi

nts

RPT120_c2_46_071410

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570

(UI)

Table 2-46: TX Jitter Generation Measurement (4250 Mb/s, 212.5 MHz)


TX Jitter Generation Measurement_4250_212.5_TJ 0.13 0.29 0.17 0.03 UI

TX Jitter Generation Measurement_4250_212.5_DJ 0 0.13 0.05 0.02 UI

TX Jitter Generation Measurement_4250_212.5_RJ 0.08 0.21 0.13 0.02 UI



JT20M_OPPM

250

200

150

100

50

0

Num

ber

of D

ata

Poi

nts

RPT120_c2_47_071410

0.05

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85

0.950

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

(UI)



4250 Mb/s Line Rate













JT80M_OPPM

200

180

160

140

120

100

80

60

40

20

0

Num

ber

of D

ata

Poi

nts

RPT120_c2_48_071410

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.

4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

(UI)







Figure 2-49: RX Sinusoidal Jitter Tolerance with ±100 PPM CDR Offset (4250 Mb/s, 212.5 MHz)

JT80M_POSMPPM

80

70

60

50

40

30

20

10

00.

05

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85

0.950

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

Num

ber

of D

ata

Poi

nts

RPT120_c2_49_071410(UI)

Table 2-49: RX Sinusoidal Jitter Tolerance with ±100 PPM CDR Offset (4250 Mb/s, 212.5 MHz)




Figure 2-50: RX Sinusoidal Jitter Tolerance with –2000 PPM CDR Offset (4250 Mb/s, 212.5 MHz)

JT80M_NEGMPPM

60

50

40

30

20

10

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_50_071410(UI)



4250 Mb/s Line Rate



Table 2-50: RX Sinusoidal Jitter Tolerance with –2000 PPM CDR Offset (4250 Mb/s, 212.5 MHz)








RXSEN

400

350

300

250

200

150

100

50

0

35 105

175

245

315

385

455

525

595

6650 70 140

210

280

350

420

490

560

630

Num

ber

of D

ata

Poi

nts

RPT120_c2_51_071410(mV)




5000 Mb/s Line Rate







Data Rate (Mb/s)




and DIVPost

DividerOversample

5000 2500 100 1 5 * 5 = 25 1 1

5000 2500 250 1 2 * 5 = 10 1 1



TJ

140

120

100

80

60

40

20

0

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_52_071410








5000 Mb/s Line Rate








140

120

100

80

60

40

20

00.

05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_53_071410

JT80





RX Input Sensitivity 44 104 66.8 13.05 mV

RXSEN

200

180

160

140

120

100

80

60

40

20

0

35 70 105

140

175

210

245

280

315

350

385

420

455

490

525

560

595

630

6650

(mV)

Num

ber

of D

ata

Poi

nts

RPT120_c2_54_071410











RPT120_c2_55_061610



5000 Mb/s Line Rate





TJ

300

250

200

150

100

50

0

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_56_071410

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570








JT20M_OPPM

160

140

120

100

80

60

40

20

0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.05

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85

0.95

Num

ber

of D

ata

Poi

nts

RPT120_c2_57_071410(UI)
















JT80M_OPPM

200

180

160

140

120

100

80

60

40

20

0

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_58_071410

0.05 0.

1

0.15 0.

2

0.25 0.

3

0.35 0.4

0.45 0.

5

0.55 0.

6

0.65 0.

7

0.75 0.

8

0.85 0.

9

0.950



5000 Mb/s Line Rate





70

60

50

40

30

20

10

00.

05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_59_071410

JT80M_POSMPPM

(UI)






70

60

50

40

30

20

10

0

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

Num

ber

of D

ata

Poi

nts

RPT120_c2_60_071410

JT80M_NEGMPPM

(UI)














RXSEN

400

350

300

250

200

150

100

50

0

35 105

175

245

315

385

455

525

595

6650 70 140

210

280

350

420

490

560

630

Num

ber

of D

ata

Poi

nts

RPT120_c2_61_071410(mV)



6250 Mb/s Line Rate

6250 Mb/s Line Rate







Data Rate (Mb/s)




and DIVPost

DividerOversample

6250 3125 312.5 1 2 * 5 = 10 1 1

6250 1562.5 156.25 1 3 * 5 = 10 1 1



140

120

100

80

60

40

20

0

0.03

0.06

0.09

0.12

0.15

0.13

0.21

0.24

0.27 0.

3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_62_071410

TJ















JT80

100

90

80

70

60

50

40

30

20

10

00.

05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_63_071410






RXSEN

300

250

200

150

100

50

0

35 70 105

140

175

210

245

280

315

350

385

420

455

490

525

560

595

630

6650

(mV)

Num

ber

of D

ata

Poi

nts

RPT120_c2_64_071410



6250 Mb/s Line Rate








RPT120_c2_65_061610








TJ

250

200

150

100

50

0

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_66_071410

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570




TX Jitter Generation Measurement_6250_312.5_DJ 0.01 0.16 0.09 0.03 UI




JT20M_OPPM

160

140

120

100

80

60

40

20

0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.05

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85

0.95

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_67_071410



6250 Mb/s Line Rate













JT80M_OPPM

180

160

140

120

100

80

60

40

20

0

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_68_071410

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.05

0.15

0.25

0.35

0.45

0.55

0.65

0.75

0.85

0.95









RXSEN

200

180

160

140

120

100

80

60

40

20

0

Num

ber

of D

ata

Poi

nts

RPT120_c2_69_071410

35 105

175

245

315

385

455

525

595

6650 70 140

210

280

350

420

490

560

630

(mV)



6500 Mb/s Line Rate

6500 Mb/s Line Rate







Data Rate (Mb/s)




and DIVPost

DividerOversample

6500 3250 325 1 2 * 5 = 10 1 1



RPT120_c2_70_061610








TJ

300

250

200

150

100

50

0

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_71_071410

0.03

0.06

0.09

0.12

0.15

0.18

0.21

0.24

0.27 0.3

0.33

0.36

0.39

0.42

0.45

0.48

0.51

0.54

0.570




TX Jitter Generation Measurement_6250_325_DJ 0.02 0.16 0.09 0.03 UI




JT20M_OPPM

350

300

250

200

150

100

50

0

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_72_071410

0.05 0.

1

0.15 0.

2

0.25 0.

3

0.35 0.4

0.45 0.

5

0.55 0.

6

0.65 0.

7

0.75 0.

8

0.85 0.

9

0.950



6500 Mb/s Line Rate



RX Sinusoidal Jitter Tolerance with ±200 PPM CDR Offset (SJ = 80 MHz)










JT80M_OPPM

300

250

200

150

100

50

0

(UI)

Num

ber

of D

ata

Poi

nts

RPT120_c2_73_071410

0.05 0.1

0.15 0.2

0.25 0.3

0.35 0.4

0.45 0.5

0.55 0.6

0.65 0.7

0.75 0.8

0.85 0.9

0.950




RX Sinusoidal Jitter Tolerance with ±2000 PPM CDR Offset (SJ = 80 MHz)






JT80_POS_200PPM

160

140

120

100

80

60

40

20

0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Num

ber

of D

ata

Poi

nts

RPT120_c2_74_071410(UI)

JT80_NEG200PPM

180

160

140

120

100

80

60

40

20

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.90

Num

ber

of D

ata

Poi

nts

RPT120_c2_75_071410(UI)

Table 2-74: RX Sinusoidal Jitter Tolerance with ±200 PPM CDR Offset (6500 Mb/s, 325 MHz)






6500 Mb/s Line Rate







JT80_POS_2000PPM

160

140

120

100

80

60

40

20

0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Num

ber

of D

ata

Poi

nts

RPT120_c2_76_071410(UI)

140

120

100

80

60

40

20

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.90

Num

ber

of D

ata

Poi

nts

RPT120_c2_77_071410

JT80_NEG_2000PPM

TJ (UI)

Table 2-75: RX Sinusoidal Jitter Tolerance with ±2000 PPM CDR Offset (6500 Mb/s, 325 MHz)












RXSEN

450

400

350

300

250

200

150

100

50

0

Num

ber

of D

ata

Poi

nts

RPT120_c2_78_071410

35 70 105

140

175

210

245

280

315

350

385

420

455

490

525

560

595

630

6650

(mV)



Chapter 3

Line Rate Independent Tests

The descriptions, setups, and methods for the tests in this chapter are described in Methodology for Line Rate Independent Tests, page 37.

This chapter contains the following sections:

• TX OOB Signal, page 112

• RX OOB Signal Detect, page 115

• Power Consumption, page 118

• Return Loss Measurements, page 121

• Termination (DC Resistance), page 123

• TX Buffer Bypass, page 125

• RX Buffer Bypass Margin, page 129

• TX Lane-to-Lane Skew, page 130

• TX Amplitude, page 131

• TX Output Rise Time, page 132

• TX Output Fall Time, page 133

• TX Pre-Emphasis, page 134

• TX Post-Emphasis, page 135

• RX Stressed Eye Tolerance, page 137

• RX Equalization, page 142

• RX CDR Bandwidth, page 142

• RX Jitter Tolerance vs. REFCLK Jitter, page 149



Chapter 3: Line Rate Independent Tests

TX OOB SignalThe test conditions for this section are described in TX OOB Signal, page 37.X-Ref Target - Figure 3-1

Figure 3-1: TX OOB (Squelch Amplitude, 1.5 Gb/s–5.0 Gb/s)

Table 3-1: TX OOB (Squelch Amplitude)


TXOOB Amplitude 4 7.63 5.47 0.99 mV


Figure 3-2: TX OOB Delay (2.5 Gb/s, 125 MHz)

Table 3-2: TX OOB Signal (2.5 Gb/s, 125 MHz)


TX_IDLE_DELAY = 0 36.51 39.9 37.56 1.09 ns

TX_IDLE_DELAY = 1 40.53 43.75 41.76 1.14 ns

TXSQUELCH_amp

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 300

5

10

15

20

25

30

35

40

RPT120_c3_01_071310TXAMP_Squelched (mV)

Num

ber

of D

ata

Poi

nts

MINMAXMEDIAN

0 1 2 3 4 5 6 70.00

10.00

20.00

30.00

40.00

50.00

60.00

70.00

80.00

TX

OO

B_d

elay

(ns

)

RPT120_c3_02_071310TX_IDLE_(DE)ASSERT_DELAY



TX OOB Signal

TX_IDLE_DELAY = 2 44.63 47.58 45.86 1.07 ns

TX_IDLE_DELAY = 3 48.54 51.93 49.6 1.16 ns

TX_IDLE_DELAY = 4 52.54 55.93 53.7 1.14 ns

TX_IDLE_DELAY = 5 56.13 60.67 57.61 1.34 ns

TX_IDLE_DELAY = 6 60.64 63.94 61.79 1.13 ns

TX_IDLE_DELAY = 7 64.37 67.93 65.65 1.24 ns


Figure 3-3: EIOS-to-Idle Delay (2.5 Gb/s, 125 MHz)


Figure 3-4: TX OOB Delay (5 Gb/s, 250 MHz)

Table 3-2: TX OOB Signal (2.5 Gb/s, 125 MHz)


MINMAXMEDIAN

0 1 2 3 4 5 6 70.00

5.00

10.00

15.00

20.00

25.00

EIO

S-t

o-ID

LE D

elay

(ns

)


MINMAXMEDIAN

0 1 2 3 4 5 6 70.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

45.00

TX

OO

B_d

elay

(ns

)





Table 3-3: TX OOB Signal (5 Gb/s, 250 MHz)


TX_IDLE_DELAY = 0 19.28 21.82 19.89 0.6 ns

TX_IDLE_DELAY = 1 21.18 23.82 21.98 0.69 ns

TX_IDLE_DELAY = 2 22.65 26.36 23.85 0.8 ns

TX_IDLE_DELAY = 3 25 27.64 26.07 0.63 ns

TX_IDLE_DELAY = 4 26.91 30.36 27.85 0.8 ns

TX_IDLE_DELAY = 5 29.36 32 30.26 0.69 ns

TX_IDLE_DELAY = 6 30.82 34.18 31.89 0.73 ns

TX_IDLE_DELAY = 7 33.27 36 34.02 0.7 ns


Figure 3-5: EIOS to Idle Delay (5 Gb/s, 250 MHz)

MINMAXMEDIAN

0 1 2 3 4 5 6 70.00

14.00

12.00

10.00

8.00

6.00

4.00

2.00

EIO

S-t

o-ID

LE D

elay

(ns

)





RX OOB Signal DetectThe test conditions for this section are described in RX OOB Signal Detect, page 37.X-Ref Target - Figure 3-6

Figure 3-6: RX OOB Signal Detect (2.5 Gb/s, 125 MHz)

Table 3-4: RX OOB Electrical Idle Detect (2.5 Gb/s, 125 MHz)


RX OOB Signal Detect = 0 10 105 64.71 19.68 mV








Virtex-6 FPGA GTX Transceiver 2G5 OOBElectrical Idle Threshold

0

20

40

60

80

100

120

0 50 100 150 200 250

RPT120_c3_06_073010

300 350 400

OOB (mV)

Num

ber

of D

ata

Poi

nts

2G5_OOB0

2G5_OOB1

2G5_OOB2

2G5_OOB3

2G5_OOB4

2G5_OOB5

2G5_OOB6

2G5_OOB7








Table 3-5: RX OOB Signal Detect (2.5 Gb/s, 125 MHz)




0

10

20

30

40

50

60

70

80

90

100

0 20 40 60

80

100

120

140

160

180

200

220

240

260

280

30

0

320

340

36

0

38

0

Num

ber

of D

ata

Poi

nts

OOB3_2G5

RPT120_c3_07_073010OOB (mV)

Virtex-6 FPGA GTX Transceiver 5G OOBElectrical Idle Threshold

0

10

20

30

40

50

60

70

80

90

100

0 50 100 150 200 250

RPT120_c3_08_073010

300 350 400

OOB (mV)

Num

ber

of D

ata

Poi

nts

5G_OOB0

5G_OOB1

5G_OOB2

5G_OOB3

5G_OOB4

5G_OOB5

5G_OOB6

5G_OOB7












Table 3-5: RX OOB Signal Detect (2.5 Gb/s, 125 MHz) (Cont’d)


0

10

20

30

40

50

60

70

80

90

100

0 20 40 60

80

100

120

140

160

180

200

220

240

260

280

30

0

320

340

36

0

38

0

Num

ber

of D

ata

Poi

nts

OOB3_5G

RPT120_c3_09_073010OOB (mV)




Power ConsumptionThe test conditions for this section are described in Power Consumption, page 39.


Figure 3-10: RX OOB Delay (2.5 Gb/s, 125 MHz)

Table 3-6: RX OOB Signal Detect (2.5 Gb/s, 125 MHz)


RXOOB Delay 12.41 21.5 16 2.07 ns

0 80757065605550454035302520151050

45

40

35

30

25

20

15

10

5

Num

ber

of D

ata

Poi

nts

RPT120_c3_10_071310RXOOB_delay (ns)

RX_OOB_delay


Figure 3-11: IAVCC Power Consumption

Table 3-7: IAVCC Power Consumption


IAVCC with PLL at 1.6 GHz 51.65 72.57 58.77 5.48 mA

IAVCC with PLL at 3.2 GHz 88.78 124.2 107.82 10.27 mA

1200

1700

2200

2700

3200

3700

0

20

40

60

80

100

120

140

160

180

200

IAV

CC

per

GT

X T

rans

ceiv

er (

mA

)

RPT120_c3_11_072910VCO_FREQUENCY (MHz)

AVCC



Power Consumption


Figure 3-12: IAVTT Power Consumption

Table 3-8: IAVTT Power Consumption


IAVTT with PLL at 1.6 GHz 51.5 59.94 55.87 2.79 mA

IAVTT with PLL at 3.2 GHz 51 63.2 57.26 3.32 mA


Figure 3-13: IAVTT vs. BUFDIFFCTRL Power Consumption

Table 3-9: IAVTT vs. BUFDIFF Power Consumption


IAVTT with BUFDIFF at 0 40.2 50.9 46.4 2.89 mA


1200

1700

2200

2700

3200

3700

0

10

20

30

40

50

60

70

80

90

100

IAV

TT

per

GT

X T

rans

ceiv

er (

mA

)

RPT120_c3_12_062810VCO_FREQUENCY (MHz)

AVTT

MINMAXMEDIAN

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0

10

20

30

40

50

60

70

80

90

100

IAV

TT

X_P

LL p

er G

TX

_DU

AL

(mA

)

RPT120_c3_13_062810TX_DIFF_CTRL [3:0]





IAVTT with BUFDIFF at 15 53.8 70 62.4 3.68 mA


Figure 3-14: IVCCINT Power Consumption

Table 3-10: AVCCINT Power Consumption


Dynamic AVCC_INT at 1.4 Gb/s 10.84 15.9 13.79 1.14 mA

Dynamic AVCC_INT at 6.4 Gb/s 50.08 72.28 63.58 5.11 mA

Table 3-9: IAVTT vs. BUFDIFF Power Consumption (Cont’d)


MINMAXMEDIAN

1400

2400

3400

4400

5400

6400

7400

0

10

20

30

40

50

60

70

80

90

100

PC

S (

VC

C_I

NT

) pe

r G

TX

(m

A)

RPT120_c3_14_062810Data Rate in Mb/s



Return Loss Measurements

Return Loss MeasurementsThe test conditions for this section are described in Return Loss Measurements, page 40.X-Ref Target - Figure 3-15

Figure 3-15: Return Loss Measurements (TX [SDD11] vs. Frequency)


Figure 3-16: Return Loss Measurements (RX [SDD11] vs. Frequency)

0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

0

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0

RPT120_c3_15_071310Frequency (GHz)

Pow

er (

dB)

TX_SDD11PCIe Gen2CPRI LV TXXAUICPRI HV RXCEI6GSFP+

0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

0

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0


Pow

er (

dB)

RX_SDD11PCIe Gen2CPRI LV RXXAUICPRI HV RXCEI6GSFP+





Figure 3-17: Return Loss Measurements (TX [SCC11] vs. Frequency)


Figure 3-18: Return Loss Measurements (RX [SCC11] vs. Frequency)

0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

0

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0


Pow

er (

dB)

TX_SCC11PCIe Gen2CPRICEI6GXAUI

0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

0

-30.0

-25.0

-20.0

-15.0

-10.0

-5.0


Pow

er (

dB)

RX_SCC11PCIe Gen2CPRICEI6GXAUI



Termination (DC Resistance)

Termination (DC Resistance)The test conditions for this section are described in Termination (DC Resistance), page 42.X-Ref Target - Figure 3-19

Figure 3-19: TX Differential Termination

Table 3-11: TX Differential Termination (DC Resistance)


TX Differential Termination 83.33 116.22 101.02 6.45 Ω


Figure 3-20: RX Differential Termination (GND)

Table 3-12: RX Differential Termination (DC Resistance)


RX Differential Termination (GND) 93.58 118.7 105.98 5.21 Ω

TX Rout

0

0 10 20 30 40 50 60 70 80 90 100

110

120

130

140

150

20

40

60

80

100

120

140

160

Num

ber

of D

ata

Poi

nts

RPT120_c3_19_071310TX - R out (Ω)

RXout_GNDterm

0

0 10 20 30 40 50 60 70 80 90 100

110

120

130

140

150

20

40

60

80

100

120

140

200

160

180

Num

ber

of D

ata

Poi

nts

RPT120_c3_20_071310RX - R out (Ω)





Figure 3-21: RX Differential Termination (VTT)



RX Differential Termination (VTT) 98.42 126 110.85 5.32 Ω


Figure 3-22: RX Differential Termination (Float)



RX Differential Termination (Float) 93.24 117.51 105.55 5 Ω

RXout_VTTterm

0

0 10 20 30 40 50 60 70 80 90 100

110

120

130

140

150

20

40

60

80

100

120

140

180

160

Num

ber

of D

ata

Poi

nts

RPT120_c3_21_071310RX - R out (Ω)

RXout_FLOATterm

0

0 10 20 30 40 50 60 70 80 90 100

110

120

130

140

150

20

40

60

80

100

120

140

200

180

160

Num

ber

of D

ata

Poi

nts

RPT120_c3_22_071310RX - R out (Ω)



TX Buffer Bypass

TX Buffer BypassThe test conditions for this section are described in TX Buffer Bypass Margin, page 43.

Figure 3-23 and Figure 3-24 show the minimum margin to TX low latency across TXUSCLK frequencies when the TXUSRCLK is advanced and delayed in 16-bit and 20-bit modes, respectively.

Figure 3-24 shows the TX buffer bypass initial phase margin in 16-bit mode with a 210 MHz USRCLK.


Figure 3-23: Minimum Reversible TX Low-Latency Initial Phase Margin (16-Bit Mode)


Figure 3-24: Minimum Reversible TX Low-Latency Initial Phase Margin (20-Bit Mode)

200

250

300

350

400

450

-5000

-4000

-3000

-2000

-1000

0

1000

2000

3000

4000

5000P

hase

Mar

gin

(ps)

RPT120_c3_23_071310TXUSRCLK - 16-Bit Mode (MHz)

DelayAdvanceCenter

200

220

260

240

300

280

320

340

-5000

-4000

-3000

-2000

-1000

0

1000

2000

3000

4000

5000

Pha

se M

argi

n (p

s)

RPT120_c3_24_071310TXUSRCLK - 20-Bit Mode (MHz)

DelayAdvanceCenter




In Table 3-15, the initial phase margin is not entirely reversible. The initial margin is roughly the duration of the delay aligner plus half of a USRCLK period. The reversible phase margin is the duration of the delay aligner plus one-fourth of a USRCLK period.


Figure 3-25: TX Buffer Bypass Initial Phase Margin, 210 MHz (16-Bit Mode)

Table 3-15: TX Buffer Bypass


TX Buffer Bypass Margin in 16-bit mode with USRCLK of 210 MHz (Advance)

–4166.67 –5442.18 –5442.18 307.75 ps

TX Buffer Bypass Margin in 16-bit mode with USRCLK of 210 MHz (Delay)

4039.12 5442.18 5442.18 311.27 ps




–4124.15 –5442.18 –5442.18 309.08 ps


3911.57 5442.18 5442.18 302.2 ps

0

-600

0

-540

0

-480

0

-420

0

-360

0

-300

0

-240

0

-180

0

-120

0

-600 0

600

1200

1800

2400

3000

3600

4200

4800

5400

6000

900

800

700

600

500

400

300

200

100

Num

ber

of D

ata

Poi

nts

RPT120_c3_25_071310USRCLK Phase Margin (ps)

210MHz_16bit_ADVANCE210MHz_16bit_DELAY

TEST LIMITS



TX Buffer Bypass

In Table 3-16 and Figure 3-26, the initial phase margin is not entirely reversible. The initial margin is roughly the duration of the delay aligner plus half of a USRCLK period. The reversible phase margin is the duration of the delay aligner plus one-fourth of a USRCLK period.






–3382.04 –3463.2 –3463.2 2.26 ps


3192.64 3463.2 3463.2 15.12 ps

0

-600

0

-540

0

-480

0

-420

0

-360

0

-300

0

-240

0

-180

0

-120

0

-600 0

600

1200

1800

2400

3000

3600

4200

4800

5400

6000

900

800

700

600

500

400

300

200

100

Num

ber

of D

ata

Poi

nts



TEST LIMITS










–3409.09x –3463.2 –3463.2 1.62 ps


2813.85 3463.2 3463.2 25.38 ps



0

-500

0

-460

0

-420

0

-380

0

-340

0

-300

0

-260

0

-220

0

-180

0

-140

0

-100

0

-600

-200 20

0

600

1000

1400

1800

2200

2600

3000

3400

3800

4200

4600

5000

1600

1400

1200

1000

800

600

400

200

Num

ber

of D

ata

Poi

nts



TEST LIMITS

0

-500

0

-460

0

-420

0

-380

0

-340

0

-300

0

-260

0

-220

0

-180

0

-140

0

-100

0

-600

-200 20

0

600

1000

1400

1800

2200

2600

3000

3400

3800

4200

4600

5000

1400

1200

1000

800

600

400

200

Num

ber

of D

ata

Poi

nts



TEST LIMITS



RX Buffer Bypass Margin


RX Buffer Bypass MarginThe test conditions for this section are described in RX Buffer Bypass Margin, page 45.

Figure 3-29 shows the minimum margin to RX low latency across RXUSRCLK frequencies when RXUSRCLK is advanced and delayed.

Figure 3-30 shows the minimum margin to RX low latency across RXUSRCLK frequencies when RXUSRCLK is advanced and delayed.


Figure 3-29: Minimum Reversible RX Low-Latency Initial Phase Margin (16-Bit Mode)


Figure 3-30: Minimum Reversible RX Low-Latency Initial Phase Margin (20-Bit Mode)

200

250

300

350

400

450

-2000

-1000

0

1000

2000

Pha

se M

argi

n (p

s)

RPT120_c3_29_071310RXUSRCLK - 16-Bit Mode (MHz)

DelayAdvanceCenter

200

220

240

260

280

300

320

340

-2000

-1000

0

1000

2000

Pha

se M

argi

n (p

s)

RPT120_c3_30_071310RXUSRCLK - 20-Bit Mode (MHz)

DelayAdvanceCenter




TX Lane-to-Lane SkewThe test conditions for this section are described in TX Lane-to-Lane Skew, page 46.

This characterization was performed on three quads of an XC6VLX240T device. The skew is the largest for the XC6VLX550T device.X-Ref Target - Figure 3-31

Figure 3-31: TX Lane-to-Lane Skew (FX240T)

Table 3-19: TX Lane-To-Lane Skew


TX Lane-to-Lane Skew –31 187 63 56.5 ps

-400

-360

-320

-280

-240

-200

-160

-120 -80

-40 0 40 80 120

160

200

240

280

320

360

400

(Data Rate: 2.5 Gbs, 6.5 Gbs; Temp: –40°C, 25°C, 100°C; Split: SS, TT, FF)

0

140

120

100

80

60

40

20

Num

ber

of D

ata

Poi

nts

RPT120_c3_31_071310Lane-to-Lane Skew (ps)



TX Amplitude

TX AmplitudeThe test conditions for this section are described in TX Amplitude, page 47.X-Ref Target - Figure 3-32

Figure 3-32: TX Amplitude (2500 Mb/s, 125 MHz)

Table 3-20: TX Amplitude (2500 Mb/s, 125 MHz)


TX Amplitude 0 90 140 110 10 mV









TX Amplitude 9 760 1000 880 60 mV

TX Amplitude 10 820 1070 940 60 mV

TX Amplitude 11 880 1120 990 60 mV

TX Amplitude 12 920 1160 1040 60 mV

TX Amplitude 13 970 1200 1080 60 mV

TX Amplitude 14 1000 1230 1110 60 mV

TX Amplitude 15 1030 1250 1130 60 mV

MINMEDIANMAX

0 151413121110987654321

(Data Rate: 2.5 Gb/s; Temp: –40°C, 25°C, 100°C; Splits: All)

0

1400

1200

1000

800

600

400

200

Vdi

ff_am

p (m

V P

eak-

to-P

eak)

RPT120_c3_32_071310TX Amplitude Setting




TX Output Rise TimeX-Ref Target - Figure 3-33

Figure 3-33: TX Output Rise Time

Table 3-21: TX Output Rise Time (2500 Mb/s, 125 MHz)


TX Output Rise Time (ampl 0) 112 133.7 126.7 4.4 ps

TX Output Rise Time (ampl 1) 117.6 136.7 125.8 3.7 ps





TX Output Rise Time (ampl 6) 115.8 135.9 124 3.9 ps






TX Output Rise Time (ampl 12) 116.8 133 124.2 4 ps



TX Output Rise Time (ampl 15) 115.1 131.3 124.7 4 ps

MINMEDIANMAX

0 151413121110987654321

(Data Rate: 2.5 Gb/s; Temp: –40°C, 25°C, 100°C; Splits: All) on a 4.5” Channel

70

150

140

130

120

110

100

90

80

TX

rise_

20%

–80%

(ps

)

RPT120_c3_33_071410TX Output Rise Time



TX Output Fall Time

TX Output Fall TimeX-Ref Target - Figure 3-34

Figure 3-34: TX Output Fall Time

Table 3-22: TX Output Fall Time (2500 Mb/s, 125 MHz)


TX Output Fall Time FT_0 99.2 123.2 108.3 5 ps

TX Output Fall Time FT_1 106.2 124.3 113 3.7 ps


TX Output Fall Time FT_3 109.5 129.2 118.8 4.3 ps



TX Output Fall Time FT_6 114 135.6 125.2 4.5 ps



TX Output Fall Time FT_9 120.4 141 130.8 4.7 ps


TX Output Fall Time FT_11 122.3 141 132.2 4.2 ps





MINMEDIANMAX

(Data Rate: 2.5 Gb/s; Temp: –40°C, 25°C, 100°C; Splits: All) on a 4.5” Channel

70

150

140

130

120

110

100

90

80

TX

all_

80%

–20%

(ps

)

RPT120_c3_34_071410TX Output Fall TIme

0 151413121110987654321




TX Pre-EmphasisThe test conditions for this section are described in TX Emphasis, page 48.X-Ref Target - Figure 3-35

Figure 3-35: TX Pre-Emphasis (2500 Mb/s, 125 MHz)

Table 3-23: TX Pre-Emphasis (2500 Mb/s, 125 MHz)


TXPREEMPH_000 –0.19 –0.12 –0.15 0.02 dB

TXPREEMPH_001 –0.32 –0.27 –0.3 0.01 dB

TXPREEMPH_002 –0.48 –0.42 –0.45 0.02 dB

TXPREEMPH_003 –0.65 –0.57 –0.61 0.02 dB

TXPREEMPH_004 –0.79 –0.7 –0.74 0.02 dB

TXPREEMPH_005 –0.94 –0.85 –0.91 0.02 dB

TXPREEMPH_006 –1.12 –1.03 –1.07 0.02 dB

TXPREEMPH_007 –1.31 –1.2 –1.25 0.02 dB

TXPREEMPH_008 –1.4 –1.32 –1.36 0.02 dB

TXPREEMPH_009 –1.59 –1.5 –1.55 0.02 dB

TXPREEMPH_010 –1.81 –1.68 –1.74 0.02 dB

TXPREEMPH_011 –2 –1.87 –1.94 0.03 dB

TXPREEMPH_012 –2.18 –2.05 –2.11 0.03 dB

TXPREEMPH_013 –2.39 –2.25 –2.32 0.03 dB

TXPREEMPH_014 –2.63 –2.47 –2.54 0.03 dB

TXPREEMPH_015 –2.84 –2.7 –2.77 0.04 dB

MinMedianMax

0

-0.5

-1

-1.5

-2

-2.5

-3

-3.5

-4

-4.5

-51 2 3 4 5 6 7 8 9 10 11 12 13 14 150

TXPREEMPHASIS

20LO

G(V

min

/Vm

ax)

(dB

)

RPT120_c3_35_071510

(Data Rate: 2.5 Gb/s; Vol: ±5% Nom.; Temp: –40°C, 25°C, 100°C; Splits: SS, TT, FF, FS, SF)



TX Post-Emphasis

TX Post-EmphasisX-Ref Target - Figure 3-36

Figure 3-36: TX Post-Emphasis (2500 Mb/s, 125 MHz)

Table 3-24: TX Post-Emphasis (2500 Mb/s, 125 MHz)


TXPOSTEMPH_000 –0.59 –0.12 –0.18 0.11 dB

TXPOSTEMPH_001 –0.67 –0.12 –0.19 0.12 dB

TXPOSTEMPH_002 –0.57 –0.12 –0.18 0.11 dB

TXPOSTEMPH_003 –0.64 –0.12 –0.18 0.12 dB

TXPOSTEMPH_004 –0.63 –0.11 –0.18 0.11 dB

TXPOSTEMPH_005 –0.62 –0.1 –0.18 0.12 dB

TXPOSTEMPH_006 –0.69 –0.11 –0.18 0.12 dB

TXPOSTEMPH_007 –0.63 –0.11 –0.18 0.12 dB

TXPOSTEMPH_008 –0.68 –0.11 –0.19 0.12 dB

TXPOSTEMPH_009 –0.68 –0.12 –0.2 0.13 dB

TXPOSTEMPH_010 –0.96 –0.23 –0.39 0.14 dB

TXPOSTEMPH_011 –1.23 –0.43 –0.63 0.13 dB

TXPOSTEMPH_012 –1.32 –0.64 –0.82 0.13 dB

TXPOSTEMPH_013 –1.66 –0.88 –1.07 0.14 dB

TXPOSTEMPH_014 –1.93 –1.12 –1.32 0.16 dB

TXPOSTEMPH_015 –2.46 –1.38 –1.6 0.19 dB

TXPOSTEMPH_016 –2.08 –1.49 –1.65 0.12 dB

TXPOSTEMPH_017 –2.41 –1.77 –1.94 0.13 dB

MinMedianMax

2

0

-2

-4

-6

-8

-10162 184 206 228 2410 2612 2814 300

TXPOSTEMPHASIS

20LO

G(V

min

/Vm

ax)

(dB

)

RPT120_c3_36_071510

(Data Rate: 2.5 Gb/s; Vol: ±5% Nom.; Temp: –40°C, 25°C, 100°C; Splits: SS, TT, FF, FS, SF)




TXPOSTEMPH_018 –2.79 –1.79 –2.21 0.15 dB

TXPOSTEMPH_019 –3.16 –2.04 –2.52 0.17 dB

TXPOSTEMPH_020 –3.37 –2.28 –2.76 0.16 dB

TXPOSTEMPH_021 –3.79 –2.36 –3.08 0.19 dB

TXPOSTEMPH_022 –4.2 –2.49 –3.41 0.21 dB

TXPOSTEMPH_023 –4.62 –2.69 –3.77 0.23 dB

TXPOSTEMPH_024 –4.61 –2.91 –3.97 0.2 dB

TXPOSTEMPH_025 –5.11 –3.27 –4.36 0.22 dB

TXPOSTEMPH_026 –5.49 –3.54 –4.73 0.24 dB

TXPOSTEMPH_027 –6.17 –3.83 –5.16 0.28 dB

TXPOSTEMPH_028 –6.25 –3.24 –5.47 0.33 dB

TXPOSTEMPH_029 –6.81 –4.36 –5.93 0.28 dB

TXPOSTEMPH_030 –7.38 –4.62 –6.38 0.31 dB

TXPOSTEMPH_031 –8 –5.09 –6.89 0.34 dB

Table 3-24: TX Post-Emphasis (2500 Mb/s, 125 MHz) (Cont’d)





RX Stressed Eye ToleranceThe test conditions for this section are described in RX Stressed Eye Tolerance, page 49. Figure 3-37 shows the BU jitter tolerance vs. equalizer across 16 inches plus 4 inches of FR4 channels at 6.5 Gb/s. A 16-inch FR4 channel has roughly 14 db of loss at 3.25 GHz.

Figure 3-38 shows the BU jitter tolerance vs. equalizer across 20 + 4 inches of FR4 channels at 6.5 Gb/s. A 20-inch FR4 channel has roughly 15 db of loss at 3.25 GHz.


Figure 3-37: BU Jitter Tolerance vs. Equalizer Across 16 + 4 FR4 Channels at 6.5 Gb/s



0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31

auto

6.5 Gb/s - 16” FR4 - RX Jitter Tolerance -AC_CAP_DIS:0 RCV_TERM_VTTRX:0

0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

BU

- J

itter

Tol

eran

ce

RPT120_c3_37_061410DFE TAP1 Setting

PRBS31 RXEQ:6PRBS31 RXEQ:0PRBS31 RXEQ:2PRBS7 RXEQ:6PRBS7 RXEQ:0PRBS7 RXEQ:2

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31

auto


0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

BU

- J

itter

Tol

eran

ce


PRBS31 RXEQ:6PRBS31 RXEQ:0PRBS31 RXEQ:2PRBS7 RXEQ:6PRBS7 RXEQ:0PRBS7 RXEQ:2










0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31

auto


0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

BU

- J

itter

Tol

eran

ce


PRBS31 RXEQ:6PRBS31 RXEQ:0PRBS31 RXEQ:2


0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31

auto


0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

BU

- J

itter

Tol

eran

ce







In Figure 3-43 and Figure 3-44, the difference between the PRBS31 and PRBS7 patterns disappears when the internal AC capacitor is bypassed.


Figure 3-41: BU Jitter Tolerance vs. DFE with RXEQ = 2 and 16 Inches FR4 at 6.5 Gb/s



DA

TA

FE

TA

P1

PR

BS

7P

RB

S31

0.1

U.I.

0.2

U.I.

0.3

U.I.

0.4

U.I.

0.5

U.I.

0.6

U.I.

135791113151719212325272931

RPT120_c3_41_070110

135791113151719212325272931

DA

TA

FE

TA

P1

PR

BS

7P

RB

S31

0.1

U.I.

0.2

U.I.

0.3

U.I.

0.4

U.I.

0.5

U.I.

0.6

U.I.

135791113151719212325272931

RPT120_c3_42_070110

135791113151719212325272931





Figure 3-43: BU Jitter Tolerance vs. DFE with RXEQ = 2 and 16 Inches FR4 at 6.5 Gb/s (DC Coupled)


Figure 3-44: BU Jitter Tolerance vs. DFE with RXEQ = 2 and 20 Inches FR4 at 6.5 Gb/s (DC Coupled)

DAT

A

FE

TA

P1

PR

BS

7P

RB

S31

0.1

U.I.

0.2

U.I.

0.3

U.I.

0.4

U.I.

0.5

U.I.

0.6

U.I.

13579

1113151719212325272931

RPT120_c3_43_061410

13579

1113151719212325272931

DAT

A

FE

TA

P1

PR

BS

7P

RB

S31

0.1

U.I.

0.2

U.I.

0.3

U.I.

0.4

U.I.

0.5

U.I.

0.6

U.I.

13579

1113151719212325272931

RPT120_c3_44_061410

13579

1113151719212325272931








DA

TA

DF

E T

AP

1

PR

BS

7P

RB

S31

0.1

U.I.

0.2

U.I.

0.3

U.I.

0.4

U.I.

0.5

U.I.

0.6

U.I.

135791113151719212325272931

RPT120_c3_45_061010

135791113151719212325272931

DA

TA

DF

E T

AP

1

PR

BS

7P

RB

S31

0.1

U.I.

0.2

U.I.

0.3

U.I.

0.4

U.I.

0.5

U.I.

0.6

U.I.

135791113151719212325272931

RPT120_c3_46_061010

135791113151719212325272931




RX EqualizationThe test conditions for this section are described in RX Equalization, page 50.

The FR4 length used in Figure 3-47 is the last passing J-BERT channel (the instrument limit is 44 inches).

RX CDR BandwidthThe test conditions for this section are described in RX CDR Bandwidth, page 51.

4.25 Gb/s CDR tests are run with RXEQ = 0 and DFE_TAP1 = 16. The data is PRBS31 data across a 36-inch FR4 channel with an additional 0.05 UI of RJ on the data. Figure 3-48 through Figure 3-51 show the jitter tolerance sweep by step size and by PPM.


Figure 3-47: RX Equalization vs. Passing DFE Taps

20”+

8”A

C_M

ID

32”+

8”A

C_M

ID

44”+

8”A

C_M

ID

20”+

8”A

C_V

TT

32”+

8”A

C_V

TT

44”+

8”A

C_V

TT

20”+

8”D

C_M

ID

32”+

8”D

C_M

ID

44”+

8”D

C_M

ID

20”+

8”D

C_V

TT

32”+

8”D

C_V

TT

44”+

8”D

C_V

TT

0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

Num

ber

of P

assi

ng D

FE

TA

P1

Set

tings

(Max

= 3

2)

RPT120_c3_47_071310FR4 Channel Length / RX Termination

RXEQ = 0RXEQ = 2RXEQ = 4RXEQ = 6


Figure 3-48: Jitter Tolerance Sweep by Step Size (4.25 Gb/s, CDR: 1st = N, 2nd = Off)

0.1

1.0

10.0

100.0

Tole

ranc

e (U

I)

RPT120_c3_48_071310SJ Frequency

104 106 107 108105

CDR Tracking Corner

23 KHz SJ Tolerance

0 PPM / N = 10 PPM / N = 20 PPM / N = 4



RX CDR Bandwidth


Figure 3-49: Jitter Tolerance Sweep by PPM (4.25 Gb/s, CDR: 1st = N, 2nd = Off)

Table 3-25: First-Order CDR Corner Frequency (MHz) by Step Size

1 2 3 4

–200 PPM 0.49 1.75 3.20 4.43

–100 PPM 0.80 2.29 3.72 5.45

0 PPM 1.06 2.24 3.36 5.04

+100 PPM 0.74 2.08 3.65 4.81

+200 PPM 0.44 1.71 2.96 4.38

Table 3-26: First-Order JT UI at 23 KHz by Step Size

1 2 3 4

–200 PPM 11.60 33.78 56.65 78.58

–100 PPM 17.49 40.30 62.47 85.07

0 PPM 23.45 46.11 68.49 89.86

+100 PPM 17.77 40.38 62.55 84.31

+200 PPM 11.73 34.20 56.60 79.71

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


–200 N = 1–200 N = 2–200 N = 4–100 N = 1–100 N = 2–100 N = 40 N = 10 N = 20 N = 4100 N = 1100 N = 2100 N = 4200 N = 1200 N = 2200 N = 4

104 106 107 108105




5 Gb/s CDR tests are run with RXEQ = 0 and DFE_TAP1 = 16. The data is PRBS31 data across a 36-inch FR4 channel with an additional 0.05 UI of RJ on the data. Figure 3-52 through Figure 3-55 show the jitter tolerance sweep by step size and by PPM.


Figure 3-50: Jitter Tolerance Sweep by Step Size (4.25 Gb/s, CDR: 1st = N, 2nd = M)


Figure 3-51: Jitter Tolerance Sweep by PPM (4.25 Gb/s, CDR: 1st = N, 2nd = 1)

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


N = 1 / M = 0N = 2 / M = 0N = 3 / M = 0N = 4 / M = 1N = 1 / M = 1N = 1 / M = 2N = 2 / M = 1N = 2 / M = 2

104 106 107 108105

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


–2000–1000–100010010002000

104 105 106 107 108



RX CDR Bandwidth


Figure 3-52: Jitter Tolerance Sweep by Step Size (5 Gb/s, CDR: 1st = N, 2nd = Off)


Figure 3-53: Jitter Tolerance Sweep by PPM (5 Gb/s, CDR: 1st = N, 2nd = Off)


1 2 3 4

–200 PPM 0.60 1.86 4.02 5.55

–100 PPM 0.96 2.52 3.37 5.83

0 PPM 1.44 2.96 5.27 6.32

+100 PPM 0.86 2.53 3.52 5.71

+200 PPM 0.66 3.36 3.84 4.60

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


104 105 106 107 108

CDR tracking corner

23 KHz SJ tolerance

0 PPM / N = 10 PPM / N = 20 PPM / N = 4

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)



104 105 106 107 108




5.00 Gb/s CDR tests are run with RXEQ = 00 and DFE_TAP1 = 16. The data is PRBS31 data across a 28-inch FR4 channel with an additional 0.05 UI of RJ on the data. Figure 3-56 through Figure 3-57 show the jitter tolerance sweep by step size and by PPM.

Table 3-28: First-Order JT (UI) at 23 KHz by Step Size

1 2 3 4

–200 PPM 13.29 40.19 64.20 90.87

–100 PPM 20.41 47.06 71.02 97.44

0 PPM 27.28 53.39 79.65 105.0

+100 PPM 20.66 47.29 71.27 97.30

+200 PPM 13.42 39.72 66.10 90.72


Figure 3-54: Jitter Tolerance Sweep by Step Size (5 Gb/s, CDR: 1st = N, 2nd = M)


Figure 3-55: Jitter Tolerance Sweep by PPM (5 Gb/s, CDR: 1st = 1, 2nd = 1)

104

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)



105 106 107 108

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


–2000–1000–100010010002000

104 105 106 107 108



RX CDR Bandwidth


Figure 3-56: Jitter Tolerance Sweep by Step Size (5.00 Gb/s, CDR: 1st = N, 2nd = Off)


Figure 3-57: Jitter Tolerance Sweep by PPM (5.00 Gb/s, CDR: 1st = N, 2nd = Off)


1 2 3 4

–200 PPM 0.90 2.94 4.42 2.62

–100 PPM 1.21 3.33 5.21 6.09

0 PPM 1.77 3.63 4.23 3.88

+100 PPM 1.10 2.53 4.55 6.25

+200 PPM 1.06 2.43 5.45 5.00

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


104 105 106 107 108

CDR Tracking Corner

23 KHz SJ Tolerance

0 PPM / N = 10 PPM / N = 20 PPM / N = 4

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)



104 105 106 107 108




The 6p5G CDR data with second-order loop ON is presented across only 4 inches of FR4 (Figure 3-58 and Figure 3-59).

Table 3-30: First-Order JT (UI) at 23 KHz by Step Size

1 2 3 4

–200 PPM 16.56 50.31 81.48 105.12

–100 PPM 25.63 58.19 87.92 106.10

0 PPM 34.03 65.37 87.08 109.7

+100 PPM 24.80 40.58 83.45 108.02

+200 PPM 15.62 46.70 81.17 102.45


Figure 3-58: Jitter Tolerance Sweep by Step Size (6 Gb/s, CDR: 1st = N, 2nd = M)


Figure 3-59: Jitter Tolerance Sweep by PPM (6 Gb/s, CDR: 1st = 2, 2nd = 1)


100.0

10.0

1.0

0.1

SJ Frequency

Tole

ranc

e (U

I)

RPT120_c3_58_070110

104 105 106 107 108

-2000

0

2000

100.0

10.0

1.0

0.1

SJ Frequency

Tole

ranc

e (U

I)

RPT120_c3_59_070110

104 105 106 107 108



RX Jitter Tolerance vs. REFCLK Jitter

RX Jitter Tolerance vs. REFCLK JitterFigure 3-60 shows the RX jitter tolerance when the REFCLK jitter is 0.10 UI. The largest effects are seen when the REFCLK jitter is inside the PLL bandwidth, but outside of the CDR tracking bandwidth.

Figure 3-61 shows the RX jitter tolerance when the REFCLK jitter is 0.45 UI. The largest effects are seen when the REFCLK jitter is inside the PLL bandwidth, but outside of the CDR tracking bandwidth.

Figure 3-62 shows the RX jitter tolerance when the REFCLK jitter is 100 KHz. Because the 100 KHz REFCLK jitter is inside the PLL bandwidth, it passes onto the PLL and into the receiver. Because 100 KHz is within the CDR bandwidth of the receiver, little adverse effect is measured.


Figure 3-60: Jitter Tolerance (6.5 Gb/s, REFCLK Jitter = 0.10 UI)


Figure 3-61: Jitter Tolerance (6.5 Gb/s, REFCLK Jitter = 0.45 UI)

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


SJ Freq: 10 KHzSJ Freq: 100 KHzSJ Freq: 1 MHzSJ Freq: 2 MHzSJ Freq: 10 MHzSJ Freq: 80 MHzSJ Freq: 100 MHz

104 105 106 107 108 109

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


SJ Freq: 10 KHzSJ Freq: 100 KHzSJ Freq: 1 MHzSJ Freq: 2 MHzSJ Freq: 10 MHzSJ Freq: 80 MHzSJ Freq: 100 MHz

104 105 106 107 108 109




Figure 3-63 shows the RX jitter tolerance when the REFCLK jitter is 10 MHz. Because the 10 MHz REFCLK jitter is inside the PLL bandwidth, it passes onto the PLL and into the receiver. Because 10 MHz is outside the CDR bandwidth of the receiver, large adverse effects are measured.

Figure 3-64 shows the RX jitter tolerance when the REFCLK jitter is 100 MHz. Because the 100 MHz REFCLK jitter is outside the PLL bandwidth, only a portion passes onto the PLL and into the receiver. Because 100 MHz is outside the CDR bandwidth of the receiver, medium adverse effects are measured.


Figure 3-62: Jitter Tolerance (6.5 Gb/s, REFCLK Jitter = 100 KHz)


Figure 3-63: Jitter Tolerance (6.5 Gb/s, REFCLK Jitter = 10 MHz)

100KHz_0.05 UI100KHz_0.10 UI100KHz_0.20 UI100KHz_0.45 UI

0

1.0

10.0

100.0

Tol

eran

ce (

UI)


104 105 106 107 108 109

10MHz_0.05 UI10MHz_0.10 UI10MHz_0.20 UI10MHz_0.45 UI

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


104 105 106 107 108 109



RX Jitter Tolerance vs. REFCLK Jitter

I

Figure 3-65 shows the RX jitter tolerance performance loss when the REFCLK jitter is RJ rms. Performance loss in jitter tolerance is dominated by an increase in RJ greater than the CDR bandwidth, but below the PLL bandwidth onto REFCLK.

Figure 3-66 shows the RX jitter tolerance when the REFCLK jitter is RJ rms. Performance loss in jitter tolerance is dominated by an increase in RJ greater than the CDR bandwidth, but below the PLL bandwidth onto REFCLK.


Figure 3-64: Jitter Tolerance (REFCLK Jitter = 100 MHz)


Figure 3-65: Jitter Tolerance Performance Loss (REFCLK Jitter = RJ rms)

100MHz_0.05 UI100MHz_0.10 UI100MHz_0.20 UI100MHz_0.45 UI

0.1

1.0

10.0

100.0

Tol

eran

ce (

UI)


104 105 106 107 108 109

180

160

140

120

100

80

60

40

20

00 20 40 60 80 100 120

Loss in RX JT at SJ > 10 MHz (ps)

RJ

> 1

0 M

Hz

Inje

cted

Jitt

eron

to R

efC

lk (

ps)

RPT120_c3_65_070110

median_6p5

median_4p25

median_6p25

median_5p0

median_3p2





Figure 3-66: Jitter Tolerance (REFCLK Jitter = RJ rms)

0.1

1.0

10.0

100.0

Tole

ranc

e (U

I)

0.00 _UI_RJ0.18 _UI_RJ0.42 _UI_RJ0.66 _UI_RJ

RPT120_c3_66_070110

104 105 106 107 108 109

SJ Frequency


Virtex-6 FPGA GTX Transceiver - Xilinx · 2020. 9. 5. · Virtex-6 FPGA GTX Transceiver Report 7 RPT120 (v1.0) July 30, 2010 Chapter 1 Transceiver Characterization Methodology Test

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