Vectored Interrupt Controller 2009-10 CHAPTER 1 INTRODUCTION An AMBA based microcontroller typically consists of a high performance system backbone bus, able to sustain the external memory bandwidth, on which the CPU on-chip memory and other direct memory access [DMA] devices reside. This bus provides a high bandwidth interface between the elements that are involved in the majority of transfers also located on the high performance bus is a bridge to the lower bandwidth APB, where most of the peripheral devices in the system are located vectored interrupt controller is one of the high performance system bus slave. The figure 1.1 shows an example of AMBA based system. DEPT OF E&C, SJCIT 1 UART High- bandwidt h RAM ARM Process or PIO B R I D G High- performanc e Memory interface Vectore d interru pt Control ler DMA Control ler Keypad TIMER
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Vectored Interrupt Controller 2009-10
CHAPTER 1
INTRODUCTION
An AMBA based microcontroller typically consists of a high performance system
backbone bus, able to sustain the external memory bandwidth, on which the CPU on-chip
memory and other direct memory access [DMA] devices reside. This bus provides a high
bandwidth interface between the elements that are involved in the majority of transfers also
located on the high performance bus is a bridge to the lower bandwidth APB, where most of
the peripheral devices in the system are located vectored interrupt controller is one of the
high performance system bus slave. The figure 1.1 shows an example of AMBA based
system.
Figure 1.1:A typical AMBA system
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UART
High-bandwidth
RAM
ARM Processor
PIO
B
R
I
D
G
High-performance
Memory interface
Vectored interrupt Controller
DMA Controller
KeypadTIMER
Vectored Interrupt Controller 2009-10
The AHB slave main function is an interface unit that allows AHB. Logic to initiate a data
transfer on the AHB. The AHB specifies the type transaction to be executed on the slave through a
user friendly interface. AHB is optimized to interface with VIC to initiate data transfer on the AHB.
Once the VIC received the request from AHB bus, executes the transaction on the AHB with
the AHB protocol.VIC AHB slave interface will handle only one response state interrupts.
At this point we propose a vectored interrupt controller with which having the following
specifications
Uses the AMBA AHB protocol.
Up to 32 interrupt source.
High level sensitive, interrupt source type.
Support for 32 vectored interrupts.
Fixed interrupt priority level.
Fixed IRQ and FIQ generation.
Software interrupts generation.
Interrupt enable.
Raw interrupt status.
Interrupt source get acknowledgment.
Memory space offset address start with 00.
VIC can provide an interrupt controller peripheral for AMBA based SOCs.VIC captures interrupt
requests from 32 interrupt inputs. Each interrupt input independently configures for level sensitive,
interrupt request and for active high interrupt requests. VIC supports for fixed priority scheduling
method to handle the interrupt requests. VIC support for 4 FIQ and 28 IRQ requests. VIC
acknowledges the interrupt requests.
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CHAPTER 2
BLOCK DIAGRAM OF VECTORED INTERRUPT CONTROLLER (VIC)
The vectored interrupt controller is mainly divided in to three blocks namely
1. Peripheral interface
2. CPU interface
3. AHB slave interface
The Block diagram of vectored interrupt controller is shown in figure 2.1
Figure 2.1:Block Diagram of Vectored Interrupt Controller
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2.1 Peripheral Interface
The Peripheral interface is composed of only one functional unit called Interrupt request logic
2.1.1 Interrupt Request Logic
The interrupt request logic receives the interrupt requests from the peripheral and
combines them with the software interrupt requests. It then makes out the interrupt requests
that are not enabled and steering logic is used to split the interrupt request into fast interrupt
request and general interrupt request two separate acknowledgements are send back for fast
interrupt request.
2.2 CPU Interface
The CPU interface consists of two sub blocks namely FIQ request handling and IRQ
request handling.
2.2.1 FIQ request handling
Here we use fixed priority logic for lower 4 bits of Intr_src and generates the nfiq
signals which is active low and selects the vector address of the respective peripheral from
vectored table to the CPU.
2.2.2 IRQ request handling
Here it was fixed priority logic for upper 28 bits of Intr_src and generates the nirq
signal which is active low and selects the vector address of the respective peripheral from
vectored table to the CPU.
2.3 AHB Slave
An AHB bus slave responds to transfers initiated by bus masters within the system.
The slave uses a HSEL select signal from the decoder to determine when it should respond to
a bus transfer. All other signals required for the transfer, such as the address and control
information, will be generated by the bus master.
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2.4 Peripheral Interface
2.4.1 Interrupt Request Logic
Figure 2.2: Interrupt request logic
The interrupt request logic receiver the interrupt request from the peripheral and combines
them with the software interrupt requests to either IRQ status or FIQ status
Soft_Int [Software Interrupt Register ]:
The read and write software register, with address offset 0x080, generates
software interrupt. Soft INT is 32 bits register, setting a bit generation a software
interrupt masking. A high bit sets the corresponding bit in the VICSOFTINT register
a low bit has no effect
Enable_ Int[Interrupt Enable Register]:
The read write interrupt enable register, with address effect of 0x084, enable
the interrupt request id masking lines by masking the interrupt sources for the IRQ
interrupt
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Interrupt enable register is a 32 bits register which enable the interrupt request lines
setting a bit interrupt enabled, Enable interrupt request to processor setting a bit 0
interrupts are disabled, on reset all interrupts are disabled A high bit sets the
corresponding bits in interrupt enable register, a low bit has no effect.
Int_Status [Interrupt Status Register]:
It has an address offset of 0x088, provides the status of the source interrupt,
and software interrupt to the interrupt controller.
Int _Status is 32 bit register, shows the status of the interrupts before masking by the
enable registers .A high bit indicates that the appropriate interrupt request is active
before masking.
Interrupt request logic receives 32 Intr_src lines from CPU peripherals and
combines with the software interrupt which are written by CPU on Soft_Int register and
enable the user selected interrupts by gated enabling and separate the 32 request lines into 4
fast interrupt request and 28 general interrupt request and also encode the filtered output
generates two separate request id for FIQ’s and IRQ’s.
2.5 CPU Interface
2.5.1 FIQ request handling
The FIQ request handling shown in figure 2.3 asserts the nfiq signal. i.e. if FIQ_status
is nonzero, set the nfiq as low. It selects the vectored address of the corresponding fast
interrupt request. Send it to CPU through AHB slave interface. It will select the vectored
address from the vectored address table, vectored address table is the memory configuration
space, which contain the subroutine of the each interrupt request. The vectored addresses in
the vectored table are programmable. FIQ_status acts as a select line for vectored address
selection. nfiq is active low signal for CPU.
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Figure 2.3:FIQ request handling
2.5.2 IRQ Request Handling
The IRQ request handling shown in figure 2.4 Asserts the nirq signal. i.e., if
irq_status is nonzero, set the nfiq as low and selects the vectored address of the
corresponding interrupt request. Send it to CPU through AHB slave interface. It will select
the vectored address from the vectored address table, vectored address table is the memory
configuration space, which contain the subroutine of the each interrupt request. The vectored
addresses in the vectored table are programmable. IRQ_status acts as a select line for
vectored address selection. nirq is active low signal for CPU.
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Figure 2.4:IRQ request handling
2.6 AHB Slave Interface
The AHB slave shown in figure 2.5 maps the memory configaration space with the interrupt
controller and perform the data transaction as AHB asserts its signal. In this block asserts
Hready_out as high and Hresp as OKAY, because we designed Interrupt controller as a
single slave.
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Figure 2.5 AHB slave interface
2.7 Signal Details
2.7.1 AHB Slave Signals
Name Type Source Description
HCLK Input Clock source This clock times all bus transfers. All
signal timings are related to the rising
edge of HCLK.
HRESET Input Reset controller The bus reset signal is active HIGH
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and is used to reset the system and
the bus.
HSEL Input Decoder Each AHB slave has its own slave
select signal and this signal indicates
that the current transfer is intended
for the selected slave. This signal is
simply a combinatorial decode of the
address bus.
HTRANS[1:0] Input Master Indicates the type of the current
transfer, which can be
NONSEQUENTIAL,
SEQUENTIAL, IDLE or BUSY.
HREADY_IN Input External slave Transfer done signal, generated by an
alternate slave. When HIGH,
indicates that a transfer is complete.
Can be driven LOW to extend a
transfer.
HWRITE Input Master When HIGH this signal indicates a
write transfer and when LOW a read
transfer.
HADDR[11:2] Input Master Systems address bus.
HREADY_OUT Output Slave Transfer done signal, generated by
the VIC. When HIGH, indicates that
a transfer is complete. Can be driven
LOW to extend a transfer.
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HRESP[1:0] Output Slave Transfer done signal, generated by
the VIC. When HIGH, indicates that
a transfer is complete. Can be driven
LOW to extend a transfer.
HRDATA[31:0] Output Slave Read data bus, used to transfer data
from bus slaves to bus master during
read operations
Table 2.1: AHB Slave Signals
2.7.2 Peripheral Interface Signals
Name Type Source DescriptionINTR_SRC
(31 interrupt lines)Input Peripheral This is a one bit signal from each
peripheral. The signal is active
HIGH which indicates there is a
interrupt from respective peripheral.
RQST_ID_F [4:0] Output Interrupt Controller
Address bus, returns the address to
FIQ peripherals at the time of
acknowledgment.
RQST_ID_I [4:0] Output Interrupt Controller
Address bus, returns the address to
IRQ peripherals at the time of
acknowledgment.
ACK_F Output Interrupt Controller
When HIGH, Indicates the FIQ
interrupt acknowledgment to
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peripherals.
ACK_I Output Interrupt Controller
When HIGH,indicates the IRQ
interrupt acknowledgment to
peripherals.
FIQ_status [4:0] Output Peripheral Interface
Indicates the FIQ signals status
IRQ_status [28:0] Output Peripheral Interface
Indicates the IRQ signals status
Table 2.2 :Peripheral Interface Signals
2.4.3 CPU Interface Signals
Name Type Source DescriptionFIQ_status [4:0] Input Peripheral
InterfaceIndicates the IRQ signals status
IRQ_status [28:0] Input Peripheral Interface
Indicates the IRQ signals status
NFIQ Output Interrupt Controller
FIQ request to processor
NIRQ Output Interrupt Controller
IRQ request to processor
VECT_ADDR[31:0] Output Interrupt Controller
Address bus ,contains vector
address of interrupt to processor
Table 2.3:CPU Interface Signals
CHAPTER 3
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AMBA SPECIFICATION
On-chip communication standard for designing high performance embedded
microcontroller.
Three distinct buses are defined within the AMBA specifications
The advanced high performance bus [AHB]
The advanced system bus [ASB]
The advanced peripheral bus [APB]
A test methodology is included with the AMBA specification which provides an
infrastructure for modular macro cell test and diagnostic access.
The AMBA specification has been derived to satisfy the requirements such as
To facilitate the right first home developments of embedded microcontroller
product with one or more CPU or signal processors.
To be the only independent and ensure that highly reusable peripheral and system
macro cells can be migrated across a diverse range of IC processes and be
appropriate for full-custom, standard cell and get array technologies
To encourage modular system design to improve processor independence,
providing a development road map for advanced cached CPU cores and the
development of peripheral libraries
To minimize the silicon infrastructure required to support efficient on-chip and
off-chip communication for both operation and manufacturing test
An AMBA based microcontroller typically consists of high performance system
backbone bus, able to sustain the external memory based width, on which the CPU on-chip
memory and other direct memory access (DMA) devices reside. This bus provides a high
bandwidth interface between the elements that are involved in the majority of transfers. Also
located on the lower bandwidth APB, where most of the peripheral devices in the systems are
located.
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Figure 3.1:AMBA Based SOC
3.1 AMBA AHB
AHB is a new generation of AMBA bus which is intended to address the
requirements of high-performance synthesizable designs. It is a high-performance system bus
that supports multiple bus masters and provides high-bandwidth operation.
AMBA AHB implements the features required for high-performance, high clock frequency
systems including
High performance
Pipelined operation
Multiple bus master
Burst transfers
Split transaction
An AMBA AHB design may contain one or more bus masters, typically a system would
contain at least the processor and test interface. However, it would also be common for a
Direct Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus
masters.
3.2 AMBA ASB
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ASB is the first generation of AMBA system bus. ASB sits above the current APB and
implements the features required for high-performance systems including
High performance
Pipelined operation
Multiple bus master
A typical AMBA ASB system may contain one or more bus masters( For example, at
least the processor and test interface). However, it would also be common for a Direct
Memory Access (DMA) or Digital Signal Processor (DSP) to be included as bus masters.
The external memory interface, APB bridge and any internal memory are the most
common ASB slaves. Any other peripheral in the system could also be included as an ASB
slave. However, low-bandwidth peripherals typically reside on the APB.
3.3 AMBA APB
The AMBA APB appears as a local secondary bus that is encapsulated as a single
AHB or ASB slave device. APB provides a low-power extension to the system bus which
builds on AHB or ASB signals directly.
The features of APB are
Low power.
Latched address and control
Simply interface
Suitable for many peripherals
An AMBA APB implementation typically contains a single APB bridge which is
required to convert AHB or ASB transfers into a suitable format for the slave devices on the
APB. The bridge provides latching of all address, data and control signals, as well as
providing a second level of decoding to generate slave select signals for the APB peripherals.
AMBA APB provides
the basic peripheral macro cell communication infrastructure. As a secondary bus from the
higher band width pipelined main system bus such peripherals typically
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Have interfaces which are memory mapped register.
Have no high bandwidth interfaces.
Are accessed under programmed control
3.4 The External Memory Interface
Specific and may only here a narrow data path that may also support address access mode
which allows the internal AMBA AHB, ASB & APB modules to be tested in isolation with
system independent test sets.
Bus cycle: A bus cycle is a basic unit of one bus clock period and for the purpose of
AMBA AHB or APB protocol description is defined from rising edge transactions.
Bus signal timing is referenced to the bus cycle clock.
Bus transfer: An AMBA ASB or AHB bus transfer is a read write operation of a data
object, which may take one or more bus cycles. The bus transfer is terminated by a
completion response from the addressed slave.
The transfer sizes supported by AMBA ASB include byte (8-bit), half word (16- bit)
and word (32-bit) AMBA AHB addressing supports wider data transfer including 64-
bit and 128-bit transfers An AMBA APB bus transfer is a read or write operation of a
data object which always requires two bus cycles
Burst operation: burst operation is defined as one or more data transactions initiated
by a bus master, which have a consistent width of transaction setup per transaction is
determined by the width of transfer. No burst operation is supported on the APB.
CHAPTER 4
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ARM INTERRUPT HANDLING
Interrupts which are kinds of exceptions are essential. It enables the system to deal
with external events by receiving interrupt signals telling the CPU that there is something to
be done-instead of the alternative way of doing the same operation by the pooling mechanism
which wastes the CPU time in looping forever checking some flags to know that the event
occurred.
Applies to: ARM1020/22E, ARM1026EJ-S, ARM1136, ARM720T, ARM7EJ-S,