i SINKRONISASI ANTARA PEMANCAR DAN PENERIMA MODULASI FREKUENSI DENGAN 4 FREQUENCY HOPPING TUGAS AKHIR Diajukan untuk memenuhi salah satu syarat memperoleh gelar Sarjana Teknik pada Program Studi Teknik Elektro Disusun oleh IGNATIUS TULUS SETIADI NIM : 045114013 PROGRAM STUDI TEKNIK ELEKTRO FAKULTAS SAINS DAN TEKNOLOGI UNIVERSITAS SANATA DHARMA YOGYAKARTA 2009
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Transcript
i
SINKRONISASI ANTARA PEMANCAR DAN
PENERIMA MODULASI FREKUENSI DENGAN
4 FREQUENCY HOPPING
TUGAS AKHIR
Diajukan untuk memenuhi salah satu syarat
memperoleh gelar Sarjana Teknik pada
Program Studi Teknik Elektro
Disusun oleh
IGNATIUS TULUS SETIADI
NIM : 045114013
PROGRAM STUDI TEKNIK ELEKTRO
FAKULTAS SAINS DAN TEKNOLOGI
UNIVERSITAS SANATA DHARMA
YOGYAKARTA
2009
ii
SYNCHRONOUS BETWEEN FM TRANSMITTER AND
FM RECEIVER WITH FOUR FREQUENCY HOPPING
FINAL PROJECT
Presented as Partial Fulfillment of the Requirements
to obtain the Sarjana Teknik Degree
in Electrical Engineering
By :
IGNATIUS TULUS SETIADI
Student Number : 045114013
ELECTRICAL ENGINEERING STUDY PROGRAM
SCIENCE AND TECHNOLOGY FACULTY
SANATA DHARMA UNIVERSITY
YOGYAKARTA
2009
iii
iv
v
vi
LEMBAR PERNYATAAN PERSETUJUAN
PUBLIKASI KARYA ILMIAH UNTUK KEPENTINGAN AKADEMIS
Yang bertanda tanggan di bawah ini, saya mahasiswa Universitas Sanata Dharma:
Nama : Ignatius Tulus Setiadi
Nomor Mahasiswa : 045114013
Demi pengembangan ilmu pengetahuan, saya memberikan kepada Perpustakaan
Universitas Sanata Dharma karya ilmiah saya yang berjudul :
Sinkonisasi Antara Pemancar Dan Penerima Modulasi Frekuensi
Dengan Empat Frequency Hopping beserta peragkat yang diperlukan (bila ada). Dengan demikian saya memberikan
kepada Perpustakaan Universitas Sanata Dharma hak untuk menyimpan, me-
ngalihkan dalam bentuk media lain, mengelolanya dalam bentuk pangkalan data,
mendistribusikan secara terbatas, dam mempublikasikan di internet atau media
lain untuk kepentingan akademis tanpa perlu meminta ijin dari saya maupun
memberikan royalti kepada saya selama tetap mencantumkan nama saya sebagai
penulis.
Demikian pernyataan ini yang saya buat dengan sebenarnya.
Dibuat di Yogyakarta
Pada tanggal : Agustus 2009
Yang Menyatakan
(Ignatius Tulus Setiadi)
vii
“You have to endure caterpillars if you want to see You have to endure caterpillars if you want to see You have to endure caterpillars if you want to see You have to endure caterpillars if you want to see
butterfliesbutterfliesbutterfliesbutterflies”
Seseorang yang oprimis akan melihat adanya kesempatan dalam setiap
malapetaka, sedangkan orang pesimis melihat malapetaka dalam setiap
kesempatan.
Jangan takut dengan kesalahan. Kebijaksanaan
biasanya lahir dari kesalahan.
KekuranganKekuranganKekuranganKekurangan----kekurangan yang kita lihat dalam kekurangan yang kita lihat dalam kekurangan yang kita lihat dalam kekurangan yang kita lihat dalam
diri mereka, kebanyakan adalah kekurangan kita diri mereka, kebanyakan adalah kekurangan kita diri mereka, kebanyakan adalah kekurangan kita diri mereka, kebanyakan adalah kekurangan kita
sendiri.sendiri.sendiri.sendiri.
Sukses adalah keberhasilan yang kamu capai dalam menggunakan talenta-talenta yang telah
Allah berikan kepada kamu
Karyaku ini kupersembahkan untuk Bapak dan Ibuku tercinta,
kakak-kakakku yang kucintai, dan untuk semua orang yang aku
sayangi dan menyayangi aku.
viii
INTISARI
Teknik frequency hopping (FH) merupakan salah satu metode transmisi
data dalam bidang telekomunikasi. Dengan frequency hopping, gangguan-
gangguan pada telekomunikasi seperti jamming dan noise dapat dikurangi.
Penelitian ini bertujuan untuk menghasilkan perangkat subsistem sinkronisasi
yang digunakan pemancar dan penerima Frequency Modulation (FM) frequency
hopping.
Subsistem sinkronisasi pada pemancar dan penerima FM frequency
hopping ini terdiri dari dua bagian utama yaitu tone generator dan tone decoder.
Tone generator terdiri dari keypad 1x4 yang berfungsi untuk mengatur tunda
waktu pada mikrokontroler ATTINY2313. Pengaturan tunda waktu
mempengaruhi sinyal DTMF yang dibangkitkan oleh IC MT8888. Sinyal DTMF
yang dihasilkan ditransmisikan melalui pemancar FM frequency hopping sebagai
pengendali fungsi hopping pada penerima FM frequency hopping. Sinyal DTMF
digunakan untuk sinkronisasi antara pemancar dan penerima FM frequency
hopping. Mikrokontroler ATTINY2313 yang digunakan pada tone decoder untuk
mengatur pembagi terprogram dalam membangkitkan frekuensi carrier dengan
data masukan berasal dari IC MT8870.
Hasil dari penelitian ini adalah subsistem sinkronisasi yang dapat
mensinkronkan pemancar FM frequency hopping dan penerima FM frequency
hopping dalam transmisi data. Sinyal DTMF yang dihasilkan perangkat subsistem
sinkronisasi bekerja dengan memodulasi frekuensi carrier secara bergantian pada
empat frekuensi yang berbeda yaitu 97 MHz, 99 MHz, 101 MHz dan 103 MHz
dengan periode hopping 0,25 detik.
Kata kunci : tone generator, tone decoder, sinkronisasi, frequency hopping, FM,
DTMF, subsistem.
ix
ABSTRACT
Frequency hopping technique is one of data transmission method in
telecommunication. Frequency hopping can minimize the effect of the
telecommunication disturbances such as jamming and noise. This research goal
aim is to produce synchonization subsystem that can synchronize between
frequency hopping FM transmitter and frequency hopping FM receiver.
Synchonization subsystem on transmitter and frequency hopping FM
receiver consists of two main section. There are tone generator and tone decoder.
Tone generator consists of 1x4 for controlling time delay on ATTINY2313
microcontroller. The time delay arrangement influencing DTMF signal that
generated by IC MT8888. DTMF signal that being resulted then transmitt to pass
frequency hopping FM transmitter as hopping function controller on frequency
hopping FM receiver. DTMF signal is used for synchonization between
transmitter and frequency hopping FM receiver. The function of ATTINY2313
microcontroller that is used for arrange programmable divider and generate carrier
frequency with data input from IC MT8870.
The result of the research are synchonization subsystem that can be
synchronize between frequency hopping FM transmitter and frequency hopping
FM receiver in transmitting data. DTMF signal that have been resulted
synchonization subsystem equipment operates with modulation four carrier
frequency, 97 MHz, 99 MHz, 101 MHz and 103 MHz with 0.25 second hopping
period.
Keyword : frequency hopping, tone generator, tone decoder, synchronization, FM,
DTMF, subsystem.
x
KATA PENGANTAR
Puji dan syukur penulis panjatkan ke Hadirat Tuhan Yang Maha Esa yang
telah melimpahkan rahmat dan karunia-Nya sehingga penulis dapat
menyelesaikan Tugas Akhir yang berjudul “Sinkronisasi Antara Pemancar Dan
Penerima Modulasi Frekuensi Dengan Empat Frequency Hopping”. Tugas
Akhir ini disusun sebagai salah satu syarat untuk memperoleh gelar Sarjana
Teknik. Dalam penyusunannya, banyak pihak yang telah membantu dan
memberikan dukungan pada penulis, oleh karena itu, penulis ingin mengucapkan
terima kasih kepada :
1. Bapak Damar Widjaja, S.T., M.T., selaku Dosen Pembimbing I Tugas
Akhir yang telah banyak meluangkan waktu untuk memberi
bimbingan.
2. Bapak Alexius Rukmono, S.T. selaku Pembimbing II yang telah
bersedia meluangkan waktu untuk membimbing penulis.
3. Untuk seluruh dosen-dosen di program studi Teknik Elektro atas
segala tempaan ilmunya.
4. Bapak (Agustinus Kastam) dan Ibuku tercinta (Mc. Mujiasih) yang
selalu memberiku dorongan, semangat, nasihat dan dukungan moril,
spiritual maupun materi.
5. Untuk kakak-kakakku, Budi Prasetyo sekeluarga, Erni Dwiantari
sekeluarga, dan Yogie Triatno atas segala bantuan moril, spiritual
maupun materi.
xi
6. Untuk seluruh teman-teman elektro angkatan 2004 atas segala doa dan
dukungannya.
7. Untuk teman-teman hopping modulasi frekuensi Nova Budi Prasetyo
dan Yanuarius Vendi Purnomo atas segala masukan dan bantuannya.
8. Untuk saudara F. Ade Krismawan, S.T. yang telah membantuku dan
Data frekuensi carrier pada VCO (Voltage Controlled Oscillator)
1. Frekuensi carrier 97 MHz
2. Frekuensi carrier 99 MHz
3. Frekuensi carrier 101 MHz
L12
4. Frekuensi carrier 103 MHz
Data spektrum frekuensi sinyal DTMF dan sinyal informasi
Frekuensi sinyal DTMF 1 atau tone 1 pada Mixer audio
1. Sinyal informasi 4 kHz
2. Sinyal informasi 5 kHz
L13
3. Sinyal informasi 6 kHz
4. Sinyal informasi 7 kHz
5. Sinyal informasi 8 kHz
6. Sinyal informasi 9 kHz
L14
Frekuensi sinyal DTMF 2 atau tone 2 pada Mixer audio
1. Sinyal informasi 4 kHz
2. Sinyal informasi 5 kHz
3. Sinyal informasi 6 kHz
4. Sinyal informasi 7 kHz
L15
5. Sinyal informasi 8 kHz
6. Sinyal informasi 9 kHz
Frekuensi sinyal DTMF 3 atau tone 3 pada Mixer audio
1. Sinyal informasi 4 kHz
2. Sinyal informasi 5 kHz
L16
3. Sinyal informasi 6 kHz
4. Sinyal informasi 7 kHz
5. Sinyal informasi 8 kHz
6. Sinyal informasi 9 kHz
L17
Frekuensi sinyal DTMF 4 atau tone 4 pada Mixer audio
1. Sinyal informasi 4 kHz
2. Sinyal informasi 5 kHz
3. Sinyal informasi 6 kHz
4. Sinyal informasi 7 kHz
L18
5. Sinyal informasi 8 kHz
6. Sinyal informasi 9 kHz
2543DS–AVR–03/04
Features• Utilizes the AVR® RISC Architecture• AVR – High-performance and Low-power RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution– 32 x 8 General Purpose Working Registers– Fully Static Operation– Up to 24 MIPS Throughput at 24 MHz
• Data and Non-volatile Program and Data Memories– 2K Bytes of In-System Self Programmable Flash
Endurance: 100,000 Write/Erase Cycles– 128 Bytes Internal SRAM– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes– Four PWM Channels– On-chip Analog Comparator– Programmable Watchdog Timer with On-chip Oscillator– USI – Universal Serial Interface– Full Duplex USART
• Special Microcontroller Features– debugWIRE On-chip Debugging– In-System Programmable via SPI Port– External and Internal Interrupt Sources– Low-power Idle, Power-down, and Standby Modes– Enhanced Power-on Reset Circuit– Programmable Brown-out Detection Circuit– Internal Calibrated Oscillator
• I/O and Packages– 18 Programmable I/O Lines– 20-pin PDIP, 20-pin SOIC, and 32-pin MLF
8-bit Microcontroller with 2K Bytes In-SystemProgrammable Flash
ATtiny2313/V
PreliminarySummary
Rev. 2543DS–AVR–03/04
Note: This is a summary document. A complete documentis available on our Web site at www.atmel.com.
2 ATtiny2313/V2543DS–AVR–03/04
Pin Configurations Figure 1. Pinout ATtiny2313
Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVRenhanced RISC architecture. By executing powerful instructions in a single clock cycle,the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the systemdesigner to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowingtwo independent registers to be accessed in one single instruction executed in one clockcycle. The resulting architecture is more code efficient while achieving throughputs up toten times faster than conventional CISC microcontrollers.
The ATtiny2313 provides the following features: 2K bytes of In-System ProgrammableFlash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 generalpurpose working registers, a single-wire Interface for On-chip Debugging, two flexibleTimer/Counters with compare modes, internal and external interrupts, a serial program-mable USART, Universal Serial Interface with Start Condition Detector, a programmableWatchdog Timer with internal Oscillator, and three software selectable power savingmodes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, andinterrupt system to continue functioning. The Power-down mode saves the register con-tents but freezes the Oscillator, disabling all other chip functions until the next interruptor hardware reset. In Standby mode, the crystal/resonator Oscillator is running while therest of the device is sleeping. This allows very fast start-up combined with low-powerconsumption.
The device is manufactured using Atmel’s high density non-volatile memory technology.The On-chip ISP Flash allows the program memory to be reprogrammed In-Systemthrough an SPI serial interface, or by a conventional non-volatile memory programmer.By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a mono-lithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highlyflexible and cost effective solution to many embedded control applications.
The ATtiny2313 AVR is supported with a full suite of program and system developmenttools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-cuit Emulators, and Evaluation kits.
5
ATtiny2313/V
2543DS–AVR–03/04
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port A output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port A pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port A pins are tri-stated when a resetcondition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATtiny2313 as listedon page 52.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port B output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port B pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port B pins are tri-stated when a resetcondition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny2313 as listedon page 52.
Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port D output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port D pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port D pins are tri-stated when a resetcondition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATtiny2313 as listedon page 55.
RESET Reset input. A low level on this pin for longer than the minimum pulse length will gener-ate a reset, even if the clock is not running. The minimum pulse length is given in Table15 on page 33. Shorter pulses are not guaranteed to generate a reset. The Reset Inputis an alternate function for PA2 and dW.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.XTAL1 is an alternate function for PA0.
XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.
Figure 3.
6 ATtiny2313/V2543DS–AVR–03/04
Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informationand minimum quantities.
2. Pb-free packaging alternative.3. See Figure 81 on page 177 and Figure 82 on page 177.
Speed (MHz) Power Supply Ordering Code Package(1) Operation Range
20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
13
ATtiny2313/V
2543DS–AVR–03/04
Errata The revision in this section refers to the revision of the ATtiny2313 device.
ATtiny2313 Rev B • Wrong values read after Erase Only operation• Parallel Programming does not work• Watchdog Timer Interrupt disabled
1. Wrong values read after Erase Only operation
At supply voltages below 2.7 V, an EEPROM location that is erased by the EraseOnly operation may read as programmed (0x00).
Problem Fix/Workaround
If it is necessary to read an EEPROM location after Erase Only, use an Atomic Writeoperation with 0xFF as data in order to erase a location. In any case, the Write Onlyoperation can be used as intended. Thus no special considerations are needed aslong as the erased location is not read before it is programmed.
2. Parallel Programming does not work
Parallel Programming is not functioning correctly. Because of this, reprogrammingof the device is impossible if one of the following modes are selected:
Serial Programming is still working correctly. By avoiding the two modes above, thedevice can be reprogrammed serially.
3. Watchdog Timer Interrupt disabled
If the watchdog timer interrupt flag is not cleared before a new timeout occurs, thewatchdog will be disabled, and the interrupt flag will automatically be cleared. This isonly applicable in interrupt only mode. If the Watchdog is configured to reset thedevice in the watchdog time-out following an interrupt, the device works correctly.
Problem fix / Workaround
Make sure there is enough time to always service the first timeout event before anew watchdog timeout occurs. This is done by selecting a long enough time-outperiod.
ATtiny2313 Rev A Revision A has not been sampled.
4-91
Features
• Central office quality DTMF transmitter/receiver
• Low power consumption
• High speed Intel micro interface
• Adjustable guard time
• Automatic tone burst mode
• Call progress tone detection to -30dBm
Applications
• Credit card systems
• Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• Personal computers
Description
The MT8888C is a monolithic DTMF transceiver withcall progress filter. It is fabricated in CMOStechnology offering low power consumption and highreliability.
The receiver section is based upon the industrystandard MT8870 DTMF receiver while thetransmitter utilizes a switched capacitor D/Aconverter for low distortion, high accuracy DTMFsignalling. Internal counters provide a burst modesuch that tone bursts can be transmitted with precisetiming. A call progress filter can be selected allowinga microprocessor to analyze call progress tones.
The MT8888C utilizes an Intel micro interface, whichallows the device to be connected to a number ofpopular microcontrollers with minimal external logic.The MT8888C-1 is functionally identical to theMT8888C except the receiver is enhanced to acceptlower level signals, and also has a specified lowsignal rejection level.
3 3 GS Gain Select . Gives access to output of front end differential amplifier for connection of feedback resistor.
4 4 VRef Reference Voltage output (VDD/2).
5 5 VSS Ground (0V).
6 6 OSC1 Oscillator input. This pin can also be driven directly by an external clock.
7 7 OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter, see Figure 8.
14-17
18-21
D0-D3 Microprocessor Data Bus. High impedance when CS = 1 or RD = 1.TTL compatible.
18 22 ESt Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
19 23 St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St.
20 24 VDD Positive power supply (5V typ.).
8,916,17
NC No Connection.
12345678910 11
12
2019181716151413
IN+IN-GS
VRefVSS
OSC1OSC2TONE
R/WCS
VDDSt/GTEStD3D2D1D0IRQ/CPRDRS0
NC
123456789101112 13
141516
2423222120191817
IN+IN-GS
VRefVSS
OSC1OSC2
NCTONE
R/WCS
VDDSt/GTEStD3D2D1D0NCNCIRQ/CPRDRS0
24 PIN SSOP20 PIN CERDIP/PLASTIC DIP/SOIC
MT8888C/MT8888C-1
4-93
Functional Description
The MT8888C/MT8888C-1 Integrated DTMFTransceiver consists of a high performance DTMFreceiver with an internal gain setting amplifier and aDTMF generator which employs a burst counter tosynthesize precise tone bursts and pauses. A callprogress mode can be selected so that frequencieswithin the specified passband can be detected. TheIntel micro interface allows microcontrollers, such asthe 8080, 80C31/51 and 8085, to access theMT8888C/MT8888C-1 internal registers.
Input Configuration
The input arrangement of the MT8888C/MT8888C-1provides a differential-input operational amplifier aswell as a bias source (VRef), which is used to bias theinputs at VDD/2. Provision is made for connection ofa feedback resistor to the op-amp output (GS) forgain adjustment. In a single-ended configuration, theinput pins are connected as shown in Figure 3.
Figure 4 shows the necessary connections for adifferential input configuration.
Receiver Section
Separation of the low and high group tones isachieved by applying the DTMF signal to the inputsof two sixth-order switched capacitor bandpassfilters, the bandwidths of which correspond to the lowand high group frequencies (see Table 1). Thesefilters incorporate notches at 350 Hz and 440 Hz forexceptional dial tone rejection. Each filter output isfollowed by a single order switched capacitor filtersection, which smooths the signals prior to limiting.Limiting is performed by high-gain comparatorswhich are provided with hysteresis to preventdetection of unwanted low-level signals. The outputsof the comparators provide full rail logic swings atthe frequencies of the incoming DTMF signals.
Following the filter section is a decoder employingdigital counting techniques to determine thefrequencies of the incoming tones and to verify thatthey correspond to standard DTMF frequencies. Acomplex averaging algorithm protects against tonesimulation by extraneous signals such as voice whileproviding tolerance to small frequency deviationsand variations. This averaging algorithm has beendeveloped to ensure an optimum combination ofimmunity to talk-off and tolerance to the presence ofinterfering frequencies (third tones) and noise. Whenthe detector recognizes the presence of two validtones (this is referred to as the “signal condition” insome industry specifications) the “Early Steering”(ESt) output will go to an active state. Anysubsequent loss of signal condition will cause ESt toassume an inactive state.
Steering Circuit
Before registration of a decoded tone pair, thereceiver checks for a valid signal duration (referredto as character recognition condition). This check isperformed by an external RC time constant driven byESt. A logic high on ESt causes vc (see Figure 5) torise as the capacitor discharges. Provided that thesignal condition is maintained (ESt remains high) forthe validation period (tGTP), vc reaches the threshold(VTSt) of the steering logic to register the tone pair,latching its corresponding 4-bit code (see Table 1)into the Receive Data Register. At this point the GToutput is activated and drives vc to VDD. GTcontinues to drive high as long as ESt remains high.Finally, after a short delay to allow the output latch tosettle, the delayed steering output flag goes high,signalling that a received tone pair has beenregistered. The status of the delayed steering flagcan be monitored by checking the appropriate bit inthe status register. If Interrupt mode has beenselected, the IRQ/CP pin will pull low when thedelayed steering flag is active. The contents of the output latch are updated on anactive delayed steering transition. This data ispresented to the four bit bidirectional data bus whenthe Receive Data Register is read. The steeringcircuit works in reverse to validate the interdigitpause between signals. Thus, as well as rejectingsignals too short to be considered valid, the receiverwill tolerate signal interruptions (drop out) too shortto be considered a valid pause. This facility, togetherwith the capability of selecting the steering timeconstants externally, allows the designer to tailorperformance to meet a wide variety of systemrequirements.
Figure 5 - Basic Steering Circuit
Guard Time Adjustment
The simple steering circuit shown in Figure 5 isadequate for most applications. Component valuesare chosen according to the following inequalities(see Figure 7):
The value of tDP is a device parameter (see ACElectrical Characteristics) and tREC is the minimumsignal duration to be recognized by the receiver. Avalue for C1 of 0.1 µF is recommended for most
Figure 6 - Guard Time Adjustment
VDD
VDD
St/GT
ESt
C1
Vc
R1
MT8888C/
tGTA = (R1C1) In (VDD / VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
MT8888C-1
VDD
St/GT
ESt
VDD
St/GT
ESt
C1
R1 R2
C1
R1 R2
tGTA = (R1C1) In (VDD/VTSt)
tGTP = (RPC1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
tGTA = (RpC1) In (VDD/VTSt)
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
RP = (R1R2) / (R1 + R2)
a) decreasing tGTP; (tGTP < tGTA)
b) decreasing tGTA; (tGTP > tGTA)
MT8888C/MT8888C-1
4-95
applications, leaving R1 to be selected by thedesigner. Different steering arrangements may beused to select independent tone present (tGTP) andtone absent (tGTA) guard times. This may benecessary to meet system specifications which placeboth accept and reject limits on tone duration andinterdigital pause. Guard time adjustment also allowsthe designer to tailor system parameters such as talkoff and noise immunity.
Increasing tREC improves talk-off performance sinceit reduces the probability that tones simulated byspeech will maintain a valid signal condition longenough to be registered. Alternatively, a relativelyshort tREC with a long tDO would be appropriate forextremely noisy environments where fast acquisitiontime and immunity to tone drop-outs are required.Design information for guard time adjustment isshown in Figure 6. The receiver timing is shown inFigure 7 with a description of the events in Figure 9.
Call Progress Filter
A call progress mode, using the MT8888C/MT8888C-1, can be selected allowing the detectionof various tones, which identify the progress of atelephone call on the network. The call progresstone input and DTMF input are common, however,call progress tones can only be detected when CP
mode has been selected. DTMF signals cannot bedetected if CP mode has been selected (see Table7). Figure 8 indicates the useful detect bandwidth ofthe call progress filter. Frequencies presented to theinput, which are within the ‘accept’ bandwidth limitsof the filter, are hard-limited by a high gaincomparator with the IRQ/CP pin serving as theoutput. The squarewave output obtained from theschmitt trigger can be analyzed by a microprocessoror counter arrangement to determine the nature ofthe call progress tone being detected. Frequencieswhich are in the ‘reject’ area will not be detected andconsequently the IRQ/CP pin will remain low.
Figure 8 - Call Progress Response
AAAAAAAAAAAAAAAAAAAA
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AAAAAAAAAAAAAAAAAAAA
AAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAA
LEVEL(dBm)
FREQUENCY (Hz)
-25
0 250 500 750
= Reject
= May Accept
= Accept
Figure 7 - Receiver Timing Diagram
Vin
ESt
St/GT
RX0-RX3
b3
b2
ReadStatusRegister
IRQ/CP
EVENTS A B C D E F
tRECtREC tID tDO
TONE #n TONE#n + 1
TONE#n + 1
tDP tDA
tGTPtGTA
tPStRX
tPStb3
DECODED TONE # (n-1) # n # (n + 1)
VTSt
MT8888C/MT8888C-1
4-96
Figure 9 - Description of Timing Events
EXPLANATION OF EVENTSA) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER.C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED.F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER
RETAINED UNTIL NEXT VALID TONE PAIR.
EXPLANATION OF SYMBOLSVin DTMF COMPOSITE INPUT SIGNAL.ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.RX0-RX3 4-BIT DECODED DATA IN RECEIVE DATA REGISTERb3 DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL.
b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA REGISTER. THE BIT IS CLEARED AFTER THE STATUS REGISTER IS READ.
IRQ/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS CLEARED AFTER THE STATUS REGISTER IS READ.
tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID.tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION.tID MINIMUM TIME BETWEEN VALID SEQUENTIAL DTMF SIGNALS.tDO MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL.tDP TIME TO DETECT VALID FREQUENCIES PRESENT.tDA TIME TO DETECT VALID FREQUENCIES ABSENT.tGTP GUARD TIME, TONE PRESENT.tGTA GUARD TIME, TONE ABSENT.
DTMF Generator
The DTMF transmitter employed in the MT8888C/MT8888C-1 is capable of generating all sixteenstandard DTMF tone pairs with low distortion andhigh accuracy. All frequencies are derived from anexternal 3.579545 MHz crystal. The sinusoidalwaveforms for the individual tones are digitallysynthesized using row and column programmabledividers and switched capacitor D/A converters. Therow and column tones are mixed and filteredproviding a DTMF signal with low total harmonicdistortion and high accuracy. To specify a DTMFsignal, data conforming to the encoding formatshown in Table 1 must be written to the transmit DataRegister. Note that this is the same as the receiveroutput code. The individual tones which aregenerated (fLOW and fHIGH) are referred to as LowGroup and High Group tones. As seen from thetable, the low group frequencies are 697, 770, 852and 941 Hz. The high group frequencies are 1209,1336, 1477 and 1633 Hz. Typically, the high group tolow group amplitude ratio (twist) is 2 dB to com-pensate for high group attenuation on long loops.
The period of each tone consists of 32 equal timesegments. The period of a tone is controlled byvarying the length of these time segments. During
write operations to the Transmit Data Register the 4bit data on the bus is latched and converted to 2 of 8coding for use by the programmable divider circuitry.This code is used to specify a time segment length,which will ultimately determine the frequency of thetone. When the divider reaches the appropriatecount, as determined by the input code, a reset pulseis issued and the counter starts again. The numberof time segments is fixed at 32, however, by varyingthe segment length as described above thefrequency can also be varied. The divider outputclocks another counter, which addresses thesinewave lookup ROM.
The lookup table contains codes which are used bythe switched capacitor D/A converter to obtaindiscrete and highly accurate DC voltage levels. Twoidentical circuits are employed to produce row andcolumn tones, which are then mixed using a lownoise summing amplifier. The oscillator describedneeds no “start-up” time as in other DTMFgenerators since the crystal oscillator is runningcontinuously thus providing a high degree of toneburst accuracy. A bandwidth limiting filter isincorporated and serves to attenuate distortionproducts above 8 kHz. It can be seen from Figure 8that the distortion products are very low in amplitude.
MT8888C/MT8888C-1
4-97
Figure 10 - Spectrum Plot
Scaling Information
10 dB/DivStart Frequency = 0 HzStop Frequency = 3400 HzMarker Frequency = 697 Hz and1209 Hz
Burst Mode
In certain telephony applications it is required thatDTMF signals being generated are of a specificduration determined either by the particularapplication or by any one of the exchange transmitterspecifications currently existing. Standard DTMFsignal timing can be accomplished by making use ofthe Burst Mode. The transmitter is capable of issuingsymmetric bursts/pauses of predetermined duration.This burst/pause duration is 51 ms±1 ms, which is astandard interval for autodialer and central officeapplications. After the burst/pause has been issued,the appropriate bit is set in the Status Registerindicating that the transmitter is ready for more data.The timing described above is available when DTMFmode has been selected. However, when CP mode(Call Progress mode) is selected, the burst/pauseduration is doubled to 102 ms ±2 ms. Note that whenCP mode and Burst mode have been selected,DTMF tones may be transmitted only and notreceived. In applications where a non-standardburst/pause time is desirable, a software timing loopor external timer can be used to provide the timingpulses when the burst mode is disabled by enablingand disabling the transmitter.
Single Tone Generation
A single tone mode is available whereby individualtones from the low group or high group can begenerated. This mode can be used for DTMF testequipment applications, acknowledgment tonegeneration and distortion measurements. Refer toControl Register B description for details.
Table 2. Actual Frequencies Versus Standard Requirements
Distortion Calculations
The MT8888C/MT8888C-1 is capable of producingprecise tone bursts with minimal error in frequency(see Table 2). The internal summing amplifier isfollowed by a first-order lowpass switched capacitorfilter to minimize harmonic components andintermodulation products. The total harmonicdistortion for a single tone can be calculated usingEquation 1, which is the ratio of the total power of allthe extraneous frequencies to the power of thefundamental frequency expressed as a percentage.
Equation 1. THD (%) For a Single Tone
ACTIVEINPUT
OUTPUT FREQUENCY (Hz) %ERROR
SPECIFIED ACTUAL
L1 697 699.1 +0.30
L2 770 766.2 -0.49
L3 852 847.4 -0.54
L4 941 948.0 +0.74
H1 1209 1215.9 +0.57
H2 1336 1331.7 -0.32
H3 1477 1471.9 -0.35
H4 1633 1645.0 +0.73
THD (%) = 100Vfundamental
V22f + V2
3f + V24f + .... V2
nf
MT8888C/MT8888C-1
4-98
The Fourier components of the tone outputcorrespond to V2f.... Vnf as measured on the outputwaveform. The total harmonic distortion for a dualtone can be calculated using Equation 2. VL and VHcorrespond to the low group amplitude and highgroup amplitude, respectively and V2
IMD is the sumof all the intermodulation components. The internalswitched-capacitor filter following the D/A converterkeeps distortion products down to a very low level asshown in Figure 10.
Equation 2. THD (%) For a Dual Tone
DTMF Clock Circuit
The internal clock circuit is completed with theaddition of a standard television colour burst crystal.The crystal specification is as follows:
A number of MT8888C/MT8888C-1 devices can beconnected as shown in Figure 11 such that only onecrystal is required. Alternatively, the OSC1 inputs onall devices can be driven from a TTL buffer with theOSC2 outputs left unconnected.
Figure 11 - Common Crystal Connection
Microprocessor Interface
The MT8888C/MT8888C-1 incorporates an Intelmicroprocessor interface which is compatible withfast versions (16 MHz) of the 80C51. No wait cyclesneed to be inserted.
V2L + V2
H
V22L + V2
3L + .... V2nL + V2
2H +
V23H + .. V2
nH + V2IMD
THD (%) = 100
MT8888C/
OSC1 OSC2
MT8888C/
OSC1 OSC2
MT8888C/
OSC1 OSC2
3.579545 MHz
MT8888C-1 MT8888C-1 MT8888C-1
Figures 17 and 18 are the timing diagrams for theIntel 8031, 8051 and 8085 (5 MHz) microcontrollers.By NANDing the address latch enable (ALE) outputwith the high-byte address (P2) decode output, CS isgenerated. Figure 12 summarizes the connection ofthese Intel processors to the MT8888C/MT8888C-1transceiver.
The microprocessor interface provides access to fiveinternal registers. The read-only Receive DataRegister contains the decoded output of the lastvalid DTMF digit received. Data entered into thewrite-only Transmit Data Register will determinewhich tone pair is to be generated (see Table 1 forcoding details). Transceiver control is accomplishedwith two control registers (see Tables 6 and 7), CRAand CRB, which have the same address. A writeoperation to CRB is executed by first setting themost significant bit (b3) in CRA. The following writeoperation to the same address will then be directedto CRB, and subsequent write cycles will be directedback to CRA. The read-only status register indicatesthe current transceiver state (see Table 8).
A software reset must be included at the beginningof all programs to initialize the control registers uponpower-up or power reset (see Figure 17). Refer toTables 4-7 for bit descriptions of the two controlregisters.
The multiplexed IRQ/CP pin can be programmed togenerate an interrupt upon validation of DTMFsignals or when the transmitter is ready for moredata (burst mode only). Alternatively, this pin can beconfigured to provide a squarewave output of the callprogress signal. The IRQ/CP pin is an open drainoutput and requires an external pull-up resistor (seeFigure 13).
Table 3. Internal Register Functions
Table 4. CRA Bit Positions
Table 5. CRB Bit Positions
RS0 WR RD FUNCTION
0 0 1 Write to TransmitData Register
0 1 0 Read from ReceiveData Register
1 0 1 Write to Control Register
1 1 0 Read from Status Register
b3 b2 b1 b0
RSEL IRQ CP/DTMF TOUT
b3 b2 b1 b0
C/R S/D TEST BURST ENABLE
MT8888C/MT8888C-1
4-99
Table 6. Control Register A Description
Table 7 . Control Register B Description
BIT NAME DESCRIPTION
b0 TOUT Tone Output Control. A logic high enables the tone output; a logic low turns the tone outputoff. This bit controls all transmit tone functions.
b1 CP/DTMF Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;a logic low enables DTMF mode. In DTMF mode the device is capable of receiving andtransmitting DTMF signals. In CP mode a rectangular wave representation of the receivedtone signal will be present on the IRQ/CP output pin if IRQ has been enabled (controlregister A, b2=1). In order to be detected, CP signals must be within the bandwidthspecified in the AC Electrical Characteristics for Call Progress.Note: DTMF signals cannot be detected when CP mode is selected.
b2 IRQ Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates theinterrupt function. When IRQ is enabled and DTMF mode is selected (control register A,b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has beenreceived for a valid guard time duration, or 2) the transmitter is ready for more data (burstmode only).
b3 RSEL Register Select. A logic high selects control register B for the next write cycle to the controlregister address. After writing to control register B, the following control register write cyclewill be directed to control register A.
BIT NAME DESCRIPTION
b0 BURST Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode.When activated, the digital code representing a DTMF signal (see Table 1) can be writtento the transmit register, which will result in a transmit DTMF tone burst and pause of equaldurations (typically 51 msec.). Following the pause, the status register will be updated (b1 -Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has beenenabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pausedurations are extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by theTOUT bit (control register A, b0).
b1 TEST Test Mode Control. A logic high enables the test mode; a logic low de-activates the testmode. When TEST is enabled and DTMF mode is selected (control register A, b1=0), thesignal present on the IRQ/CP pin will be analogous to the state of the DELAYEDSTEERING bit of the status register (see Figure 7, signal b3).
b2 S/D Single or Dual Tone Generation. A logic high selects the single tone output; a logic lowselects the dual tone (DTMF) output. The single tone generation function requires furtherselection of either the row or column tones (low or high group) through the C/R bit (controlregister B, b3).
b3 C/R Column or Row Tone Select. A logic high selects a column tone output; a logic low selectsa row tone output. This function is used in conjunction with the S/D bit (control register B,b2).
MT8888C/MT8888C-1
4-100
Table 8 . Status Register Description
Figure 12 - MT8888C Interface Connections for Various Intel Micros
* Microprocessor based systems can inject undesirable noise into the supply rails.The performance of the MT8888C/MT8888C-1 can be optimized by keepingnoise on the supply rails to a minimum. The decoupling capacitor (C3) should beconnected close to the device and ground loops should be avoided.
MT8888C/MT8888C-1
MT8888C/MT8888C-1
4-101
Figure 14 - Test Circuits
Figure 15 - Application Notes
TEST POINT
MMD6150 (or equivalent)
5.0 VDC
2.4 kΩ
24 kΩ130 pF
MMD7000 (orequivalent)
TEST POINT
5.0 VDC
3 kΩ
100 pF
Test load for IRQ /CP pinTest load for D0-D3 pins
INITIALIZATION PROCEDUREA software reset must be included at the beginning of all programs to initialize the control registers afterpower up.The initialization procedure should be implemented 100ms after power up.Description: Control Data
RS0 WR RD b3 b2 b1 b01) Read Status Register 1 1 0 X X X X2) Write to Control Register 1 0 1 0 0 0 03) Write to Control Register 1 0 1 0 0 0 04) Write to Control Register 1 0 1 1 0 0 05) Write to Control Register 1 0 1 0 0 0 06) Read Status Register 1 1 0 X X X X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONSTransmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones.
Sequence:RS0 WR RD b3 b2 b1 b0
1) Write to Control Register A 1 0 1 1 1 0 1(tone out, DTMF, IRQ, Select Control Register B)
2) Write to Control Register B 1 0 1 0 0 0 0(burst mode)
3) Write to Transmit Data Register 0 0 1 0 1 1 1(send a digit 7)
4) Wait for an interrupt or poll Status Register5) Read the Status Register 1 1 0 X X X X
-if bit 1 is set, the Tx is ready for the next tone, in which case...Write to Transmit Register 0 0 1 0 1 0 1(send a digit 5)
-if bit 2 is set, a DTMF tone has been received, in which case....Read the Receive Data Register 0 1 0 X X X X
-if both bits are set...Read the Receive Data Register 0 1 0 X X X XWrite to Transmit Data Register 0 0 1 0 1 0 1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (±2 ms) AFTER THE DATA IS
WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms (± 4 ms) .
MT8888C/MT8888C-1
4-102
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
‡ Typical figures are at 25 °C and for design aid only: not guaranteed and not subject to production testing.
† Characteristics are over recommended operating conditions unless otherwise stated.‡ Typical figures are at 25 °C, VDD =5V and for design aid only: not guaranteed and not subject to production testing.* See “Notes” following AC Electrical Characteristics Tables.
Absolute Maximum Ratings *
Parameter Symbol Min Max Units
1 Power supply voltage VDD-VSS VDD 6 V
2 Voltage on any pin VI VSS-0.3 VDD+0.3 V
3 Current at any pin (Except VDD and VSS) 10 mA
4 Storage temperature TST -65 +150 °C
5 Package power dissipation PD 1000 mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter Sym Min Typ ‡ Max Units Test Conditions
1 Positive power supply VDD 4.75 5.00 5.25 V
2 Operating temperature TO -40 +85 °C
3 Crystal clock frequency fCLK 3.575965 3.579545 3.583124 MHz
DC Electrical Characteristics † - VSS=0 V.
Characteristics Sym Min Typ ‡ Max Units Test Conditions
1SUP
Operating supply voltage VDD 4.75 5.0 5.25 V
2 Operating supply current IDD 7.0 11 mA
3 Power consumption PC 57.8 mW
4 INPUTS
High level input voltage(OSC1)
VIHO 3.5 V Note 9*
5 Low level input voltage(OSC1)
VILO 1.5 V Note 9*
6 Steering threshold voltage VTSt 2.2 2.3 2.5 V VDD=5V
7
OUTPUTS
Low level output voltage (OSC2) VOLO 0.1 V
No loadNote 9*
8 High level output voltage(OSC2) VOHO 4.9 V
No loadNote 9*
9 Output leakage current(IRQ) IOZ 1 10 µA VOH=2.4 V
10 VRef output voltage VRef 2.4 2.5 2.6 V No load, VDD=5V
11 VRef output resistance ROR 1.3 kΩ
12 Digital
Low level input voltage VIL 0.8 V
13 High level input voltage VIH 2.0 V
14 Input leakage current IIZ 10 µA VIN=VSS to VDD
15 DataBus
Source current IOH -1.4 -6.6 mA VOH=2.4V
16 Sink current IOL 2.0 4.0 mA VOL=0.4V
17 EStand
St/Gt
Source current IOH -0.5 -3.0 mA VOH=4.6V
18 Sink current IOL 2 4 mA VOL=0.4V
19 IRQ/CP
Sink current IOL 4 16 mA VOL=0.4V
MT8888C/MT8888C-1
4-103
‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
† Characteristics are over recommended temperature and at VDD=5V, using the test circuit shown in Figure 13.
† Characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in Figure 13.
† Characteristics are over recommended operating conditions unless otherwise stated.‡ Typical figures are at 25°C, VDD = 5V, and for design aid only: not guaranteed and not subject to production testing.* *See “Notes” following AC Electrical Characteristics Tables.
Electrical CharacteristicsGain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=5V, TO=25°C.
Characteristics Sym Min Typ ‡ Max Units Test Conditions
1 Input leakage current IIN ±100 nA VSS ≤ VIN ≤ VDD
2 Input resistance RIN 10 MΩ
3 Input offset voltage VOS 25 mV
4 Power supply rejection PSRR 60 dB 1 kHz
5 Common mode rejection CMRR 60 dB 0.75 ≤ VIN ≤ 4.25V
6 DC open loop voltage gain AVOL 65 dB
7 Unity gain bandwidth BW 1.5 MHz
8 Output voltage swing VO 4.5 Vpp RL ≥ 100 kΩ to VSS
9 Allowable capacitive load (GS) CL 100 pF
10 Allowable resistive load (GS) RL 50 kΩ
11 Common mode range VCM 3.0 Vpp No Load
MT8888C-1 AC Electrical Characteristics † - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym Min Typ Max Units Notes*
1
RX
Valid input signal levels (each tone of composite signal)
-31 +1 dBm 1,2,3,5,6
21.8 869 mVRMS 1,2,3,5,6
2 Input Signal Level Reject -37 dBm 1,2,3,5,6
10.9 mVRMS 1,2,3,5,6
MT8888C AC Electrical Characteristics † - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym Min Typ ‡ Max Units Notes*
1RX
Valid input signal levels (each tone of composite signal)
-29 +1 dBm 1,2,3,5,6
27.5 869 mVRMS 1,2,3,5,6
AC Electrical Characteristics † - Voltages are with respect to ground (VSS) unless otherwise stated. fC=3.579545 MHz
Characteristics Sym Min Typ ‡ Max Units Notes*
1
RX
Positive twist accept 8 dB 2,3,6,9
2 Negative twist accept 8 dB 2,3,6,9
3 Freq. deviation accept ±1.5%± 2Hz 2,3,5
4 Freq. deviation reject ±3.5% 2,3,5
5 Third tone tolerance -16 dB 2,3,4,5,9,10
6 Noise tolerance -12 dB 2,3,4,5,7,9,10
7 Dial tone tolerance 22 dB 2,3,4,5,8,9
MT8888C/MT8888C-1
4-104
† Characteristics are over recommended operating conditions unless otherwise stated‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
† Characteristics are over recommended operating conditions unless otherwise stated‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
† Timing is over recommended temperature & power supply voltages. ‡ Typical figures are at 25°C and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics †- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym Min Typ ‡ Max Units Conditions
† Characteristics are over recommended operating conditions unless otherwise stated‡ Typical figures are at 25°C, VDD=5V, and for design aid only: not guaranteed and not subject to production testing
NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load.2) Digit sequence consists of all 16 DTMF tones.3) Tone duration=40 ms. Tone pause=40 ms.4) Nominal DTMF frequencies are used.5) Both tones in the composite signal have an equal amplitude.6) The tone pair is deviated by ± 1.5%±2 Hz.7) Bandwidth limited (3 kHz) Gaussian noise.8) The precise dial tone frequencies are 350 and 440 Hz (±2%).9) Guaranteed by design and characterization. Not subject to production testing.10) Referenced to the lowest amplitude tone in the DTMF signal.11) For guard time calculation purposes.
AC Electrical Characteristics †- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics Sym Min Typ ‡ Max Units Conditions
1 RD/WR clock frequency fCYC 4.0 MHz Figure 16
2 RD/WR cycle period tCYC 250 ns Figure 16
3 RD/WR rise and fall time tR, tF 20 ns Figure 16
4 Address setup time tAS 23 ns Figures 17 & 18
5 Address hold time tAH 26 ns Figures 17 & 18
6 Data hold time (read) tDHR 22 ns Figures 17 & 18
7 RD to valid data delay (read) tDDR 100 ns Figures 17 & 18
10 Data setup time (write) tDSW 45 ns Figures 17 & 18
11 Data hold time (write) tDHW 10 ns Figures 17 & 18
12 Input Capacitance (data bus) CIN 5 pF
13 Output Capacitance (IRQ/CP) COUT 5 pF
MT8888C/MT8888C-1
4-106
Figure 16 - RD /WR Clock Pulse
Figure 17 - 8031/8051/8085 Read Timing Diagram
Figure 18 - 8031/8051/8085 Write Timing Diagram
tCYC
tR
tPWH tPWLRD/WR
tF
RD
CS, RS0
DATA BUS
tPWL
tAS tAH
tPWH
tDDR tDHR
RD
CS, RS0
DATA BUS
tPWL
tAS tAH
tPWH
tDSW tDHW
4-11
MT8870D/MT8870D-1Integrated DTMF Receiver
Features• Complete DTMF Receiver
• Low power consumption
• Internal gain setting amplifier
• Adjustable guard time
• Central office quality
• Power-down mode
• Inhibit mode
• Backward compatible withMT8870C/MT8870C-1
Applications• Receiver system for British Telecom (BT) or
CEPT Spec (MT8870D-1)
• Paging systems
• Repeater systems/mobile radio
• Credit card systems
• Remote control
• Personal computers
• Telephone answering machine
Description
The MT8870D/MT8870D-1 is a complete DTMFreceiver integrating both the bandsplit filter anddigital decoder functions. The filter section usesswitched capacitor techniques for high and lowgroup filters; the decoder uses digital countingtechniques to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count isminimized by on chip provision of a differential inputamplifier, clock oscillator and latched three-state businterface.
3 3 GS Gain Select. Gives access to output of front end differential amplifier for connection offeedback resistor.
4 4 VRef Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 6and Fig. 10).
5 5 INH Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, Cand D. This pin input is internally pulled down.
6 6 PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. Thispin input is internally pulled down.
7 8 OSC1 Clock (Input) .
8 9 OSC2 Clock (Output) . A 3.579545 MHz crystal connected between pins OSC1 and OSC2completes the internal oscillator circuit.
9 10 VSS Ground (Input) . 0V typical.
10 11 TOE Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin ispulled up internally.
11-14
12-15
Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to thelast valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are highimpedance.
15 17 StD Delayed Steering (Output). Presents a logic high when a received tone-pair has beenregistered and the output latch updated; returns to logic low when the voltage on St/GT fallsbelow VTSt.
16 18 ESt Early Steering (Output). Presents a logic high once the digital algorithm has detected avalid tone pair (signal condition). Any momentary loss of signal condition will cause ESt toreturn to a logic low.
17 19 St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected atSt causes the device to register the detected tone pair and update the output latch. Avoltage less than VTSt frees the device to accept a new tone pair. The GT output acts toreset the external steering time-constant; its state is a function of ESt and the voltage on St.
18 20 VDD Positive power supply (Input) . +5V typical.
7,16
NC No Connection.
123456789 10
1817161514131211
IN+IN-GS
VRefINH
PWDNOSC1OSC2
VSS
VDDSt/GTEStStDQ4Q3Q2Q1TOE
18 PIN PLASTIC DIP/SOIC
123456789
10 1112
2019181716151413
IN+IN-GS
VRefINH
PWDNNC
OSC1OSC2
VSS
20 PIN SSOP
VDDSt/GTEStStD
Q4Q3Q2Q1TOE
NC
ISO2-CMOS MT8870D/MT8870D-1
4-13
Functional Description
The MT8870D/MT8870D-1 monolithic DTMFreceiver offers small size, low power consumptionand high performance. Its architecture consists of abandsplit filter section, which separates the high andlow group tones, followed by a digital countingsection which verifies the frequency and duration ofthe received tones before passing the correspondingcode to the output bus.
Filter Section
Separation of the low-group and high group tones isachieved by applying the DTMF signal to the inputsof two sixth-order switched capacitor bandpassfilters, the bandwidths of which correspond to the lowand high group frequencies. The filter section alsoincorporates notches at 350 and 440 Hz forexceptional dial tone rejection (see Figure 3). Eachfilter output is followed by a single order switchedcapacitor filter section which smooths the signalsprior to limiting. Limiting is performed by high-gaincomparators which are provided with hysteresis toprevent detection of unwanted low-level signals. Theoutputs of the comparators provide full rail logicswings at the frequencies of the incoming DTMFsignals.
Decoder Section
Following the filter section is a decoder employingdigital counting techniques to determine thefrequencies of the incoming tones and to verify thatthey correspond to standard DTMF frequencies. Acomplex averaging algorithm protects against tonesimulation by extraneous signals such as voice while
Figure 4 - Basic Steering Circuit
providing tolerance to small frequency deviationsand variations. This averaging algorithm has beendeveloped to ensure an optimum combination ofimmunity to talk-off and tolerance to the presence ofinterfering frequencies (third tones) and noise. Whenthe detector recognizes the presence of two validtones (this is referred to as the “signal condition” insome industry specifications) the “Early Steering”(ESt) output will go to an active state. Anysubsequent loss of signal condition will cause ESt toassume an inactive state (see “Steering Circuit”).
Steering Circuit
Before registration of a decoded tone pair, thereceiver checks for a valid signal duration (referred toas character recognition condition). This check isperformed by an external RC time constant driven byESt. A logic high on ESt causes vc (see Figure 4) torise as the capacitor discharges. Provided signal
condition is maintained (ESt remains high) for thevalidation period (tGTP), vc reaches the threshold(VTSt) of the steering logic to register the tone pair,latching its corresponding 4-bit code (see Table 1)into the output latch. At this point the GT output isactivated and drives vc to VDD. GT continues to drivehigh as long as ESt remains high. Finally, after ashort delay to allow the output latch to settle, thedelayed steering output flag (StD) goes high,signalling that a received tone pair has beenregistered. The contents of the output latch aremade available on the 4-bit output bus by raising thethree state control input (TOE) to a logic high. Thesteering circuit works in reverse to validate theinterdigit pause between signals. Thus, as well asrejecting signals too short to be considered valid, thereceiver will tolerate signal interruptions (dropout)too short to be considered a valid pause. This facility,together with the capability of selecting the steeringtime constants externally, allows the designer totailor performance to meet a wide variety of systemrequirements.
Guard Time Adjustment
In many situations not requiring selection of toneduration and interdigital pause, the simple steeringcircuit shown in Figure 4 is applicable. Componentvalues are chosen according to the formula:
tREC=tDP+tGTPtID=tDA+tGTA
The value of tDP is a device parameter (see Figure11) and tREC is the minimum signal duration to berecognized by the receiver. A value for C of 0.1 µF is
recommended for most applications, leaving R to beselected by the designer.
Different steering arrangements may be used toselect independently the guard times for tonepresent (tGTP) and tone absent (tGTA). This may benecessary to meet system specifications which placeboth accept and reject limits on both tone durationand interdigital pause. Guard time adjustment alsoallows the designer to tailor system parameterssuch as talk off and noise immunity. Increasing tRECimproves talk-off performance since it reduces theprobability that tones simulated by speech willmaintain signal condition long enough to beregistered. Alternatively, a relatively short tREC witha long tDO would be appropriate for extremely noisyenvironments where fast acquisition time andimmunity to tone drop-outs are required. Designinformation for guard time adjustment is shown inFigure 5.
VDD
St/GT
ESt
C1
R1 R2
a) decreasing tGTP; (tGTP<tGTA)
tGTP=(RPC1)In[VDD/(VDD-VTSt)]
tGTA=(R1C1)In(VDD/VTSt)
RP=(R1R2)/(R1+R2)
VDD
St/GT
ESt
C1
R1R2
tGTP=(R1C1)In[VDD/(VDD-VTSt)]
tGTA=(RPC1)In(VDD/VTSt)
RP=(R1R2)/(R1+R2)
b) decreasing tGTA; (tGTP>tGTA)
Digit TOE INH ESt Q4 Q3 Q2 Q1
ANY L X H Z Z Z Z
1 H X H 0 0 0 1
2 H X H 0 0 1 0
3 H X H 0 0 1 1
4 H X H 0 1 0 0
5 H X H 0 1 0 1
6 H X H 0 1 1 0
7 H X H 0 1 1 1
8 H X H 1 0 0 0
9 H X H 1 0 0 1
0 H X H 1 0 1 0
* H X H 1 0 1 1
# H X H 1 1 0 0
A H L H 1 1 0 1
B H L H 1 1 1 0
C H L H 1 1 1 1
D H L H 0 0 0 0
A H H Lundetected, the output codewill remain the same as theprevious detected code
B H H L
C H H L
D H H L
ISO2-CMOS MT8870D/MT8870D-1
4-15
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power downthe device to minimize the power consumption in astandby mode. It stops the oscillator and thefunctions of the filters.
Inhibit mode is enabled by a logic high input to thepin 5 (INH). It inhibits the detection of tonesrepresenting characters A, B, C, and D. The outputcode will remain the same as the previous detectedcode (see Table 1).
Differential Input Configuration
The input arrangement of the MT8870D/MT8870D-1provides a differential-input operational amplifier aswell as a bias source (VRef) which is used to bias theinputs at mid-rail. Provision is made for connection ofa feedback resistor to the op-amp output (GS) foradjustment of gain. In a single-ended configuration,the input pins are connected as shown in Figure 10with the op-amp connected for unity gain and VRefbiasing the input at 1/2VDD. Figure 6 shows thedifferential configuration, which permits theadjustment of gain with the feedback resistor R5.
Crystal Oscillator
The internal clock circuit is completed with theaddition of an external 3.579545 MHz crystal and isnormally connected as shown in Figure 10 (Single-Ended Input Configuration). However, it is possible toconfigure several MT8870D/MT8870D-1 devicesemploying only a single oscillator crystal. Theoscillator output of the first device in the chain iscoupled through a 30 pF capacitor to the oscillatorinput (OSC1) of the next device. Subsequent devicesare connected in a similar fashion. Refer to Figure 7for details. The problems associated withunbalanced loading are not a concern with thearrangement shown, i.e., precision balancingcapacitors are not required.
All resistors are ±1% tolerance.All capacitors are ±5% tolerance.
R3=R2R5
R2+R5
VOLTAGE GAIN (Av diff)=R5
R1
INPUT IMPEDANCE
(ZINDIFF) = 2 R12+
1ωc
2
OSC1
OSC2
OSC2
OSC1
C
X-tal
C
To OSC1 of nextMT8870D/MT8870D-1
C=30 pFX-tal=3.579545 MHz
MT8870D/MT8870D-1 ISO2-CMOS
4-16
Applications
RECEIVER SYSTEM FOR BRITISH TELECOMSPEC POR 1151
The circuit shown in Fig. 9 illustrates the use ofMT8870D-1 device in a typical receiver system. BTSpec defines the input signals less than -34 dBm asthe non-operate level. This condition can be attainedby choosing a suitable values of R1 and R2 toprovide 3 dB attenuation, such that -34 dBm inputsignal will correspond to -37 dBm at the gain settingpin GS of MT8870D-1. As shown in the diagram, thecomponent values of R3 and C2 are the guard timerequirements when the total component tolerance is6%. For better performance, it is recommended touse the non-symmetric guard time circuit in Fig. 8.
† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.Derate above 75 °C at 16 mW / °C. All leads soldered to board.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings †
Parameter Symbol Min Max Units
1 DC Power Supply Voltage VDD 7 V
2 Voltage on any pin VI VSS-0.3 VDD+0.3 V
3 Current at any pin (other than supply) II 10 mA
4 Storage temperature TSTG -65 +150 °C
5 Package power dissipation PD 500 mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter Sym Min Typ ‡ Max Units Test Conditions
1 DC Power Supply Voltage VDD 4.75 5.0 5.25 V
2 Operating Temperature TO -40 +85 °C
3 Crystal/Clock Frequency fc 3.579545 MHz
4 Crystal/Clock Freq.Tolerance ∆fc ±0.1 %
DC Electrical Characteristics - VDD=5.0V± 5%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.
Characteristics Sym Min Typ ‡ Max Units Test Conditions
1 SUPPLY
Standby supply current IDDQ 10 25 µA PWDN=VDD
2 Operating supply current IDD 3.0 9.0 mA
3 Power consumption PO 15 mW fc=3.579545 MHz
4
INPUTS
High level input VIH 3.5 V VDD=5.0V
5 Low level input voltage VIL 1.5 V VDD=5.0V
6 Input leakage current IIH/IIL 0.1 µA VIN=VSS or VDD
7 Pull up (source) current ISO 7.5 20 µA TOE (pin 10)=0,VDD=5.0V
8 Pull down (sink) current ISI 15 45 µA INH=5.0V, PWDN=5.0V,VDD=5.0V
9 Input impedance (IN+, IN-) RIN 10 MΩ @ 1 kHz
10 Steering threshold voltage VTSt 2.2 2.4 2.5 V VDD = 5.0V
11
OUTPUTS
Low level output voltage VOL VSS+0.03 V No load
12 High level output voltage VOH VDD-0.03 V No load
13 Output low (sink) current IOL 1.0 2.5 mA VOUT=0.4 V
14 Output high (source) current IOH 0.4 0.8 mA VOUT=4.6 V
15 VRef output voltage VRef 2.3 2.5 2.7 V No load, VDD = 5.0V
16 VRef output resistance ROR 1 kΩ
MT8870D/MT8870D-1 ISO2-CMOS
4-18
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones. 3. Tone duration= 40 ms, tone pause= 40 ms. 4. Signal condition consists of nominal DTMF frequencies. 5. Both tones in composite signal have an equal amplitude. 6. Tone pair is deviated by ±1.5 %± 2 Hz. 7. Bandwidth limited (3 kHz ) Gaussian noise. 8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %. 9. For an error rate of better than 1 in 10,000.10. Referenced to lowest level frequency component in DTMF signal.11. Referenced to the minimum valid accept level.12. Guaranteed by design and characterization.
Characteristics Sym Min Typ ‡ Max Units Test Conditions
1 Input leakage current IIN 100 nA VSS ≤ VIN ≤ VDD
2 Input resistance RIN 10 MΩ
3 Input offset voltage VOS 25 mV
4 Power supply rejection PSRR 50 dB 1 kHz
5 Common mode rejection CMRR 40 dB 0.75 V ≤ VIN ≤ 4.25 V biasedat VRef =2.5 V
6 DC open loop voltage gain AVOL 32 dB
7 Unity gain bandwidth fC 0.30 MHz
8 Output voltage swing VO 4.0 Vpp Load ≥ 100 kΩ to VSS @ GS
9 Maximum capacitive load (GS) CL 100 pF
10 Resistive load (GS) RL 50 kΩ
11 Common mode range VCM 2.5 Vpp No Load
MT8870D AC Electrical Characteristics - VDD=5.0V ±5%, VSS=0V, -40°C ≤ TO ≤ +85°C , using Test Circuit shown in
Figure 10.
Characteristics Sym Min Typ ‡ Max Units Notes*
1Valid input signal levels (eachtone of composite signal)
-29 +1 dBm 1,2,3,5,6,9
27.5 869 mVRMS 1,2,3,5,6,9
2 Negative twist accept 8 dB 2,3,6,9,12
3 Positive twist accept 8 dB 2,3,6,9,12
4 Frequency deviation accept ±1.5% ± 2 Hz 2,3,5,9
5 Frequency deviation reject ±3.5% 2,3,5,9
6 Third tone tolerance -16 dB 2,3,4,5,9,10
7 Noise tolerance -12 dB 2,3,4,5,7,9,10
8 Dial tone tolerance +22 dB 2,3,4,5,8,9,11
ISO2-CMOS MT8870D/MT8870D-1
4-19
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.2. Digit sequence consists of all DTMF tones.3. Tone duration= 40 ms, tone pause= 40 ms.4. Signal condition consists of nominal DTMF frequencies.5. Both tones in composite signal have an equal amplitude.6. Tone pair is deviated by ±1.5 %± 2 Hz.7. Bandwidth limited (3 kHz ) Gaussian noise.8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.9. For an error rate of better than 1 in 10,000.10. Referenced to lowest level frequency component in DTMF signal.11. Referenced to the minimum valid accept level.12. Referenced to Fig. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz.13. Guaranteed by design and characterization.
MT8870D-1 AC Electrical Characteristics - VDD=5.0V±5%, VSS=0V, -40°C ≤ TO ≤ +85°C , using Test Circuit shown
in Figure 10.
Characteristics Sym Min Typ ‡ Max Units Notes*
1Valid input signal levels (eachtone of composite signal)
-31 +1 dBm Tested at VDD=5.0V1,2,3,5,6,9
21.8 869 mVRMS
2 Input Signal Level Reject-37 dBm Tested at VDD=5.0V
1,2,3,5,6,910.9 mVRMS
3 Negative twist accept 8 dB 2,3,6,9,13
4 Positive twist accept 8 dB 2,3,6,9,13
5 Frequency deviation accept ±1.5%± 2 Hz 2,3,5,9
6 Frequency deviation reject ±3.5% 2,3,5,9
7 Third zone tolerance -18.5 dB 2,3,4,5,9,12
8 Noise tolerance -12 dB 2,3,4,5,7,9,10
9 Dial tone tolerance +22 dB 2,3,4,5,8,9,11
MT8870D/MT8870D-1 ISO2-CMOS
4-20
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
*NOTES:1. Used for guard-time calculation purposes only.2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high.
Figure 10 - Single-Ended Input Configuration
AC Electrical Characteristics - VDD=5.0V±5%, VSS=0V, -40°C ≤ To ≤ +85°C , using Test Circuit shown in Figure 10.
Characteristics Sym Min Typ ‡ Max Units Conditions
CD4514BC• CD4515BC4-Bit Latched/4-to-16 Line Decoders
General DescriptionThe CD4514BC and CD4515BC are 4-to-16 line decoderswith latched inputs implemented with complementary MOS(CMOS) circuits constructed with N- and P-channelenhancement mode transistors. These circuits are prima-rily used in decoding applications where low power dissipa-tion and/or high noise immunity is required.
The CD4514BC (output active high option) presents a logi-cal “1” at the selected output, whereas the CD4515BC pre-sents a logical “0” at the selected output. The input latchesare R–S type flip-flops, which hold the last input data pre-sented prior to the strobe transition from “1” to “0”. Thisinput data is decoded and the corresponding output is acti-vated. An output inhibit line is also available.
Features Wide supply voltage range: 3.0V to 15V
High noise immunity: 0.45 VDD (typ.)
Low power TTL: fan out of 2
compatibility: driving 74L
Low quiescent power dissipation:0.025 µW/package @ 5.0 VDC
Single supply operation
Input impedance = 1012Ω typically
Plug-in replacement for MC14514, MC14515
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Note 1: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed. Except for “Operating Tempera-ture Range” they are not meant to imply that the devices should be oper-ated at these limits. The tables of “Recommended Operating Conditions”and “Electrical Characteristics” provide conditions for actual device opera-tion.
Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 2)CD4514BC, CD4515BC
Note 3: IOH and IOL are tested one output at a time.
DC Supply Voltage (VDD) −0.5V to +18V
Input Voltage (VIN) −0.5V to VDD + 0.5V
Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260°C
DC Supply Voltage (VDD) 3V to 15V
Input Voltage (VIN) 0V to VDD
Operating Temperature Range (TA)
CD4514BC, CD4515BC −40°C to +85°C
Symbol Parameter Conditions −40°C +25°C +85°C
Units Min Max Min Typ Max Min Max
IDD Quiescent Device VDD = 5V, VIN = VDD or V SS 20 0.005 20 150 µA
Current VDD = 10V, VIN = VDD or V SS 40 0.010 40 300 µA
VDD = 15V, VIN = VDD or V SS 80 0.015 80 600 µA
VOL LOW Level VIL = 0V, VIH = VDD,
Output Voltage |IO| < 1 µA
VDD = 5V 0.05 0 0.05 0.05 V
VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
VOH HIGH Level VIL = 0V, VIH = VDD,
Output Voltage |IO| < 1 µA
VDD = 5V 4.95 4.95 5.0 4.95 V
VDD = 10V 9.95 9.95 10.0 9.95 V
VDD = 15V 14.95 14.95 15.0 14.95 V
VIL LOW Level |IO| < 1 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 V
VDD = 10V, VO = 1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH HIGH Level |IO| < 1 µA
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 V
VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
Current (Note 3) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.90 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
Current (Note 3) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.90 mA
CPD Power Dissipation Capacitance Per Package (Note 5) 150 pF
CIN Input Capacitance Any Input (Note 6) 5 7.5 pF
5-59
FAST AND LS TTL DATA
BCD TO 7-SEGMENTDECODER
The SN54 /74LS48 is a BCD to 7-Segment Decoder consisting of NANDgates, input buffers and seven AND-OR-INVERT gates. Seven NAND gatesand one driver are connected in pairs to make BCD data and its complementavailable to the seven decoding AND-OR-INVERT gates. The remainingNAND gate and three input buffers provide lamp test, blanking input/ripple-blanking input for the LS48.
The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending onthe state of the auxiliary inputs, decodes this data to drive other components.The relative positive logic output levels, as well as conditions required at theauxiliary inputs, are shown in the truth tables.
The LS48 circuit incorporates automatic leading and/or trailing edgezero-blanking control (RBI and RBO). Lamp Test (LT) may be activated anytime when the BI /RBO node is HIGH. Both devices contain an overridingblanking input (BI) which can be used to control the lamp intensity by varyingthe frequency and duty cycle of the BI input signal or to inhibit the outputs.• Lamp Intensity Modulation Capability (BI/RBO)• Internal Pull-Ups Eliminate Need for External Resistors• Input Clamp Diodes Eliminate High-Speed Termination Effects
14 13 12 11 10 9
1 2 3 4 5 6
VCC
7
16 15
8
f g a b c d e
B C LT BI / RBO RBI D A GND
CONNECTION DIAGRAM DIP (TOP VIEW)
LOGIC DIAGRAM
INPUT
BLANKING INPUT ORRIPPLE-BLANKINGOUTPUT
RIPPLE-BLANKINGINPUT
LAMP-TESTINPUT
A
B
C
D
a
b
c
d
e
f
g
OUTPUT
SN54/74LS48
BCD TO 7-SEGMENTDECODER
LOW POWER SCHOTTKY
J SUFFIXCERAMIC
CASE 620-09
N SUFFIXPLASTIC
CASE 648-08
161
16
1
ORDERING INFORMATION
SN54LSXXJ CeramicSN74LSXXN PlasticSN74LSXXD SOIC
161
D SUFFIXSOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16GND = PIN 8
7 1 2 6 3 5
13 12 11 10 9 15 14 4
A B C D LT RBI
a b c d e f gBI/RBO
SN54/74LS48
14 15
NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS
0 1 2 3 4 5 6 7 8 9 10 11 12 13
NOTES:(1) BI/RBO is wired-AND logic serving as blanking input (BI) and/or
ripple-blanking output (RBO). The blanking out (BI) must be openor held at a HIGH level when output functions 0 through 15 aredesired, and ripple-blanking input (RBI) must be open or at a HIGHlevel if blanking of a decimal 0 is not desired. X=input may be HIGHor LOW.
(2) When a LOW level is applied to the blanking input (forced condition)all segment outputs go to a LOW level, regardless of the state of anyother input condition.
(3) When ripple-blanking input (RBI) and inputs A, B, C, and D are atLOW level, with the lamp test input at HIGH level, all segmentoutputs go to a HIGH level and the ripple-blanking output (RBO)goes to a LOW level (response condition).
(4) When the blanking input/ripple-blanking output (BI/RBO) is open orheld at a HIGH level, and a LOW level is applied to lamp-test input,all segment outputs go to a LOW level.
NOTES:a) Unit Load (U.L.) = 40 µA HIGH/ 1.6 mA LOWb) Outut current measured at VOUT = 0.5 V
Output LOW drive factor is SN54LS / 74LS48: 1.25 U.L. for Military (54), 3.75 U.L. for Commercial (74).
DECIMALOR
FUNCTIONLT RBI D C B A BI / RBO a b c d e f g NOTE
0 H H L L L L H H H H H H H L 1
1 H X L L L H H L H H L L L L 1
2 H X L L H L H H H L H H L H
3 H X L L H H H H H H H L L H
4 H X L H L L H L H H L L H H
5 H X L H L H H H L H H L H H
6 H X L H H L H L L H H H H H
7 H X L H H H H H H H L L L L
8 H X H L L L H H H H H H H H
9 H X H L L H H H H H L L H H
10 H X H L H L H L L L H H L H
11 H X H L H H H L L H H L L H
12 H X H H L L H L H L L L H H
13 H X H H L H H H L L H L H H
14 H X H H H L H L L L H H H H
15 H X H H H H H L L L L L L L
BI X X X X X X L L L L L L L L 2
RBI H L L L L L L L L L L L L L 3
LT L X X X X X H H H H H H H H 4
5-61
FAST AND LS TTL DATA
SN54/74LS48
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 5474
4.54.75
5.05.0
5.55.25
V
TA Operating Ambient Temperature Range 5474
–550
2525
12570
°C
IOH Output Current — High a to g 54, 74 –100 µA
IOH Output Current — High BI /RBO 54, 74 –50 µA
IOL Output Current — Low a to g 5474
2.06.0
mA
IOL Output Current — Low BI /RBOBI /RBO
5474
1.63.2
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 VGuaranteed Input HIGH Voltage forAll Inputs
VIL Input LOW Voltage54 0.7
VGuaranteed Input LOW Voltage forAll InputsVIL Input LOW Voltage
74 0.8V
Guaranteed Input LOW Voltage forAll Inputs
VIK Input Clamp Diode Voltage –1.5 V VCC = MIN, IIN = –18 mA
VOH Output HIGH Voltage 2.4 4.2 µAVCC = MIN, IOH = –50 µA,VIN = VIH or U.L. per Truth TableVOH Output HIGH Voltage 2.4 4.2 µAVCC = MIN, IOH = –50 µA,VIN = VIH or U.L. per Truth Table
IO Output Current a to g –1.3 –2.0 mAVCC = MIN, VO = 0.85 VInput Conditioner as for VOH
VOL Output LOW Voltage a to g54, 74 0.4 V IOL = 2.0 mA VCC = MIN, VIH = 2.0 V
VIL = VIL MAXVOL Output LOW Voltage a to g74 0.5 V IOL = 6.0 mA
VCC = MIN, VIH = 2.0 VVIL = VIL MAX
VOLOutput LOW VoltageBI /RBO
54, 74 0.4 V IOL = 1.6 mA VCC = MAX, VIH = 2.0 VVIL = VIL MAXVOL
Output LOW VoltageBI /RBO 74 0.5 V IOL = 3.2 mA
VCC = MAX, VIH = 2.0 VVIL = VIL MAX
IIHInput HIGH Current(Except BI /RBO)
20 µA VCC = MAX, VIN = 2.7 VIIH
Input HIGH Current(Except BI /RBO) 0.1 mA VCC = MAX, VIN = 7.0 V
IILInput LOW Current(Except BI /RBO) –0.4 mA VCC = MAX, VIN = 0.4 V
IIL Input LOW Current BI/RBO –1.2 mA VCC = MAX, VIN = 0.4 V
ICC Power Supply Current 25 38 mA VCC = MAX
IOS Short Circuit Current BI/RBO (Note 1) –0.3 –2.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C)
Symbol Parameter
Limits
Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions
tPHLPropagation Delay Time, HIGH-to-LOWLevel Output from A Input
100 ns
CL = 15 pF, RL = 4.0 kΩtPLH
Propagation Delay Time, LOW-to-HIGHLevel Output from A Input
100 ns
CL = 15 pF, RL = 4.0 kΩ
tPHLPropagation Delay Time, HIGH-to-LOWLevel Output from RBI Input
100 ns
CL = 15 pF, RL = 6.0 kΩtPLH
Propagation Delay Time, LOW-to-HIGHLevel Output from RBI Input