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BY RAJESH

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INTRODUCTION

VHDL is a Hardware Description Language. Ovedr the years, HDLs have evolved to help electronic designers

in the following tasks -

a) Describing digital systems

b) Modeling digital systemsc) Designing digital systems

The VHDL language can be used with several goals in mind -

i) To synthesize digital circuits

ii) To verify and validate digital designs

iii) To generatetest vectors to test circuits

iv) To simulate circuits

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VHDL is an acronym of VHSIC Hardware DescriptionLanguage

VHSIC is an acronym of Very High Speed Integrated Circuits

It is founded by United States Department Of Defense in the

1980s.

VHDL-87 VHDL-93 IEEE-1076 IEEE-1164 VHDL describes the behavior of an electronic system,from which

we can attained the physical system.

It is intended for circuit simulation and synthesis.

It can be used for sequential behavior as well as concurrentbehavior.

It is strongly typed language.

The main application of VHDL are in FPGA,CPLDS, ASICS.

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CONCURRENCY

VHDL is a concurrent language????

This concurrency is achived by event driven simulation as VHDLis event driven.

This means that all components of design are executed

concurrently whenever there is a event on the ports of a

component. Here order of execution is not important.

The main concurrent body is architecture and other concurrent

blocks exist in the architecture.

Components instantiated within an architecture and all sub-blocksand subcomponents within this component are considered

concurrent

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Example

entity co_n is

Port ( a,b,c,d : in STD_LOGIC_VECTOR (3 downto 0);y : out STD_LOGIC_VECTOR (3 downto 0));

end co_n;

architecture Behavioral of co_n is

signal a1,a2,a3 : std_logic_vector(3 downto 0);

begin

a3

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SEQUENTIAL

Sequentiality refers to the statements that are executed one after another.

Here orde is important.

VHDL provides sequential bodies(process block,functions,procedures) withinwhich sequential statements are used.

The sequential bodies which describe sequential behavior are runs in parallelwith other sequential bodies.

The delta delay is an internal simulation time for VHDL simulator.

It hide us from the fact that assignments and processing are done sequentiallybut it make us to appear as if concurrent assignements are really doneconcurrently.

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BASIC DESIGN METHODOLOGY

Requirements

SimulateRTL Model

Gate-levelModel

Synthesize

Simulate Test Bench

ASIC or FPGA Place & Route

Timing

ModelSimulate

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CODE STRUCTURE

LIBRARY

ENTITY

ARCHITECTURE

Basic

VhdlCode

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FUNDAMENTAL PARTS OF LIBRARY

LIBRARY

PACKAGE

FUNCTIONS

PROCEDURES COMPONENTS

CONSTANTS

TYPES

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LIBRARYLibrary ieee;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_arith.all;

Use ieee.std_logic_signed.all;

Use ieee.std_logic_unsigned.all;

Libraries are repositories offrequently used design entities that wewish to share.

The library clause identifies a library we wish to access. Here the

library name is IEEE, but in practice it will probably map to some

directory on your local system. This directory will contain various design units that have been

compiled, e.g. a package (which contains definitions of types,

functions, or procedures to be shared by multiple application

developers (users).

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The use clause determines which package or design units in a

library will be used in the current design. e.g. in the above

description, the clause states that in library IEEE

there is a package named std_logic_1164 and that we can use all

the components defined in this package.

We need this package because the definition for the type

std_ulogic is in this package.

SYNTEX:

LIBRARY LIBRARY_NAME;

USE LIBRARY_NAME . PACKAGE_NAME.PACKAGE_PARTS

e.g-> ieee.std_logic_1164(from ieee library),

-> standard (from std library)

-> work (from work library)

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ENTITY

Output 1

Output 2

Output n

Input 1

Input 2

Input n

... ...

Entityname

This is a black box that implemented bythe statements in Architecture

It is the interface forcommunication amongdifferent modules /components and define

the signal port modes(INPUT and OUTPUT)

Entity name should be same

as the file name

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Entitydeclaration

describes the input/outputports of a module

entity name port names port mode (direction)

entity reg4 isport ( d0, d1, d2, d3, en, clk : inbit;

q0, q1, q2, q3 : outbit );end entity reg4;

reserved words

port type

punctuation

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ARCHITECTURE

An architecture defines a body for a component entity

An architecture body specifies a behavior between inputsand outputs

The architecture name is not the same as the componentname.

The architecture declaration part must be defined before firstbegin and can consist of, for example:

types

subprograms

components

signal declarations

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ARCHITECTUREChipA

B

C

D

EX

Y

Define functionality of the

chipX

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THEMODEOFTHEPORT

= in, out, inout, bufferin: Component only read the signal

out: Component only write to the signal

inout: Component read or write to the signal (bidirectional

signals)

buffer: Component write and read back the signal (nobidirectional signals, the signal is going out from thecomponent)

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DATA TYPES bit values: '0', '1'

boolean values: TRUE, FALSE

integer values: -(231) to +(231 - 1)

std_logic values: 'U','X','1','0','Z','W','H','L','-'

U' = uninitialized

'X' = unknown'W' = weak 'X

'Z' = floating

'H'/'L' = weak '1'/'0

'-' = don't care

Std_logic_vector (n downto 0);

Std_logic_vector (0 upto n);

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DESIGN DESCRIPTION METHODS

Structural Description Method:expresses the design as an

arrangement of interconnected components It is basically schematic

Behavioral Description Method:describes the functionalbehavior of a hardware design in terms of circuits

The hardware behavior is described algorithmically No architecture is required here

Data-Flow Description Method:is similar to a register-transfer language

This method describes the function of a design by defining theflow of information from one input or register to another registeror output

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DATAFLOWCODE

Dataflow code is also called concurrent code.

It refers the statements which are declared outside theprocesses,functions or procedures.

They are when statement (when/else,with/select/when,

generate statement(for , if), blocks (simple block,and

guarded block).

Other and unaffected(when no action takes place) keyword.

Syntex :

->When /else : assign when condition else.;

-> with/select/when: with identifier select

assignement when value,

;

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If generate/for generate:

label1: for identifer in range generate

label2 : if condition generate

(concurrent assignements)

end generate;

end generate;

o

Simple block /Guarded blocko Simple block is self contained within the main code.It is

locally partioning the code.

syntex: label:block

{declarative part}begin

{concurrent statements}

end block label;

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Guarded block : It is a special kind of block.It includes aguarded expression. A guarded statements in guardedblock is executed only when the guard epression is true.

It can be used to construct sequential circuits.

Syntex :

label: block (guard expression){declarative part }

begin

{ concurrent guarded and unguarded statements}

end block label;

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SEQUENTIALCODE Sequential code is also called behavioral code.

Processes, functions and procedures, are the only sections

of code that executed sequentially. Sequntial code can be used to build both sequential circuits

as well as combinational circuits.

Process: it is characterized by the presence of IF ,WAIT,

CASE or LOOP and by a sensitivity list (except when wait isused)

-> it is executed every time a signal in the sensitivity listchanges.

syntex [label:] process (sensitivity list){variable declaration};

begin

{sequential code} ; end process[label] ;

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IF Syntex:

if condition then assignements ;

elsif condition then assignements;

else assignements;

end if;

WAIT:The waitstatements explicitly specify the conditions underwhich aprocess may resume execution after being suspended.

The forms of the wait statement include -

a) wait fortime expression;

b) wait onsignal;

c) wait untilcondition;d) wait;

Process should not have sensitivity list when wait empmoyed.

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Loop :

There are 2 kinds of loop statements, i) for loops, and ii) while

loops.

o for loop syntex:

-> [label:] for identifier in range loop

{sequential statements}

end loop;o while loop syntex:

-> [label:] for condition loop

{sequential statements}

end loop;

o EXIT : used for ending of loop.

Syntex : [label:] Exit [label] [when condition]

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NEXT : used for skipping loop steps.Syntex : [label:] next [loop_label] {when condition};

o CASE Syntex :

-> case identifier iswhen value => assignements ;

when value => assignements;

end case

-> OTHERS and NULL (when nonaction takes place)keyword.

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GENERIC Generic is useful to pass certain types of information (like rise and

fall delays, the size of the interface ports)

Generics declares a constant object of mode in (i.e the vlauecan only be read ) .

It can be used in the entity declaration and its corresponding

architecture bodies(component declaration , component

instantiation,configuration declaration , configuration specification. Syntex : generic (parameter_name:parameter_type :=

parameter_value);

e.g generic(n:integer := 8);

o Synetex for during component instantiations:comp-lb: comp_nm[generic map(generic- association-list)][port

map(port-associationlist)];

e.g a1:a_na generic map (6) port map(a,b,y);

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CONFIGURATION

Configurations are used to organize top-level entity in termsof lower level entites by specifying the bindings

between the entites.

o It is used to bind the desired architecture to the entity and a

component to the desired entity.o This binding is done in two ways:

By using a configuration specification( binding a componentto the desired entity).

By using a configuration declaration(binding an entity to thedesired architecture).

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CONFIGURATIONSPECIFICATION It binds a component to the desired entity(inside the

architecture).e.g component g

Port ( a : in STD_LOGIC;

y : out STD_LOGIC);

end component;

component hPort ( a,b : in STD_LOGIC;

y : out STD_LOGIC);

end component;

for n1:g use entity work.inv1 (behave);-- port map (a=>a,y =>y); // inv1 is an inverter, g is a buffer ,

for n2,n3,n4: h use entity work.nand_behave(behave); // nand_baheve is an nand , h is an and gate

signal sbar,asel,bsel: std_logic; // after binding g act as a inverter and h as a nand gate.

Begin

n1: g port map (sel,sbar);

n2: h port map (a,sbar,asel);

n3: h port map (b,sel,bsel);

n4: h port map (asel,bsel,y);

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CONFIGURATION DECLARATION

A configuration declaration is a seprate design unit.It is

declared outside the architecture body.

o It is used to bind the desired architecture to an entity orcomponent defined in the block(architecture body, generatestatement or block statement) to desired entity.

o One entity can have more than one configurationdeclaration.

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SUBPROGRAMS

It defines sequential algorithm that performs a certain

computation. It allows decomposition of large behaviors into modular

sections.

There are two types of subprogram:

Functions:-> it is used to return a single value by using return construct.

-> it executes in zero simulation time .

-> it is only used for combinational circuits.

-> its parameter restricted to mode inonly(only read)

Syntex : function function_name(parameter-list) return

return type.

e g

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e.g

function mux_2_1(x,y,s:in std_logic) return std_logic is

variable z : std_logic;

begin

case s is

when '0' => z := x;

when '1' => z := y;

when others => z := '0';

end case;

return z;

end mux_2_1;

begin

y(0)

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Procedures:

-> It is used to return zero or more then one value using

parameters mode out and inout .

-> It is used for both combinational and sequential circuits.

-> It may executes in non zero simulation time.

Syntex : procedure procedure-name (parameter-list); e.g procedure dff( signal a,clock,reset : in std_logic ;

signal o : out std_logic) is

begin

if(reset = '1')then

o

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UNDERSTANDING DELAYS An accurate representation of digital circuit behavior

requires an accurate modeling ofdelays thru thecomponents.

There are several delay models in VHDL, e.g. Inertial

Delay Model,Transport Delay Model, Delta Delay

Model.

a) The Inertial Delay Model

It takes a gate a finite amount of time and a certain

amount of energy for the outputof a gate to respondto

a change on the input.

This means that the change on the input has to persist for

a certain period of time to ensure that the output will

respond.

This propagation delay model is called the inertial delay model and

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This propagation delay model is called the inertialdelay model, and

is the default delay model for VHDL programs.

E.g Out1 is the output waveform for delay = 8 ns.

Out2 is the output waveform for delay = 2 ns.

If the gate delay is 8 ns, then any pulse on the input signal of

duration less than 8 ns will not be propagated to the output, e.g.

Out1.

If the gate delay is 2 ns, then since each pulse in the input waveform

is greater than 2 ns, it will be propagated to the output, e.g. Out2.

8 nsInput

Out1

Out2

5 10 15 20 25 30 35

2 ns

ORinput output

Syntex :

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Syntex :

signal

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