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VHDL
Prepared by:
Gaurav
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Outline..
Brief Overview of VHDL
Structural elements of VHDL Entity
Architecture
Signals
Data Types & Operator VHDL
Design Methodology Behavioral
Structural
Dataflow
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Brief Overview of VHDL
VHDL
... stands forVeryHighSpeedIntegratedCircuit
Hardware Description
Language
can be translated into an actual hardware implementation
allows complex digital circuits to be easily created In VHDL, strong understanding of your code is more important than
syntax & style.
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Structural Elements
Entity Interface
Example: Ports, I/O
Architecture
Implementation
Behavior
Function Vhdl model
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ENTITY
provides a name to the component
contains the port definitions in the interface list
can contain some generic definitions which can beused to override default values
entity identifierisgeneric interface_list;port interface_list;declarations
beginstatements
end [entity] [identifier];
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Example
And
a
b
c
1. entity and isport (a, b: in bit; c : out bit);
end and;
2. ENTITY and ISPORT( a, b : IN std_logic; c: OUT std_logic );
END and;
2 input And gate
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Architecture
encapsulates the behavior and timing information
contains a number of concurrent statements
there can be multiple architecture bodies for a given entity
architecture identifier ofentity_name is
declarations
begin
statements
end [architecture] [identifier];
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Example
And
a
b
c
architecture and_arch of and is;
begin;c
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Signals
Signals are intermediary ports within the architecture
represents wires and storage elements
Xor
And
And
Or
A
BC
And
sum
Carry
D
E
F
Circuit diagram of full adder
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Data Types
Data type
Scalar Type Composite Type Access Type File Type
Integer
Float
Physical
Enumeration
Record
Array
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Typical Operators
Logical OperatorsAND NOR NOTOR NANDXOR XNOR
Mathematical Operators+ Addition- Subtraction* Multiplication/ Division
Relational Operators= Equal/= Not Equal< Less than> Greater than
Operators
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DesignMethodology
Design Methodology
Dataflow Behavioral Structural
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Dataflow
Concurrent/ Continuously or Combinational Logic
To give a signal a concurrent assignment
SignalName
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Dataflow(cont.)
Xor
And
And
Or
A
B
Carry in(c _in)
And
Sum(s)
Carry out(c_out)
D
E
F
Circuit diagram of full adder
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Dataflow(cont.)
library ieee;
use ieee.std_logic_1164.all;
ENTITY fulladder IS
PORT ( a, b, c_in : IN BIT; s, c_out : OUT BIT);
END fulladder;
architecture fulladder_arch of fulladder is
begin
s
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Behavioral
The circuit is described by means of Boolean equations and
a set of sequential instructions.
4 x 1
a
d
b
c
s0 s1
x
Multiplexer 4 x 1
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Behavioral (cont.)
ENTITY mux ISPORT ( a, b, c, d : IN BIT;
s0, s1 : IN BIT;x, : OUT BIT);
END mux;
ARCHITECTURE sequential OF mux ISProcess (a, b, c, d, s0, s1 )VARIABLE sel : INTEGER;BEGINIF s0 = 0 and s1 = 0 THENsel := 0;ELSIF s0 = 1 and s1 = 0 THENsel := 1;ELSIF s0 = 0 and s1 = 0 THENsel := 2;ELSEsel := 3;END IF;
CASE sel ISWHEN 0 =>x x x x
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Structural The circuit is described as an interconnection of known
components.
xor
and
A
B
sum
carry
Half Adder 1 Half Adder 2
Or
sum
Carryout
A
B
Carry in
Half adder
Full adder using half adder
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Structural (cont.)HALF ADDER (USED FOR FULL ADDER)library ieee;
use ieee.std_logic_1164.all;entity HA isport(a,b:in std_logic;s,c:out std_logic);end HA;architecture dataflow of HA isbegins
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Structural (cont.)
--STRURAL DESCRIPTION OF FULL ADDER
library ieee;use ieee.std_logic_1164.all;entity FA isport(x, y, ci :in std_logic;sum,co:out std_logic);end FA;
architecture struct of FA iscomponent HA port(a, b: in std_logic;s, c:out std_logic);end component;component OR2 port(i1,i2:in std_logic;o:out std_logic);end component;signal s1,c1,c2:std_logic;begin
HA1:HA port map(x ,y ,s1 ,c1);HA2:HA port map(s1,ci,sum ,c2);ORG:OR2 port map(c1,c2,co);
end struct;
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Advantages of VHDL
1. Standard language2. Concurrent & sequential statement processing3. No standard methodology
4. Man machine readable documentation5. Versatile design support
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References
[1] Douglas L. Perry, VHDL: programming by example,
McGraw-Hill, New York, 2002, Fourth Edition.
[2] Wai-Kai Chen, The VLSI Handbook , CRC Press,
USA, Second Edition. [3] Dr. Cecil alford tsai chi huang, Digital design vhdl
laboratory notes, 1996, version 1.01,
[4] http://en.wikipedia.org/wiki/Very-large-
scale_integration [5] 1076 IEEE Standard VHDL Language Reference
Manual
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