VHDL

UNIVERSITY INSTITUTE OF ENGINEERING & TECHNOLOGY

KURUKSHETRA UNIVERSITY KURUKSHETRA

VHDLPRACTICAL FILE

SUBMITTED TO:- SUBMITTED BY:-

Ms. Bharti Mahajan Praveen Kumar

Roll No. 2507130

ECE ‘B’ 6th

SEM.

INDEX

Sr No.

Name of Experiment Date Signature &

Remarks

1. Write a VHDL Program to implement a 3 :8 decoder. March 2, 2010

2.Write a VHDL Program to implement a

8:1 multiplexer using behavioral modeling.

March 9,2010

3. Write a VHDL Program to implement a 1 :8 demultiplexer using behavioral

modeling.

March 16,2010

4. Write a VHDL Program to implement 4 bit addition/subtraction.

March 23, 2010

5. Write a VHDL Program to implement 4 bit comparator. April 6, 2010

6. Write a VHDL Program to generate Mod- 10 up counter. April 13, 2010

7. Write a program to design a 8 bit ALU

containing 8 arithmetic & 8 logic operations.

April 27, 2010

8. Write a VHDL Program to implement a 12X8 RAM. May 4,2010

9. Write a program to perform parallel

to serial transfer of 4 bit binary number.

May 11,2010

EXPERIMENT—1.

EXPERIMENT:- Write a VHDL program to implement a 3:8 Decoder.

Decoder signals

Output waves of Decoder

EXPERIMENT –2.

EXPERIMENT:-

Write a VHDL Program to implement a 8:1 multiplexer using behavioral

modeling.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2 is

Port ( X : in STD_LOGIC_VECTOR (0 TO 7);

S : in STD_LOGIC_VECTOR (0 TO 2);

Y : out STD_LOGIC);

end mux2;

architecture Behavioral of mux2 is

begin

PROCESS (S,X)

BEGIN

CASE S IS

WHEN "000" => Y<= X(0) AFTER 10 NS;

WHEN "001" => Y<= X(1) AFTER 10 NS;

WHEN "010" => Y<= X(2) AFTER 10 NS;

WHEN "011" => Y<= X(3) AFTER 10 NS;

WHEN "100" => Y<= X(4) AFTER 10 NS;

WHEN "101" => Y<= X(5) AFTER 10 NS;

WHEN "110" => Y<= X(6) AFTER 10 NS;

WHEN "111" => Y<= X(7) AFTER 10 NS;

WHEN OTHERS => Y<= 'Z' AFTER 10 NS;

END CASE;

END PROCESS;

end Behavioral;

Multiplexer Signals

Output Waves of Multiplexer

EXPERIMENT—3.EXPERIMENT:-

Write a VHDL Program to implement a 1:8 Demultiplexer using Behaviour modeling.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dmux1 is Port ( X : in STD_LOGIC; S : in STD_LOGIC_VECTOR(0 TO 2); Y : out STD_LOGIC_VECTOR(0 TO 7));end dmux1;

architecture Behavioral of dmux1 isbegin

process (S,X)begin

CASE S isWHEN "000" => Y(0)<= X AFTER 10 NS;WHEN "001" => Y(1)<= X AFTER 10 NS;WHEN "010" => Y(2)<= X AFTER 10 NS;WHEN "011" => Y(3)<= X AFTER 10 NS;WHEN "100" => Y(4)<= X AFTER 10 NS;WHEN "101" => Y(5)<= X AFTER 10 NS;WHEN "110" => Y(6)<= X AFTER 10 NS;WHEN "111" => Y(7)<= X AFTER 10 NS;WHEN OTHERS Y( 0 TO 7) <= “ZZZZZZZZ”;

END CASE;

END PROCESS;

end Behavioral;

Demultiplexer Signals

Output Waves of Demultiplexer

EXPERIMENT—4.EXPERIMENT:-

Write a VHDL Program to implement a 4 bit addition/subtraction.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

PACKAGE my_package ISCONSTANT ADDER_WIDTH : integer := 5;CONSTANT RESULT_WIDTH : integer := 6;

SUBTYPE ADDER_VALUE IS integer RANGE 0 TO 2 ** ADDER_WIDTH - 1;SUBTYPE RESULT_VALUE IS integer RANGE 0 TO 2 ** RESULT_WIDTH - 1;

END my_package;

LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE work.my_package.ALL;

ENTITY addsub ISPORT (a: IN ADDER_VALUE;

b: IN ADDER_VALUE;addnsub: IN STD_LOGIC;result: OUT RESULT_VALUE );

END addsub;

ARCHITECTURE rtl OF addsub ISBEGIN

PROCESS (a, b, addnsub)BEGIN

IF (addnsub = '1') THENresult <= a + b;

ELSEresult <= a - b;

END IF; END PROCESS;END rtl;

Adder and Subtractor Signals

Output Waves of Adder and Subtractor

EXPERIMENT—5.EXPERIMENT:-

Write a VHDL Program to implement a 4 bit comparator.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Comparator is

GENERIC (n: natural :=2);PORT (A: in std_logic_vector (n-1 downto 0);

B: in std_logic_vector (n-1 downto 0);less: out std_logic;equal: out std_logic;greater: out std_logic );

END Comparator;

ARCHITECTURE behv OF Comparator IS

BEGIN PROCESS (A,B) BEGIN IF (A<B) THEN

less <= '1'; equal <= '0'; greater <= '0';ELSIF (A=B) THEN less <= '0'; equal <= '1'; greater <= '0';ELSE less <= '0'; equal <= '0'; greater <= '1';END IF;

END PROCESS;

END behv;

Comparator Signals

Output Waves of Comparator

EXPERIMENT—6.EXPERIMENT:-

Write a VHDL Program to generate Mod- 10 up counter.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Counter IS PORT (clk: in std_logic;

reset: in std_logic; q: out std_logic_vector(3 downto 0));

END Counter;

ARCHITECTURE Counter OF Counter IS BEGIN PROCESS (clk,reset) VARIABLE qtemp: std_logic_vector(3 downto 0); BEGIN IF reset='1' THEN qtemp:="0000"; ELSE if clk'event and clk='1' then if qtemp<9 then qtemp:=qtemp+1; else qtemp:="0000"; end if; end if; q<=qtemp; END IF; END PROCESS; END Counter;

Counter Signals

Output Waves of Counter

EXPERIMENT—7.EXPERIMENT:-

Write a VHDL Program to design a 8 bit ALU containing 8 arithmetic & 8 logic operations.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY alu8bit ISPORT ( a, b : in std_logic_vector (0 to 7);

s : in std_logic_vector(0 to 3);y : out std_logic_vector(0 to 7));

END alu8bit;

ARCHITECTURE Behavioral of alu8bit isSIGNAL arith, logic : std_logic_vector ( 0 to 7);

BEGINWITH s(0 to 2) SELECT

arith <= a when "000",a+1 when "001",a-1 when "010",b when "011",b+1 when "100",b-1 when "101",a-b when "110",a+b when others;

WITH s(0 to 2) SELECTlogic <= not a when "000",

not b when "001",a and b when "010",a or b when "011",a nand b when "100",a nor b when "101",a xor b when "110",not ( a xor b) when others;

WITH s(3) SELECT y <= arith when '0',

logic when others;

END Behavioral;

8 Bit ALU Signals

Output Waves of 8 Bit ALU

EXPERIMENT—8.EXPERIMENT:-

Write a VHDL Program to implement a 12X8 RAM.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ram is

GENERIC ( bits : integer := 8;

words : integer :=16);

PORT ( wr_en, clk : in std_logic;

add : in integer range 0 to words-1;

data : in std_logic_vector (bits-1 downto 0);

dout : out std_logic_vector( 0 to bits-1));

END ram;

ARCHITECTURE Behavioral of ram is

TYPE vector_array is ARRAY ( 0 to words-1) of

std_logic_vector ( bits-1 downto 0);

SIGNAL memory : vector_array;

BEGIN

process ( clk, wr_en)

begin

IF (wr_en='1' ) then

IF ( clk'event and clk ='1') then

memory(add) <= data;

END IF;

END IF;

END PROCESS;

dout <= memory(add);

END Behavioral;

RAM Signals

Output Waves of RAM

EXPERIMENT—9.EXPERIMENT:-

Write a program to perform parallel to serial transfer of 4 bit binary number.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;