Vhdl

MODELLING OF DIGITAL SYSTEMS USING VHDL

REFERENCE BOOKS1.VHDL third Edition by DOUCLAS PERRY2.The Designers Guide to VHDL by ASHEHDEN.P.J3.VHDL Programming with Advanced Topics by JOHN WILEY and SON.4.VHDL Features and Applications By BHASKER.5.VHDL Analysis and Modelling of Digital Systems By NAVABI.6.VHDL by LIPSETT.7.VHDL Primer By J.BHASKER .

WHAT IS VHDL?

VHDL-VHSIC Hardware Description Language

VHSIC-Very High Speed Integrated Circuits digital system at many levels of abstraction The complexity of the digital circuit

described hierarchically.

HISTORY

REQUIREMENT FOR THE LANGUAGE (YEAR OF 1983)

VHIC CHIPS FOR DoD. DIFFERENT HDL IN COMPANIES. DIFFERENT VENDOR COULD NOT

EFFECTIVELY EXCHANGE DESIGNS . BIG ISSUE OF REPROCUREMENTAND

REUSE.

STANDARDIZED HDL

IN 1983 A TEAM OF THREE COMPANIES (IBM,TEXAS INSTRUMENTS AND INTERMETRICS) DEVELOP A VERSION OF LANGUAGE

IN 1985 VERSION 7.2 OF VHDL. IN 1986 LANGUAGE WAS TRANSFERRED TO THE

“IEEE” IN 1987 IEEE STANDARDIZED THE LANGUAGE. THIS VERSION KNOWN AS “IEEE Std 1076-1987”

RECOGNIZED AS ANSI

IN 1988 VHDL HAS BEEN RECOGNIZED AS AN American National Standards Institute standard.

IEEE RULES EVERY 5 YEARS ONCE HAS TO BE REBALLOTED.

STANDARD PACKAGE

In 1987, a great need for a standard package Different vendors supported different packages on

their system. Some of logic values were 46-value logic,7-value

logic,4-value logic and so on. A committee was set up to standardize the out come of the committee is “9-value logic

package”. Called “STD_LOGIC_1164” IEEE standard “IEEE Std 1164-1993”.

CAPABILITIES(1)

Used as Exchange media between vendors and CAD tool users.

Used as communication medium between different CAD and CAE tools.

Supports hierarchy. Supports flexible design . Not technology_specific but supporting

technology specific features.

CAPABILITIES(2)

Supports both synchronous and asynchronous timings.

Various digital modelling techniques(finite-state machine description,algorithmic description ,Boolean equation).

It is a publicly available ,human_readable,machine readable .

It is an IEEE and ANSI standard It supports three basic different description

styles:*structural;*dataflow;and *behavioural.

CAPABILITIES(3)

It supports a wide range of abstraction level

It has no limitations imposed by language. It has elements that make large scale design

modelling easier(components ,functions ,procedures and packages).

Test benches can be written using the same languages to test other VHDL models. Delays,timings and spike detection can be described very

naturally in this language

Hard ware abstraction. VHDL is used to describe a model for a

digital hard ware device. There are two views . Internal view –device specifies the

functionality of structure. External view-interface of the device

through which it communicates with the other models in its environment.

MODELISATION:From specification to language

SYNTHESIS:From language to circuit Language common to all levels of

abstraction Reduction in development cycle All codes are not synthesizable

LEVEL OF DESIGNCAPATURE

OBJECTS AND CONFIGURATION

PROCESS &VHDL CONNECTIVITY MODEL

*SECTION CONTAINING SEQUENTIAL STATEMENTS

*EXISTS INSIDE AN ARCHITECTURE

*MULTIPLE PROCESSES INTERACT CONCURRENT

BASIC TERMINOLOGY

VHDL provides five different types of primary constructs, called “DESIGN UNITS”.

1.Entity declaration. 2.Architecture body. 3.configuration declaration. 4.Package body declaration. 5.package body.

ENTITY DECLARATION

It specifies the name of the entity begin modelled and listed a set of interface ports.

Ports are signals through which the entity communicates with other models in its external environments.

ENTITY DECLARATION

Entity half_add is Port ( A,B: in BIT; SUM,CARRY: out BIT );End half_add;

ARCHITECTURE BODY

The internal details specified by an architecture body using the following modelling styles:

1.As a set of interconnected statements (to represent structure)2.As a set of concurrent assignment statements (to represent dataflow)3.As a set of sequential assignments statements (to represent behavior)4.As any combination of the above three

ARCHITECTURE BODY

(EXAMPLE_ structural style)Architecture ha_stru of half_add is Component xor2Port ( x,y:in BIT; z:out BIT; }; end component;Component and2Port (l,m:in BIT; n:out BIT);End component;Begin x1:xor2 port map(a,b,sum); a1:and2 port map(a,b.carry);End ha_stru;

ARCHITECTURE BODY(EXAMPLE_ dataflow style)

Architecture ha_stru of half_add is Begin SUM<=a xor b after 5 ns;CARRY<=a and b after 3 ns;End ha_stru;

ARCHITECTURE BODY(EXAMPLE_ behavioural style)

Architecture dec_sequential of decoders2x4 is BeginProcess (a,b,enable)Variable(Abar,Bbar:BIT);BeginAbar:=not a;Bbar:=not b;If enable=‘1’ thenZ(3)=not(a and b); Z(0)=not(Abar and Bbar); Z(2)=not(a and Bbar); Z(1)=not(Abar and b);Else Z<=“1111”; end if;End process;End dec_sequential;

BASIC LANGUAGE ELEMENTS

*IDENTIFIERS* DATA OBJECTS 1.CONSTANT DECLARATIONS 2.VARIABLE DECLARATIONS 3.SIGNAL DECLARATIONS 4.FILE DECLARATION

*DATA TYPE 1.SCALAR TYPES.(SUBTYPE,SCALAR T Y P E S E N U MERATION TYPES, FLOATING POINT TYPE,) 2.COMPOSITE TYPE(ARRAY TYPES,RECORD TY PE) 3.ACCESS TYPES. 4.FILE TYPE

5.INCOMPLETE TYPE 6.FILE TYPE.

BASIC LANGUAGE ELEMENTS

*IDENTIFIERS

BASIC LANGUAGE ELEMENTS

* DATA OBJECTS 1.CONSTANT DECLARATIONS 2.VARIABLE DECLARATIONS 3.SIGNAL DECLARATIONS 4.FILE DECLARATION

BASIC LANGUAGE ELEMENTS

DATA TYPE

1.SCALAR TYPES.(SUBTYPE,SCALARTYPE,E N U MERATION TYPES,

FLOATING POINT TYPE,)

2.COMPOSITE TYPE(ARRAY TYPES,RECORD TY PE,DIFFERENT TYPES.

3.ACCESS TYPES.

4.FILE TYPE

5.INCOMPLETE TYPE

6.FILE TYPE.

BASIC LANGUAGE ELEMENTS

OPERATORS

1.LOGICAL OPERATORS.

2.RELATIONAL OPERATORS.

3.SHIFT OPERATORS.

4.ARITHMETIC OPERATORS.

5.MULTIPLYING OPERATORS.

6.MISCELLANEOUS OPERATORS.

BASIC LANGUAGE BASIC LANGUAGE ELEMENTSELEMENTS

LOGICAL OPERATORS

AND OR NAND NOR XOR XNOR NOT

BASIC LANGUAGE BASIC LANGUAGE ELEMENTSELEMENTS

RELATIONAL OPERATORS

= /= < <= > >=

BASIC LANGUAGE BASIC LANGUAGE ELEMENTSELEMENTS

SHIFT OPERATORS

Sll srl sla sra rol ror

BASIC LANGUAGE BASIC LANGUAGE ELEMENTSELEMENTS

ADDING OPERATORS

+ - &

BASIC LANGUAGE BASIC LANGUAGE ELEMENTSELEMENTS

MULTIPLYING OPERATORS

* / mod rem

BEHAVIORAL MODELINGBEHAVIORAL MODELING 1.ENTITY DECLARATION2.ARCHITECTURE BODY3.PROCESS STATEMENT4.VARIABLE ASSIGNMENTS STATEMENT5.SIGNAL ASSIGNMENTS STATEMENT6.DELTA DELAY7.WAIT STATEMENTS8.IF STATEMENMT9.CASE STATEMENT10.NULL STATEMENT11.LOOP STATEMENT12.EXIT STATEMENT13.NEXT STATEMENT14.ASSERTION STATEMENTREPORT STATEMENT15.MORE ON SIGNAL ASSIGNMENT STATEMENT 16. DELAY MODEL 17.SIGNAL WAVEFORMS 18.SIGNAL DRIVERS19.MULTIPLE PROCESS20.POSTPONED PROCESSES

ENTITY DECLARATIONEntity entity_name is[generic(list of generics and their types); ][port (list of interface port names and their types);][entiity item declarations][begin Entity statements]End [entity][entity name];

INTERFACE PORT

In ,out, inout, buffer,linkage.

Entity inverter isPort ( a,b,c,d;in BIT; z:out BIT);End inverter;

Inverter circuit and its corresponding Entity declaration

A

BC

D

Z

ARCHITECTURE BODYARCHITECTURE BODY

*DESCRIBES THE INTERNAL OF THE AN ENTITY*DESCRIBES THE FUNCTIONALITY OF THE ENTITY

SYNTAX OF AN ARCHITECTURE BODY

ARCHITECTURE ARCHITECTURE NAME OF ENTITY NAME IS[ARCHITECTURE ITEM DECLATATIONS]BEGINCONCURRENT STATEMENTS;PROCESS STATEMENTS;BLOCK STATEMENTS;CONCURREMT PROCEDURAL CALL STATEMENTS;CONCURRENT ASSERTION STATEMENTS;CONCURRENT SIGNAL ASSIGNMENTS STATEMENTS;COMPONENT INSTANTIATION STATEMENTS;GENERATE STATEMENTS;END[ARCHITECTURE][ARCHITECTURE NAME];

ARCHITECTURE BODY

TO BE WRITEN

PROCESS STATEMENT [PROCESS LABLE:][PROCESS ][SENSITIVITY LIST][IS]

[PROCESS ITEM DECLARATIONS]BEGINSEQUENTIAL STATEMENTS VARIABLE ASSIGNMENTWAIT STATEMENTOF STATEMENTIF STATEMENTCASE STATEMENTLOOP STATEMENTNULL STATEMENTEXIT STATEMENTNEXT STATEMENTASSERTION STATEMENTREPORT STATEMENTPROCEDURE CAL;L STATEMENTRETURN STATEMENTEND PROCESS [PROCESS LABLE];

VARIABLE ASSIGNMENT VARIABLE ASSIGNMENT STATEMENTSTATEMENT

*VARIABLES CAN BE DECLARED AND USED INSIDE A PROCESS STATEMENT

SYNTAS OF VARIABLE ASSIGNMENT STATEMENT SYNTAS OF VARIABLE ASSIGNMENT STATEMENT

VARIABLE OBJECTS:=EXPRESSION;

EXAMBLE 1EXAMBLE 1PROCESS (A) VARIABLE EVENTS_A:INTEGER:=1;BEGIN EVENTS_A:=EVENTS_A+1;END PROCESS;

EXAMPLE 2EXAMPLE 2…………………SIGNAL A,Z:INTEGER;……………PZ:PROCESS(A)VARIABLE V1,V2:INTEGER;BEGIN V1:=A-V2; Z<=-V1; V2:=A+V1*2;END PROCESS PZ;

edges: process(in) variable count : integer := -1;begin count := count + 1;end process;

Compute_and : process(a, b)Begin Z <= a and b;End process;

rising: process(in) variable count : integer := -1;begin if in = ’1’ and in’last_value = ’0’ then count := count +1; end if;end process;

signal a,b,c : std_logic;…process(b)begin a <= b; c <= not a;end process;

…process(b)variable a,c : std_logic;begin a := b; c : not a;end process; 

-- 4-BIT ADDER--library IEEE;use IEEE.std_logic_1164.all; entity add is port ( a: in STD_LOGIC_VECTOR (0 to 3); b: in STD_LOGIC_VECTOR (0 to 3); carry: out STD_LOGIC; s: out STD_LOGIC_VECTOR (0 to 3));end add; architecture add_arch of add issignal c : std_logic_vector(0 to 4) ;beginc(0) <= '0'; process(a,b) begin for i in 0 to 3 loop s(i) <= a(i) xor b(i) xor c(i); c(i+1) <= (a(i) and b(i)) or ( a(i) and c(i) ) or ( b(i) and c(i) ) ; end loop; carry <= c(4); end process;end add_arch;

SIGNAL ASSIGNMENT STATEMENT

*SIGNALS ARE ASSIGNED VALUES USING A SIGNAL ASSIGNMENT STATEMENT*A SIGNAL ASSIGNMENT STATEMENT CAN APPEAR WITHIN A PROCESS OR OUTSIDE OF A PROCESS. INSIDE MEANSINSIDE MEANS,IT IS CONSIDERED TO BE A SEQUENTIAL SIGNAL ASSIGNMENT STATEMENT. OUTSIDE MEANSOUTSIDE MEANS,IT IS CONSIDERED TO BE A CONCURRENT SIGNAL ASSIGNMENT STATEMENT.

SYNTAX OF SIGNAL ASSIGNMENT STATEMENT

SIGNAL OBJECT<=EXPRESION[AFTER DELAY--VALUE];

DELAY

*A delta delay is a small delay.*It does not correspond to any real and actual simulation time does not advance.*This delay models hardware where a minimal amount of time is needed for a change to occur.*Delta delay allows for ordering of events that occur At the same simulation time during a simulation. *An event always occurs at a real sim,simulation time plus an integer multiple of delta delays.*For example ,event can occur at 15ns,15ns+1D,15ns+2D 15ns+3D… …. …. And so on.

DELAY WITH ONE EXAMPLE

WAIT STATEMENT *The WAIT statement provides an alternate way

to suspend the execution of process.*There are three basic forms of the WAIT statement. WAIT ONWAIT ON sensitivity list; sensitivity list; WAIT UNTILWAIT UNTIL Boolean expression; Boolean expression; WAIT FOR TIMEWAIT FOR TIME expression; expression;*They may be a combined in a signal WAIT statement.For example

WAIT ONWAIT ON sensitivity list sensitivity list UNTIL UNTIL Boolean expressionBoolean expression FORFOR time expression time expression

EXAMPLES OF WAIT STATEMENT

1.WAIT ON A,B,C;

2.WAIT UNTIL A-B;

3.WAIT FOR 10NS;

4.WAIT ON CLOCK FOR 20NS;

5.WAIT UNTIL SUM>100 FOR 50NS;

6.WAIT ON CLOCK UNTIL SUM>100;

WAIT FOR 0

*“WAIT FOR 0” MEANS TO WAIT FOR ONE DELTA CYCLE.*TS IS USEFUL WHEN WE WANT THE PROCESS TO BE DELAYED SO THAT DELTA DELAYED SIGNAL ASSIGNMENR WITHIN A PROCESS CAN TALK EFFECT.*FOR EXAMPLE

WAIT0:PROCESSBEGIN WAIT ON DATA; SIG_A<=DATA; WAIT FOR 0NS; SIG_B<=SIG_A;END PROCESS;

EFFECT OF “WAIT FOR 0 ns”EFFECT OF “WAIT FOR 0 ns”

IF STATEMENT

*AN IF STATEMENT SELECT A SEQUENCE OF STATEMENT *AN IF STATEMENT SELECT A SEQUENCE OF STATEMENT FOR EXECUTION BASED ON THE VALUE OF A CONDITION .FOR EXECUTION BASED ON THE VALUE OF A CONDITION .*THE CONDITION CAN BE ANY EXPRESSION THAT EVALUA*THE CONDITION CAN BE ANY EXPRESSION THAT EVALUA_TES TO A BOOLEAN VALUE._TES TO A BOOLEAN VALUE.

•GENERAL FORM OF AN IF STATEMENT GENERAL FORM OF AN IF STATEMENT

IF BOOLEAN EXPRESION THENIF BOOLEAN EXPRESION THEN SEQUENTIAL STATEMENT;SEQUENTIAL STATEMENT;[ELSIF BOOLEAN EXPRESSION THEN[ELSIF BOOLEAN EXPRESSION THEN SEQUENTIAL STATEMENT;SEQUENTIAL STATEMENT;[ELSE [ELSE SEQUENTIAL STATEMENT]SEQUENTIAL STATEMENT]END IF;END IF;

DESIGN FLOW

SEQUENTIAL INSTRUCTIONSEQUENTIAL INSTRUCTION

*If … Then… Else*If … Then… Else

*Case … When…*Case … When…

*For… Loop*For… Loop

*While … Loop *While … Loop

IF STATEMENT

*AN IF STATEMENT WELECT A SEQUENCE OF STATEMENT *AN IF STATEMENT WELECT A SEQUENCE OF STATEMENT FOR EXECUTION BASED ON THE VALUE OF A CONDITION .FOR EXECUTION BASED ON THE VALUE OF A CONDITION .*THE CONDITION CAN BE ANY EXPRESSION THAT EVALUA*THE CONDITION CAN BE ANY EXPRESSION THAT EVALUA_TES TO A BOOLEAN VALUE._TES TO A BOOLEAN VALUE.

•GENERAL FORM OF AN IF STATEMENT GENERAL FORM OF AN IF STATEMENT

IF BOOLEAN EXPRESION THENIF BOOLEAN EXPRESION THEN SEQUENTIAL STATEMENT;SEQUENTIAL STATEMENT;[ELSIF BOOLEAN EXPRESSION THEN[ELSIF BOOLEAN EXPRESSION THEN SEQUENTIAL STATEMENT;SEQUENTIAL STATEMENT;[ELSE [ELSE SEQUENTIAL STATEMENT]SEQUENTIAL STATEMENT]END IF;END IF;

If -- Synthesis Result

Example 1Process (a,b,c,s1,s2,s3,o)Begin

If s1=‘0’ then Y<=o;

Elsif s2=‘1’thenY<=b;

Elsif s3=‘0’then Y<=a;

Else Y<=c;

End if ; End process;

a

c

s3

s2s1

b

o

INSTRUCTION EQUIVALENT TO IF….THEN….ELSE

Y<=A when conditionBoolean else

B when conditionBoolean else

C;

**process is a must**process is a mustProcess Process Begin Begin

If condition 1 then y<=a If condition 1 then y<=a elsif condition2 y<=b elsif condition2 y<=b

Else y<=d; Else y<=d; End if; End if;

End process; End process;

CASE ….. END CASE

INSTRUCTION CASEINSTRUCTION CASE

CASE expression IS WHEN value 1=>……….. WHEN value 2=>………… WHEN value 3=>………… WHEN others=>……………END CASE;

(NO priority in the Case )

CASE =====SYNTHESIS

ARCHITECTURE a OF case_ex ISBEGINPROCESS(A,B,C,Z)BEGIN

CASE Y IS WHEN “0001”=>Z<= A; WHEN “0010”=>Z<=B; WHEN “0100”=>Z<=C; WHEN others=>Z<= C;END CASE;END PROCESS; END a;

**process is a must**process is a must

MUX

A

B

C

SEL

Z

FOR ……….LOOP

INSTRUCTION FOR…..FOR LOOPFOR I IN 1 TO 100 LOOP ………..SEQUENCE OF INSTRUCTIONSEND LOOP;

FOR …..LOOP must end with END LOOPIt is not necessary to declare the index i

For I in 1 to 100 loop Z(i):=i*I; End loop;

WHILE(A=‘1’) loop COUNT<=COUNT+1;

End loop;

FOR ……… LOOP FOR ……… LOOP

PROCESS (A,B)PROCESS (A,B)CONSTANT MUX_LIMIT:INTEGER:=25;CONSTANT MUX_LIMIT:INTEGER:=25;BEGINBEGIN

FOR I IN 0 TO MUX_LIMIT LOOPFOR I IN 0 TO MUX_LIMIT LOOP IF DONE(I)=TRUE THENIF DONE(I)=TRUE THEN NEXT;NEXT;

ELSE ELSE DONE(I):=TRUEDONE(I):=TRUEEND IF;END IF;Q(I)<=A(I) AND B(I);Q(I)<=A(I) AND B(I);END LOOP;END LOOP;END PROCESS;END PROCESS;

NEXT I IF THECONDITION IS TRUE

VARIABLE I IS NOT\DECLARED,IT IS VALUE ONLY DURING THE LIFE TIME OF THE LOOP

THE WHILE LOOP

Library IEEE;Use IEEE.Std_logic_1164.all;

Entity DEMUX is Port ( A:in integer range 0 to 3; Z:out std_ulogic_vector(3 down to 0);End DEMUX;

Architecture A of DEMUX is Begin process(A) variable I:integer range 0 to 3; beginZ<=“0000”

I:=0; While (I<=3)loop if(a =1) ten z(I)<=‘I’; end if; I:=I+1; end loop;End process;End A;

*THIS STATEMENT GENERALLY NOT SUPPORTED BY SYNTHESIS TOOL

NULL STATEMENT

*”NULL” STATEMENT IS A SEQUENTIAL STATEMENT.

*IT DOES NOT CAUSE ANY ACTION TO TA KE PLACE ;EXECUTION CONTINUOUS WITH THE NEXT STATEMENT.

Summary Slide

Summary Slide

EXIT STATEMENT*“EXIT ”STATEMENT IS A SEQUENTIAL STATEMENT CAN BE USED ONLY INSIDE A LOOP.

*THIS STATEMENT CAUSES EXECUTION TO JUMP OUT OF THE INNERMOST LOOP OR THE LOOP WHOSE LABLE IS SPECIFIED.

*THE SYNTAX FOR AN EXIT STATEMENT

exit[loop_label][when condition];

EXAMPLES FOR EXIT STATEMENT

SUM:=1;J:=0;J:=J+21;SUM:=SUM*10;

IF SUM>100 THEN EXIT L3;END IF ;END LOOP L3;

LOOP WAIT ON A,B; EXIT WHEN A=B;END LOOP;/* THIS LOOP BEHAVES EXACTILY LIKE THE WAIT STATEMENTWAIT UNTIL A=B;*/

ASSERTION STATEMENT

*USEFUL IN MODELING COSTRAINTS OF AN ENTITY.

*THE SYNTAX OF AN ASSERTION STATEMENT assert Boolean_expression [report string expression] [severity expression]*IF THE VALUE OF BOOLEAN EXPRESSION IS FALSE, THE REPORT MESSAGE IS PRINTED ALONG WITH THE SEVERITY LEVEL.*SEVERITY _LEVEL(A PREDEFINED ENUMERATION TYPE WITH VALUES “NOTE, WIRINING,ERROR AND FAILURE” )

REPORT STATEMENT

•It is similar to as assertion statement.•But without the assertion check.•A report statement can be used to display a message.•Syntax for report statement

Report string expression[severity expression];

MORE ON SINGAL ASSIGNMENT STATEMENT

*THIS DELAY OFTEN FOUND IN “SWITHCHING CIRCUIT”

*INPUTS VALUE MUST BE STABLE FOR A SPECIFIE D PULSE REJECTION LIMIT DURATION BEFORE THE VALUE IS ALLOWED TO PROPAGATE TO

THE OUTPUT .

*IN ADDITION, THE VALUE APPEARS AT THE OUTPUTAFTER THE SPECIFIED INERTIAL DELAY.

*IF THE INPUT IS NO STABLE FOR THE SPECIFIED LIMIT,NO OUTPUT CHANGE OCCURES.

*WHEN USED WITH SIGNAL ASSIGNMENTS, THE INPUT VALUE IS REPRESENTED BY THE VALUE OF EXPRESSION ON THE

RIGHT HAND SIDE AND THE OUTPUT IS REPRESENTED BY THE TARGET SIGNAL.

Syntax for intertial delay model

Signal-object<= [[reject pulse rejection limit] inertial ] expression after inertial_ delay_ value;

Example for inertial delay

Z<= A after 10 ns;Z<=inertial A after 10 ns;

TRANSPORT DELAY MODEL *THE DELAY S IN HARDWARE THAT DO NOT EXHIBIT ANY INERTIAL DELAY.*THIS DELAY REPRESENTS PURE PROPAGATION DELAY, THAT IS ANY CHANGES ON AN INPUT ARE TRANSPORTED TO THE OUTPUT, NO MATTER HOW SMALL, AFTER THE SPECIFIED DELAY. *

TRANSPORT DELAY MODEL *TO USE A TRANSPORT DELAY MODEL, THE KEY_ WORD transport MUST BE USED IN A SIGNAL ASSIGNMENT STATEMENT*Z<=transport A after 10 ns;

COMPARISION BETWEEN COMPARISION BETWEEN INERTIAL & TRANSPORTINERTIAL & TRANSPORT DELAY MODELS DELAY MODELS

INERTIAL DELAY

TRANSPORT DELAY

DESIGN FLOW*********************************

CREATING SIGNAL WAVEFORM

*IN ALL EXAMPLES OF SIGNAL ASSIGNMENT STATEMENTS THAT WE HAVE SEEN, WE HAVE ALWAYS ASSIGNED A SIGNAL VALUE TO SIGNAL;THIS NEED NOT BE SO.

*IT IS POSIBLE TO ASSIGN MULTIPLE VALUES TO A SIGNAL, EACH WITH A DIFFERENT DELAY.

*FOR EXAMPLE

PHASE1 <=‘0’,’1’ AFTER 8 ns,’0’ AFTER 13ns,’1‘ AFTER 50ns;

CREATING SIGNAL WAVEFORM

SYNTAX OF A SIGNAL ASSIGNMENT STATEMENT

Signal-object<=[transport][[reject pulse rejection limit]inertial]

waveform element, ,waveform_element ,

waveform element,waveform_element;

SINGAL DRIVERS

*A DRIVER IS CREATED FOR EVERY SIGNAL THAT IS ASSIGNED AS A VALUE IN A PROCESS.

*THE DRIVER IS CREATED FOR EVERY SIGNAL THAT IS ASSIGNED A VALUE IN A PROCESS.

*THE DRIVER OF A SIGNAL HOLDS ITS CURRENT VALUE AND ALL ITS FUTURE VALUES AS SEQUENCE OF ONE OR MORE TRANSACTIONS, WHERE EACH TRACSATION IDENTIFIES THE VALUE TO APPERAR ON THE SIGNAL ALONG WITH THE TIME AT WHICH THE VALUE IS TO APEAR.

SINGAL DRIVERS

PROCESS BEGIN ……….. ……….. RESET<=3 after 5 ns,21 after 10 ns,14 after 17 ns;End process;

Reset<curr@now(3@T+5ns)(21@T+10ns)(14@T+17ns)

Effects of transport delay on signal driversEffects of transport delay on signal drivers

Effects of inertial delay on signal driversEffects of inertial delay on signal drivers

OTHER SEQUENTIAL STATEMENTOTHER SEQUENTIAL STATEMENT

1. PROCEDURE CALL STATEMENT.2. RETURN STATEMENT

THERE ARE TWO OTHER FORMS OF SEQUENTIAL STATEMENTS;

THESE ARE THESE ARE DISCUSSED INDISCUSSED IN OTHER CHAPTEROTHER CHAPTER

DATAFLOW MODELLINGDATAFLOW MODELLING

*In the dataflow level of abstraction, a circuit is described in terms of how data moves through the system .

• The dataflow level is often called the register transfer level, or RTL.

Entity flipflop is Port (s,r : in std_logic; q,nq : out std_logic);end flipflop; architecture dataflow of flipflop is begin q <= s nand nq; nq <= r nand q;end dataflow;

Entity flipflop is Port (s,r : in std_logic; q,nq : out std_logic);end flipflop; architecture dataflow of flipflop is begin q <= s nand nq; nq <= r nand q;end dataflow;

SIGNAL ASSIGNMENT STATEMENT

*SIGNALS ARE ASSIGNED VALUES USING A SIGNAL ASSIGNMENT STATEMENT*A SIGNAL ASSIGNMENT STATEMENT CAN APPEAR WITHIN A PROCESS OR OUTSIDE OF A PROCESS. INSIDE MEANSINSIDE MEANS,IT IS CONSIDERED TO BE A SEQUENTIAL SIGNAL ASSIGNMENT STATEMENT. OUTSIDE MEANSOUTSIDE MEANS,IT IS CONSIDERED TO BE A CONCURRENT SIGNAL ASSIGNMENT STATEMENT.

SYNTAX OF SIGNAL ASSIGNMENT STATEMENT

SIGNAL OBJECT<=EXPRESION[AFTER DELAY--VALUE];

Table 3.1: Results of RS Flip-Flop Simulation

Rounds r q nqcomments

Start1 1 0 110 1 0 1‘1’ is scheduled on q20 1 1 1‘0’ is scheduled on nq30 1 1 0No new events are scheduled41 1 1 0No new events are scheduled

Entity decode isPort (s : in std_logic_vector(2 downto 0); -- 3 select inputs z : out std_logic_vector(7 downto 0) -- 8 data outputs);end docode; architecture rtl of decode is signal temp : std_logic_vector(7 downto 0);begintemp(0) <= not s(2) and not s(1) and not s(0);temp(1) <= not s(2) and not s(1) and s(0);temp(2) <= not s(2) and s(1) and not s(0);temp(3) <= not s(2) and s(1) and s(0);temp(4) <=s(2) and not s(1) and not s(0);temp(5) <=s(2) and not s(1) and s(0);temp(6) <=s(2) and s(1) and not s(0);temp(7) <=s(2) and s(1) and s(0);z <= temp;end rtl;

Know about VHDLVHSIC HARDWARE DESCRIPTION LANGUAGE

Modeling Language for ELECTRONIC SYSTEMS

Standard InternationalIEEE Std 1076-1987IEEE Std 1164-1993

VHDL is an alternative to Schematic Capture

but it is independent of all simulator

VHSIC HARDWARE DESCRIPTION LANGUAGE

Modeling Language for ELECTRONIC SYSTEMS

Standard InternationalIEEE Std 1076-1987IEEE Std 1164-1993

VHDL is an alternative to Schematic Capture

but it is independent of all simulator

Editor VHDLEditor VHDL

SynthesisVHDLSynthesisVHDL

Place and RoutePlace and Route

SimulatorSimulator VHDL VHDL

LibrariesLibraries VITALVITAL

• Capture VHDL(Graphic or Text)• Behavioral Simulation • Synthesis FPGA or ASIC• Place and Route• NetList Generation (VHDL + SDF)• Simulation structural (VITAL)

VHDL gates Level

StimuliStimuliStimuliStimuli

DESIGN FLOW

Behavioral

RTL

Layout

DIFFERENT ARCHITECTURES

Data flow Data flow model

Hardware system specification

ASIC/FPGA design for synthesis

Gate level or PLD design

Full custom design

Logic

Behavioral

RTL

LogicAB

Z

F

Levels of abstraction

a

b c

Scrap (5).shs

VHDL OBJECTS

THE MAJOR UNITS

ENTITY External ViewARCHITECTURE Internal ViewPROCESS Internal ViewCONFIGURATION Link between Entity &ArchitecturePACKAGE Header: Ext. View, Body Int. viewLIBRARY Work files

Know about VHDL

VHSIC HARDWARE DESCRIPTION LANGUAGE

Modeling Language for ELECTRONIC SYSTEMS

Standard International IEEE Std 1076-1987 IEEE Std 1164-1993

VHDL is an alternative to Schematic Capture but it is independent of all simulator

VHSIC HARDWARE DESCRIPTION LANGUAGE

Modeling Language for ELECTRONIC SYSTEMS

Standard International IEEE Std 1076-1987 IEEE Std 1164-1993

VHDL is an alternative to Schematic Capture but it is independent of all simulator