Vhdl modeling of the sram module and state machine controller smc module of rc4 stream cipher algorithm for wi fi encryption

International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN

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VHDL MODELING OF THE SRAM MODULE AND STATE

MACHINE CONTROLLER (SMC) MODULE OF RC4

STREAM CIPHER ALGORITHM FOR Wi-Fi

ENCRYPTION

Dr.A.M. Bhavikatti1

Mallikarjun.Mugali2

1,2

Dept of CSE, BKIT, Bhalki, Karnataka State, India

ABSTRACT

In this paper, VHDL modeling of the SRAM module and State Machine Controller (SMC)

module of RC4 stream cipher algorithm for Wi-Fi encryption is proposed. Various individual

modules of Wi-Fi security have been designed, verified functionally using VHDL-simulator.

In cryptography RC4 is the most widely used software stream cipher and is used in popular protocols

such as Transport Layer Security (TLS) (to protect Internet traffic) and WEP (to secure wireless

networks). While remarkable for its simplicity and speed in software, RC4 has weaknesses that argue

against its use in new systems. It is especially vulnerable when the beginning of the output key

stream is not discarded, or when nonrandom or related keys are used; some ways of using RC4 can

lead to very insecure cryptosystems such as WEP. Many stream ciphers are based on linear feedback

shift registers (LFSRs), which, while efficient in hardware, are less so in software. The design of

RC4 avoids the use of LFSRs, and is ideal for software implementation, as it requires only byte

manipulations. The RC4 algorithm will be implemented by FPGA using VHDL software platform.

Key words: VHDL simulation, RC4 stream cipher, SRAM module, State machine diagram

I. INTRODUCTION TO RC4 STREAM CIPHER

Cryptographic algorithms that can provide fast implementation, small size, low complexity,

and high security for resource-constrained devices such as wireless sensor devices are imperative.

Conventional cryptographic algorithms are very complex and consume significant amount of energy

when used by resource constrained devices for the provision of secure communication, and public

key algorithms are still not feasible in sensor networks for several reasons including limited storage

and excessive energy usage [1]. Therefore, security schemes should rely on a symmetric key

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cryptography especially when systems have limited hardware resources. There are a number of

stream cipher algorithms presented to implement high performance software including IDEA,

ORYX, LEVIATHAN, MUGI, RC4, Helix, SEAL, SOBER, and SNOW. RC4 is a proprietary

stream cipher which was designed in 1987 by Ron Rivest. RC4 is widely used in security software

based on stream cipher including one in the encryption of traffic to and from secure web sites such as

Transport Layer Security (TLS), Secure Socket Layer (SSL), and Wired Equivalent Privacy (WEP)

implementations. RC4 is fast in comparison to other algorithms and it has a simple design hardware

implementation [2]. For instance, RC4 is five times faster than Data Encryption Standard (DES) and

fifteen times faster than Triple-DES [3].

RC4 has been used as the data encryption algorithm for many applications and protocols.

Some of the protocols and applications using RC4 include the Wi-Fi, Skype, and Bit Torrent, to

name a few. Several efficient approaches to the implementation of RC4 have been proposed [4].

II. PROPOSED BLOCK DIAGRAM OF RC4 STREAM CIPHER

The block diagram of the proposed architecture is shown in Figure1below. The block

diagram can be divided in to 6 different sub modules as shown and these sub modules are i)The

payload data processor and controller ii) SMC iii) Key set up and key stream generation block iv) K-

Stream serializer v) KRAM(256× 8) vi) Multiplexer. As it is not possible to present all the

simulation results in a single paper, it is divided in to three parts and first two parts are already

presented in [5] and [6]. So, these modules are not discussed further in this paper. This paper deals

with simulation of SRAM (256× 8) module, State Machine Controller (SMC) modules and an

analysis of RC4 algorithm state machine diagram.

Fig 1 Simulated module of Wi-Fi Encryption architecture

III. SIMULATION OF SRAM(256× 8) MODULE

The module SRAM is similar to KRAM. It is used to store the data from 0 to 255 at the

address from 0 to 255 i.e. same data is assigned to the same memory location. The address is

assigned by the output of Addr1.In this if MemWr is 1 and MemRd is 0, then data is written in to the

RAM and if if MemWr is 0 and MemRd is 1, then data is read out one by one from the RAM. Data is

International Journal of Electronics and Communication Engineering &

0976 – 6464(Print), ISSN 0976 – 6472(Online), Volume 6, Issue 1, January (2015), pp.

given in parallel form and is read out in parallel

and Fig 3 shows the simulated waveforms of SRAM

Fig 2

IV ANALYSIS OF RC4 ALGORITHM STATE MACHINE DIAGRAM

Different states of state machine

Algorithm state machine diagram.

4.1 Idle state: Data is at original state.

4.2 Initial state: In this state, first we fill the SRAM and KRAM. To fill both the RAM, the data is

given directly to the KRAM for filling the data randomly as a DataBus and address is given by

Addr1.The data at SRAM is filled with the help of


6472(Online), Volume 6, Issue 1, January (2015), pp.

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in parallel form and is read out in parallel form. Fig 2 shows the simulated module of SRAM

and Fig 3 shows the simulated waveforms of SRAM.

Fig 2 Simulated module of SRAM

Fig 3 Simulated waveforms of SRAM

ALGORITHM STATE MACHINE DIAGRAM

Different states of state machine diagram are explained briefly here.

diagram.

Data is at original state.

In this state, first we fill the SRAM and KRAM. To fill both the RAM, the data is


The data at SRAM is filled with the help of Addr1 which gives the address

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Fig 2 shows the simulated module of SRAM

ALGORITHM STATE MACHINE DIAGRAM

are explained briefly here. Fig 4 shows RC4

In this state, first we fill the SRAM and KRAM. To fill both the RAM, the data is


Addr1 which gives the address and at the same



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time, same data comes from the DataMux and are loaded at the same address. Addr1 gives the

location from 0 to 255(as cnt255) in both the RAM. The output of Addr1 is given to the-----

Fig 4 RC4 Algorithm state machine diagram

---KRAM that gives the address for DataBus of KRAM. The input of SRAM (as Addr[7:0]) show

address and Data fill linearly from DataIn as S0=0, S1=1,S2=2,-------S255=255.The initial state

exists till the SRAM/KRAM fill completely( all 255 locations).After filling, initialOver=1, and state

go to Addr2Cal state.

4.3 Addr2Cal state: In this state, Mux gives the KeyDataOut as MuxOut by selecting the Scl=1, and

SRAM gives the data through DataOut to DataDMux and SellDataOut select this DataOut as SR1

[7:0] and load this value in S_Reg1 and all these values from A2, SR1 and MuxOut are added.

4.4 Addr2Ld state: In this state, the output of Adder 1(Adder 1Out) is loaded in to the Addr2

register.

4.5 SJ State: Loaded value at Addr2 gives j value. This j value is the address, which is selected by

SelAddr(3:0) of AddrMux. The output of AddrMux gives address of SRAM. The value of that

location is obtained as DataOut, selected by DatMux as SR2 [7:0] and stored at S_Reg2 as SJ.

4.6 Swap SI: In this state, the address is taken from Addr2, which is selected by AddrMux as

Addr[7:0] and the data is loaded on this address of SRAM as DataIn by selecting Reg2[7:0] through

DataMux.

4.7 Swap SJ: In this state, the address is taken from Addr1, which is selected by AddrMux as

Addr[7:0] and the data is loaded on this address of SRAM as DataIn by selecting Reg1[7:0] through

DataMux.

All process like Addr2Cal, Addr2Ld, SJ, Swap SI and Swap SJ occurred 255 times. When

Keysetupover=1, Flag=1, then it goes to Addr2Gen state.

4.8 Addr2Gen state: At this state, again we obtained the value of J by KeySetup phase.

4.9TCal state: When Swap SJ is complete, flag will be high and reaches the TCal state.



4.10Kbyte state: The data was given to FIFO in

4.11 Encryption state: The key data byte from K_StreamSerializer and plaintext from

DataSerializer comes out serially in the form of bits.

IV. STATE MACHINE CONTROLLER (SMC) MODULE

This is considered as the

Controller (SMC) module. By this, we can control all the modules .This state machine will work

whenever InitialOver and KeySetUpOver are high.

step. First it controls Addr, SRAM and KRAM. When enable is high means that it was writing key

data in it. Then it is going to the

input and it is given to the SRAM and this process run up to 256 times.

key data bytes is performed. Then it goes to Adder 2Gen.In this state, it takes the data from S_Reg

and gives it to the Adder i.e in Adder 2Ld.It adds the given

the help of AddrMux, which swap it and then gives it to the K_SteamSerilizer. At the same time,

with the help of FIFO, the available

parallel data input to serial output, which is further EX

6(a) and (b) shows the simulation waveforms of State Machine Controller (SMC) module

Fig 5 State Machine Controller (SMC) module



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The data was given to FIFO in the initial state is now loaded in to DataSerializer.

The key data byte from K_StreamSerializer and plaintext from

DataSerializer comes out serially in the form of bits.

STATE MACHINE CONTROLLER (SMC) MODULE

This is considered as the heart of the whole architecture. Fig 5 shows the State Machine

By this, we can control all the modules .This state machine will work

whenever InitialOver and KeySetUpOver are high. This means that all the modules will work step by

SRAM and KRAM. When enable is high means that it was writing key

another state i.e. Adder 2Ld. In this state, adder will add the given

and it is given to the SRAM and this process run up to 256 times. In this process, swapping of


and gives it to the Adder i.e in Adder 2Ld.It adds the given input and then gives it to the SRAM with


available KeyData is given to the DataSerilizer. Both sterilizers convert

ut to serial output, which is further EX-ORed to give the encrypted data serially.


State Machine Controller (SMC) module



the initial state is now loaded in to DataSerializer.

The key data byte from K_StreamSerializer and plaintext from

Fig 5 shows the State Machine

By this, we can control all the modules .This state machine will work

This means that all the modules will work step by

SRAM and KRAM. When enable is high means that it was writing key

In this state, adder will add the given

In this process, swapping of


input and then gives it to the SRAM with


is given to the DataSerilizer. Both sterilizers convert

ORed to give the encrypted data serially. Fig




Fig 6(a) Simulation waveforms of

Fig 6(b) Simulation waveforms of State Machine Controller (SMC) module



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Simulation waveforms of State Machine Controller (SMC) module




State Machine Controller (SMC) module




85

T a b l e 1 D e t a i l s o f S i m u l a t i o n

V. CONCLUSIONS

Various individual modules of RC4 stream cipher for Wi-Fi security have been designed,

verified functionally using VHDL Simulator, synthesized by the synthesis tool and a final net list has

been created. The proposed design provides high data throughput using 8-bit word and variable key

length, from 8-bit to 128-bit. The proposed system achieves a data throughput of up to 22Mbps at a

clock frequency of 64 MHz .The design has been synthesized using FPGA technology from Xilinx.

Table 1 below shows the details of simulation. The measurement result and comparison with

previous implementation prove that the one proposed is flexible solution for any cryptographic

system.

VI. REFERENCES

1. Sharma K, Ghose MK, Kumar D, Singh RPK, Pandey VK, “A comparative study of various

security approaches used in wireless sensor networks” Int J Adv Sci Technol, 177(77), 2010.

2. Gupta SS, Chattopadhyay A, Sinha K, Maitra S, Sinha B, “ High-performance hardware

implementation for RC4 stream cipher” IEEE Trans Comput 62(4):730–743,2013.

3. Ahmad S, Beg MR, Abbas Q, Ahmad J, Atif S, “ Comparative study between stream cipher

and block cipher using RC4 and Hill Cipher” Int J Comput Appl (0975–8887), 1(25),2010.

4. Disha Handa, Bhanu Kapoor “ State of the Art Realistic Cryptographic Approaches for RC4

Symmetric Stream Cipher”, International Journal on Computational Sciences & Applications

(IJCSA) Vol.4, No.4, August 2014.

5. A.M.Bhavikatti, S. Srinivas Rao “VHDL Modeling of the payload data processor and

controller of RC4 stream cipher for Wi-Fi encryption” ,ICVED-2008, Proceedings of

International Conference on Embedded system & VLSI Design, 20-21 March 2008, at

PDVVP College of Engineering, Ahmednagar.

6. Dr.A.M.Bhavikatti, “VHDL Simulation of KRAM, Multiplexer and K Stream serializer

modules of RC4 Stream Cipher for Wi-Fi Security” ,International Journal of Advances in

Wireless and Mobile Communications (AWMC) ,ISSN 0973-6972, Volume 6, Number 1,

pp17-23,2013.

7. Meha Sharma and Rewa Sharma, “VHDL Implementation of Discrete Wavelet

Transformation For Efficient Power Systems” International journal of Electronics and

Communication Engineering &Technology (IJECET), Volume 1, Issue 1, 2010, pp. 10 - 20,

ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.

8. Sapna and Prof. B. P. Singh, “Low Power SRAM” International journal of Electronics and

Communication Engineering &Technology (IJECET), Volume 4, Issue 2, 2013, pp. 257 -

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Vhdl modeling of the sram module and state machine controller smc module of rc4 stream cipher algorithm for wi fi encryption

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