VHDL VHDL & & CIRCUIT SIMULATION CIRCUIT SIMULATION Made by: MANSI ROLL NO. 101206082
Nov 20, 2015
VHDL &CIRCUIT SIMULATIONMade by:MANSIROLL NO. 101206082
VHDL stands for Very high speed integrated circuit Hardware Description Language
A language used to describe complex digital circuits
HISTORYIt was developed by American department of defense in the year 1980.
It was standardized in year 1987 by IEEE VHDL
VHDL PROGRAMMING BASICSBASIC BODY OF A VHDL PROGRAM
Library is a collection of commonly used pieces of code. Placing them inside a library allows them to be used by other designs.
Mostly three libraries are used1. ieee.std_logic_1164 (from ieee library)2. standard (from std library)3.work (form work library)
Library
Specification of input and output pins
SYNTAX:Entity
ARCHITECTURE
Internal details of the structure are specified in the architecture body
3 types of modelingDataflow style of modelingStructural style of modelingBehavioral style of modeling
ADVANTAGES OF VHDLCircuit can be checked before implementationIs a concurrent languageA program created can be used again.
APPLICATIONS OF VHDLFPGA and ASICCircuit design
32-BIT CARRY SELECT ADDER
One ripple carry adder at a time!!
Inputs given to full adder
Multiplexer selects which ripple carry adder is active
Multiplexer used is a 2:1 and inputs are vectored
Carry for next mux generated by previous mux
Output sum selected on basis of carry that is given at input
Carry out of last full adder (MSB) given in last multiplexer
32-BIT CARRY SELECT ADDER
VHDL CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity csa32 is Port ( a : in STD_LOGIC_VECTOR (31 downto 0); b : in STD_LOGIC_VECTOR (31 downto 0); cin : in STD_LOGIC; s : out STD_LOGIC_VECTOR (31 downto 0); cout : out STD_LOGIC);end csa32;
architecture Behavioral of csa32 iscomponent csa_block Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); cin : in STD_LOGIC; s : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC);end component;component rcgen Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); cin : in STD_LOGIC; s : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC);end component;VHDL CODE:
16-BIT CARRY SKIP ADDER
VHDL CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity cska is Port ( a : in STD_LOGIC_VECTOR (15 downto 0); b : in STD_LOGIC_VECTOR (15 downto 0); cin : in STD_LOGIC; s : out STD_LOGIC_VECTOR (15 downto 0); cout : out STD_LOGIC);end cska;
16-bit Carry look ahead adder
VHDL CODE:library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity cla3 is Port ( a : in STD_LOGIC_VECTOR (15 downto 0); b : in STD_LOGIC_VECTOR (15 downto 0); ci : in STD_LOGIC; s : out STD_LOGIC_VECTOR (15 downto 0); cout : out STD_LOGIC);end cla3;architecture Behavioral of cla3 is
CIRCUIT SIMULATION PROJECT
BISTABLE MULTIVIBRATOR USING 555 TIMER IC
SOME OF THE COMPONENTS USED ARE:
555 TIMER IC78 POWER REGULATORSFULL WAVE BRIDGE RECTIFIER
555 TIMER ICMonolithic timing circuitOperates on +5 volts to +18 voltsDuty cycle adjustable78xx POWER REGULATORStable DC voltagexx series FULL WAVE BRIDGE RECTIFIEROutput is full wave No need for center tap
Power supply is rectified by full wave bridge rectifier
Capacitor further smoothens the output
Power regulator obtains a smooth DC
DC supply powers 555 timer IC
All components taken are virtual
Thank You