Vhdl File

FULL ADDER AIM: To synthesize and simulate a full adder using V.H.D.L Behaioural model .

TOOLS: XILINX ISE 10.1 and V.H.D.L language .

Truth table of FULL ADDER: A B CIN SUM COUT 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

RTL Schematic :

Program :

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC);end fulladder;

architecture Behavioral of fulladder is

beginsum <= a xor b xor c;carry <= (a and b)or(b and c)or(c and a);

end Behavioral;

RESULT :

SUBTRACTOR AIM: To synthesize and simulate a subtractor using V.H.D.L Behaioural model.

TOOLS: XILINX ISE 10.1 and V.H.D.L language .

Truth table :

a b C difference borrow

0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

RTL Schematic:

Programs :

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity subtractor1 is Port ( a,b,c : in STD_LOGIC; borrow : out STD_LOGIC; difference : out STD_LOGIC);end subtractor1;

architecture Behavioral of subtractor1 is

begindifference <= a xor b xor c;borrow <= (( not a) and b) or (b and c) or (( not a) and c);

end Behavioral;

Result :

DECODER

AIM: To synthesize and simulate a decoder using V.H.D.L Behaioural model.

TOOLS: XILINX ISE 10.1 and V.H.D.L language .

Truth table :

a b c Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y70 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

RTL Schematic:

Program :

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Decoder is

Port ( a,b,c : in STD_LOGIC;

Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7 : out STD_LOGIC);

end Decoder;

architecture Behavioral of Decoder is

begin

Y0 <= (NOT a ) AND (NOT b ) AND (NOT c);

Y1 <= (NOT a ) AND (NOT b ) AND c;

Y2 <= (NOT a ) AND b AND (NOT c);

Y3 <= (NOT a ) AND ( b ) AND ( c);

Y4 <= a AND (NOT b ) AND (NOT c);

Y5 <= a AND (NOT b ) AND (c);

Y6 <= ( a ) AND ( b ) AND (NOT c);

Y7 <= ( a ) AND ( b ) AND ( c);

end Behavioral;

RESULT:

INDEX

S.NO PROGRAM DATE SIGNATURE

Experiment NO. – 6

AIM: To synthesis and simulate a 3 bit EVEN PARITY GENERATOR.

TOOL USED: XILINX ISE 10.1 and VHDL language.

THEORY: In an even parity generator, the parity bit is set to 1 if the counts of ones in a given set of bits(excluding the parity bit ) is odd making the count of ones in the entire set of bits (including the parity bit ) even. When the count of ones in the set of bits is even, then the parity bit is set to 0.

TRUTH TABLE:

X Y Z PE0 0 0 00 0 1 10 1 0 10 1 1 01 0 0 11 0 1 01 1 0 01 1 1 1

CIRCUIT DAIGRAM:

PROGRAM:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity parity1 is Port ( x,y,z : in STD_LOGIC; pe : out STD_LOGIC);end parity1;

architecture Behavioral of parity1 is

begin

pe <= (x xor y xor z);

end Behavioral;

RESULT:

Experiment NO. – 5

AIM: To synthesis and simulate a 3 bit ODD PARITY GENERATOR.

TOOL USED: XILINX ISE 10.1 and VHDL language.

THEORY: In an odd parity generator, the parity bit is set to 1 if the counts of ones in a given set of bits(excluding the parity bit ) is even making the count of ones in the entire set of bits (including the parity bit ) odd. When the count of ones in the set of bits is odd, then the parity bit is set to 0.

TRUTH TABLE:

X Y Z PO0 0 0 10 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0

CIRCUIT DAIGRAM:

PROGRAM:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity parity1 is Port ( x,y,z : in STD_LOGIC; po : out STD_LOGIC);end parity1;

architecture Behavioral of parity1 is

begin

po <= not (x xor y xor z);

end Behavioral;

RESULT: