Vhdl [Compatibility Mode]

8/3/2019 Vhdl [Compatibility Mode]

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HDL For EmbeddedHDL For EmbeddedHDL For EmbeddedHDL For Embedded

SystemSystemSystemSystem

1

Mukesh Maheshwari


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VHDLVHDLVHDLVHDL

INTRODUCTION

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IntroductionIntroductionIntroductionIntroduction

WHAT IS VHDL ?

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FEATURES OF VHDL

HISTORY OF VHDL

LEVELS OF ABSTRACTION


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What is VHDL?What is VHDL?What is VHDL?What is VHDL?

DIGITAL SYSTEM DESIGN USINGHDLS IS AN ESTABLISHED

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.

VHDL stands for

Very High Speed Integrated Circuits

Hardware Description Language.


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Features of VHDLFeatures of VHDLFeatures of VHDLFeatures of VHDL

VHDL is the amalgamation of following languages:

Concurrent Language

Sequential Language

Timing Specification Simulation Language

Test Language

5

Powerful Language Constructs Ex: if---else, with---select, etc.

Design Hierarchies to create Modular designs

Supports Design LibrariesFacilitates device independent design and

Portability


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Concurrent LanguageConcurrent LanguageConcurrent LanguageConcurrent Language

Concurrent Statements execute atatatatthe same time in parallelthe same time in parallelthe same time in parallelthe same time in parallel, as in

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.


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Sequential LanguageSequential LanguageSequential LanguageSequential Language

Sequential Statements execute one atone atone atone at

a timea timea timea time in sequence.As the case with any conventional

lan ua e

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Sequence of statements is important.


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Timing SpecificationTiming SpecificationTiming SpecificationTiming Specification

Example:

process

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8

clk


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Test LanguageTest LanguageTest LanguageTest Language

Test bench Is part of a VHDL model that generates a set of test

vectors and sends them to the Module being tested.

Collects the responses made by the Module Under Test

and compares them against a specification of correct

results.

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Need

To ensure that design is correct.

Model is operating as required.


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Design HierarchyDesign HierarchyDesign HierarchyDesign Hierarchy

Hierarchy can be represented using VHDL.

Consider example of a Full-adder which is the top-

level module, being composed of three lower level

modules I.e. Half-Adder and OR gate.

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Design Unit

Is any block of VHDL code or collection of VHDLcodes that may be independently analysed and

inserted into a design library.

Design librariesDesign librariesDesign librariesDesign libraries 11

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Is a storage facility in which analysed VHDL

descriptions are stored.


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History of VHDLHistory of VHDLHistory of VHDLHistory of VHDL

In 1981 the Institute for Defense Analysis (IDA) had arranged

a workshop to study

Various Hardware Description methods Need for a standard language

Features required by such a standard.

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A team of three companies, IBM, Texas Instruments, andIntermetrics were awarded contract by DoD to develop a

language.

Version 7.2 of VHDL was released along with LanguageReference Manual (LRM) in 1985.

Standardized by IEEE in 1987 known as the IEEE Std 1076-

1987.


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Logic SystemsLogic SystemsLogic SystemsLogic Systems

Need for a multi-valued Logic System

Conventional Logic systems had only three valuesI.e. 0 , 1 and Z

Consider truth table for AND gate

A B Y

0 0 0

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1 0 0

1 1 1

For

0 Z ???

A 9-value package STD_LOGIC_1164 was developedand accepted as IEEE Std 1164-1993.


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Logic SystemsLogic SystemsLogic SystemsLogic Systems

Need for a standard Logic System

Different vendors used different logic systems.

Sharing of codes developed on different toolsets wasdifficult.

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Multivalued logic

Unknown : Value was known, but is not anymore.

Un-initialized : Value was never known in the firstplace !

High impedance : Net has no driver.

Drive strengths : Handle different output drivers.

Dont care : Optimizes synthesis implementation.


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MultiMultiMultiMulti----Valued LogicValued LogicValued LogicValued Logic

A 9-value package STD_LOGIC_1164

was developed and accepted as IEEE

Std 1164-1993.U : Uninitialized

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: n nown

0 : Logic 0

1 : Logic 1

Z : High impedance

W : weak unknown

L : weak logic 0

H : weak logic 1

- : Dont care


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ELEMENTS OF VHDLELEMENTS OF VHDLELEMENTS OF VHDLELEMENTS OF VHDL AgendaAgendaAgendaAgenda

BASIC BUILDING BLOCKS

ENTITY

ARCHITECTURE

LANGUAGE ELEMENTS

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SEQUENTIAL STATEMENTS

SIGNALS & VARIABLES

CONFIGURATION

PACKAGE


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Basic Building BlocksBasic Building BlocksBasic Building BlocksBasic Building Blocks

Entity

A designs interface to the external circuitry.

Architecture

Describes a designs behavior and functionality.

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Configuration

Binds an entity to an architecture when there are multiple

architectures for a single entity.

Package Contains frequently used declarations, constants,

functions, procedures, user data types and components.


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Basic Building BlocksBasic Building BlocksBasic Building BlocksBasic Building Blocks

Library

Is a collection of compiled VHDL units

Promotes sharing of compiled designs and hides thesource code from the users

Commonly used functions, procedure and user data types

can be compiled into a user-defined library for use in all

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designs Library should be declared before EACH entity declaration

even if it is in the same VHDL file.

Syntax library IEEE;

use IEEE.std_logic_1164.all

use IEEE.std_logic_unsigned.all


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EntityEntityEntityEntity

Equivalent to pin configuration of an IC.

Syntax: entity entity_name is

port (port_list);

end entity_name;

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Example :entity and_gate is

port ( 1A, 2A, 3A, 4A : in std_logic;

1B, 2B, 3B, 4B : in std_logic;

1Y, 2Y, 3Y, 4Y : out std_logic) ;

end and_gate ;


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VHDL design description must include,

ONLY ONE ENTITY

Entity Declaration

Defines the input and output ports of the design.

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ac por n e por s mus e g ven,

a name

data flow direction

a type.

Can be used as a component in other entities after being

compiled into a library.


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Proper documentation of the ports in an entity

is very important.

A specified port should have a self explanatory

name that provides information about its

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.

Ports should be well documented with

comments at the end of the line providing

additional information about the signal.

Consider example of an ALU.


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ModesModesModesModes

Signal in the port has a Mode which

indicates the driver direction.

Mode also indicates whether or not theport can be read from within the

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.

Four types of Modes are used in

VHDL.

Mode IN Mode OUT

Mode INOUT

Mode BUFFER


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ModeModeModeMode ININININ

Value can be read but notassigned.

Example:

Port SignalPort SignalPort SignalPort SignalEntityEntityEntityEntity

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entity driver is

port ( A : in std_logic;

B : out std_logic;

Data : inout std_logic;

Count : buffer std_logic) ;

end driver ;

Drivers resideDrivers resideDrivers resideDrivers resideoutside the entityoutside the entityoutside the entityoutside the entity


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ModeModeModeModeOUTOUTOUTOUT

Value can be assigned but not

read.

Example:

Entit

y

Port Signal

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port ( A : in std_logic;B : out std_logic;


Count : buffer std_logic )

;

end driver ;

Drivers resideinside the entity


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ModeModeModeMode INOUTINOUTINOUTINOUT

Bi-directional

Value can be read and assigned

Example:

entity driver is

Entity

Portsignal

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_

B : out std_logic;



;

end driver ;

Drivers may reside both

inside and outside the entity

Signal can

be readinside the

entity

Data


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ModeModeModeMode BUFFERBUFFERBUFFERBUFFER

Output port with Internal read

capability

Example:

Count

Entity

Driver reside

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port ( A : in std_logic;B : out std_logic;



;

end driver ;

Signal inside can be

read inside the entity


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ArchitectureArchitectureArchitectureArchitecture

Specifies,

Behavior

Function Relationship between inputs and outputs of an

entity.

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Syntax:architecture architecture_nameof entity_nameis

declarations

beginconcurrent_statements

end [ architecture_name ];


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Equivalent to truth table.

Example:

A B C

L L L

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L H LH L L

H H H


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Can contain only Concurrent Statements.

A design can be described in an Architecture using

various Levels of Abstraction.

To facilitate faster desi n

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Better understanding Lesser complexity.

There can be no architecture without an Entity.


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VHDL Design Styles or Hardware Design

Modeling

VHDL DesignVHDL DesignVHDL DesignVHDL Design

StylesStylesStylesStyles

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Components and

interconnects

Concurrent

statements RegistersRegistersRegistersRegisters & counters& counters& counters& counters

Sequential statements


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Architecture BodiesArchitecture BodiesArchitecture BodiesArchitecture Bodies

Behavioral

Also known as High-levelDescriptions.

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assignment statements torepresent behavior.

No need to focus on the

gate-level implementationof a design.


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Dataflow

Use concurrent

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signalassignment

statements.


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Structural

Components fromlibraries are connectedtogether.

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Designs are hierarchical.

Each component can beindividually simulated.

Consists of VHDLnetlists.

It is possible to mix the three Modeling styles in a single

architecture body.


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Comparing Architectural BodiesComparing Architectural BodiesComparing Architectural BodiesComparing Architectural Bodies

A structural design methodology is used to

Split a design into manageable units.

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instantiate components that represent device-specificresources and optimized structures.

eg. LogiBLOX in Xilinx Tool.


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Language ElementsLanguage ElementsLanguage ElementsLanguage Elements

VHDL is a strongly TYPED Language.

VHDL is notnotnotnot casecasecasecase sensitivesensitivesensitivesensitive.

VHDL supports a variety of data types and operators.

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OBJECTS

OPERATORS

AGGREGATES


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OBJECTSOBJECTSOBJECTSOBJECTS

Objects are used to represent & store the data in the systembeing described in VHDL.

Object contains a value of a specific type. For ex:

object

SIGNAL COUNT : INTEGER

results in an object

called count which holds

inte er value

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class Data type

The name given to object (also port ) is called as identifier.

RESERVED WORDS cannot be used as identifies

Each object has a type & class. Class indicates how the object is used in the model & what

can be done with the object.

Type indicates what type of data the object contains.


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OBJECTSOBJECTSOBJECTSOBJECTS

Each object belong to one of the following

CLASS

CONSTANT SIGNAL

VARIABLE

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The set of values that each object can hold is

specified by DATA TYPES

SCALAR ACCESS FILE

COMPOSITE

Integer ArrayRealEnumerated

Physical


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SIGNALSSIGNALSSIGNALSSIGNALS

Represents wires within a circuit.architecture and_gt of anding is

signal temp : std_logic;

beginU1 : AND2 portmap

(a,b,temp);

U2 : AND2 portmap

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Thus Signals can used

To connect design entities together & communicate changesin values within a design.

Instead of inoutsignals.

Each signal has a history of values i.e holds a list of valueswhich include current value of signal & set of possible future

values that are to appear on the signal.

Computed value is assigned to signal after specified delay called

delta delay .

, ,

end and_gt;

>>>>


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VARIABLESVARIABLESVARIABLESVARIABLES

These are objects with single current value.

Are used to store the intermediate values between the

sequential VHDL statements.

Variable assignment occurs immediately.

Variable can be declared & used inside the process

statement only. But retain their value throughout the entire

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simulation.

process ( a )

variable a_int : integer :=1;

begin

a_int := a_int + 1;

end process;

Note : a_int contains the total

number of events that occurred

on signal a


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Scalar Data TypesScalar Data TypesScalar Data TypesScalar Data Types

ENUMERATION TYPES :This declaration defines a set of user-defined values

consisting of identifiers & character literals.

Ex : type micro_op is ( load, store, add, sub, mul, div )

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As shown micro_op is enumerated types & supports thevalues load, store, add & sub.

Values of enumeration type has position numberassociated with them. Compiler encodes theseenumeration literals in ascending order.


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Scalar data typesScalar data typesScalar data typesScalar data types

PREDEFINED ENUMERATION TYPES

Bit Supports the values 0 & 1.Boolean Supports literals FALSE & TRUE is defined as

Ex : variable error_flag : boolean := true.

Std_lo ic_t e Data t e defined in the std_lo ic_1164 acka e of

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IEEE library. It is defined as

type std_logic is (U, X, 0, 1, Z, W, L, H);

U : Uninitialized

X : Unknown

0 : Logic 0

1 : Logic 1

Z : High impedance

W : Unknown

L : Low logic 0

H : Low logic 1 - : Dont care

U, X W, - represent behavior of

model itself rather than thebehavior of hardware being

synthesized.

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SCALAR DATA TYPESSCALAR DATA TYPESSCALAR DATA TYPESSCALAR DATA TYPES

Data type Meaning Example

Integer Has set of values

that follow within

specific range

type index is range 0 to 15

signal count : integer range o

to 8

Real Has a set of values t e real data is ran e 0.0 to

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OBJECTS OF PHYSICAL TYPE ARE NOTSYNTHESISABLE ??

in given range of

real numbers.

_

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Physical Used to representphysical quantities

such as current,

time distance

Constant set_up : time := 2 ns.

COMPOSITE DATA TYPESCOMPOSITE DATA TYPESCOMPOSITE DATA TYPESCOMPOSITE DATA TYPES 44


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COMPOSITE DATA TYPESCOMPOSITE DATA TYPESCOMPOSITE DATA TYPESCOMPOSITE DATA TYPES

Represents collection of values.

Ex ARRAY: - Consists of the elements that have same type.

Vector ( special case of single dimensional array )Ex signal A : std_logic_vector (7 downto 0);

Two dimensional array (typical application is a memory device)

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Ex : type memory 1K4 is array ( 0 to 1023 ) of std_logic_vector ( 3type memory 1K4 is array ( 0 to 1023 ) of std_logic_vector ( 3type memory 1K4 is array ( 0 to 1023 ) of std_logic_vector ( 3type memory 1K4 is array ( 0 to 1023 ) of std_logic_vector ( 3

downto 0);downto 0);downto 0);downto 0);

signalsignalsignalsignal memorymemorymemorymemory :::: memorymemorymemorymemory 1111KKKK4444

D t O tD OD OD t O t 45


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Data OperatorsData OperatorsData OperatorsData Operators

Logical Operators Lowest priority (except not)

??

Relational Operators

Shift Operators

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Adding Operators

Multiplying Operators

Miscellaneous Operators Highest priority


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R l ti l ( C diti l ) O tR l ti l ( C diti l ) O tR l ti l ( C diti l ) O tR l ti l ( C diti l ) O t 47


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Relational ( Conditional ) OperatorsRelational ( Conditional ) OperatorsRelational ( Conditional ) OperatorsRelational ( Conditional ) Operators

Are used to check conditions.

= /= < > == /= < > == /= < > == /= < > =

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= arepredefined for

For integer types

Enumerated types

One-dimensional arrays of enumeration

and integer types.

Relational OperatorsRelational OperatorsRelational OperatorsRelational Operators 48


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Relational OperatorsRelational OperatorsRelational OperatorsRelational Operators

No numerical meaning is associated with a BIT

vector

Elements of a vector are just a collection of objectsof the same type.

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For array types operands are aligned to the left and

compared to the right.

Shift O tShift O tShift O tShift O t VHDL 93VHDL 93VHDL 93VHDL 9349


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Shift OperatorsShift OperatorsShift OperatorsShift Operators VHDL 93VHDL 93VHDL 93VHDL 93

sll srl sla sra ror rolsll srl sla sra ror rolsll srl sla sra ror rolsll srl sla sra ror rol

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sll Shift left logical

srl Shift right logical

sla Shift left arithmetic

sra Shift right arithmetic rol Rotate left logical

ror Rotate right logical

Shift OperatorsShift OperatorsShift OperatorsShift Operators 50


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Shift OperatorsShift OperatorsShift OperatorsShift Operators

Each operator

Takes an array of BIT or BOOLEAN as the left operand

Integer value as the right operand

Ex: A is a bit_vector equal to 10010101

A sll 2 is 01010100 (shift left logical, filled with 0)

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A srl 3 is 00010010 (shift right logical, filled with 0)

A sla 3 is 10101111 (shift left arithmetic, filled with right

bit )

A sra 2 is 11100101 (shift right arithmetic, filled withleft

bit )

A rol 3 is 10101100 (rotate left)

A ror 2 is 01100101 (rotate right)


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Adding OperatorsAdding OperatorsAdding OperatorsAdding Operators52


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Do not use Concatenation operator on

the left of the assignment symbol.

Adding OperatorsAdding OperatorsAdding OperatorsAdding Operators

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architecture bad of ex issignal a : std_logic_vector ( 2 downto 0 );

signal b : std_logic_vector ( 3 downto 0 );

begin

0 & a


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( * ) and ( / ) are predefined for: Integers Floating pointnumbers

Multiplying OperatorsMultiplying OperatorsMultiplying OperatorsMultiplying Operators

**** //// mod remmod remmod remmod rem

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mod ( modulus ) and rem ( remainder ) are predefined forIntegers only.Example:

variable A,B : Integer;

Variable C : Real;C


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The abs operator has only one operand. It allows defining the

operands absolute value. The result is of the same type asthe operand.

Miscellaneous OperatorsMiscellaneous OperatorsMiscellaneous OperatorsMiscellaneous Operators

AbsAbsAbsAbs ********

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** ( Exponential Operator ) is defined for any integer orfloating point number

Examples :

2 ** 8 = 2563.8 ** 3 =54.872

abs (-1) = 1

AggregatesAggregatesAggregatesAggregates 55


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Aggregates:

Assigns values to the elements of an array.

Example :a 0; ) identical to a 1, others =>0 );

signal data_bus : std_logic_vector ( 15 downto 0 );

data_bus '0', others => '1 );

AggregatesAggregatesAggregatesAggregates 56


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Elements in a vector can also be assigned values of other

signals.

Example : a has a length of 5 bits.

a c(2), 3=> c(1), others => d(0);

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a


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Concurrent StatementsConcurrent StatementsConcurrent StatementsConcurrent Statements

MEANING IN HARDWARE TERMS

CONCURRENT CONSTRUCTS

WHEN_ELSE STATEMENT

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WITH_SELECT STATEMENT

SEQUIENTIAL CONSTRUCTS

- if - else STATEMENT

- case STATEMENTCOMPONENT INSTANTIATION

USE OF GENERATE STATEMENT

Concurrent StatementsConcurrent StatementsConcurrent StatementsConcurrent Statements 58


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Consider

X = X+Y;

In software:

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X and Y are register

locations

The contents of Xand Y are added and

the result is stored

in X.

Concurrent StatementsConcurrent StatementsConcurrent StatementsConcurrent Statements59


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Concurrent StatementsConcurrent StatementsConcurrent StatementsConcurrent Statements

In concurrent

statements, there

are no implied

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registers.

Feedback is

described around

Combinational

logic.

DriversDriversDriversDrivers60


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Are created by signal assignment statements

Concurrent signal assignment produces one driver

for each signal assignment

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DriversDriversDriversDrivers61


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elected Signal Assignment when statement62


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g g

Z


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Modeling Tri-state buffer

architecture tri_ex_a of tri_ex is

begin

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out1


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g gg g

Syntax with choice_expression select

target


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signal A, B, C, D, Z: std_logic;

signal CONTROL: std_logic_vector

(1 downto 0);

with CONTROL selectZ


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Syntax: if condition1 then{ sequential_statement }

elsif condition2then

{ sequential_statement }

else

se uential statement

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_

end if;

If Statement evaluates each

condition in order.Statements can be nested.

if Statementif Statementif Statementif Statement67


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Avoid using more than three levels Of Ifelse statements .

When defining the condition, use parentheses to differentiate

levels of operations on the condition.

If statementIf statementIf statementIf statement68


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process (sel, a, b, c, d)

beginIf sel(2) = 1 then

y


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Syntax: case expressioniswhen choice1 =>{ statements }when choice2=>{ statements }

when others=>{ statements }

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end case;

Case Statement isIs a series of

parallel checks to check a

condition.It selects, for execution one of a

number of alternative sequences of

Case statementCase statementCase statementCase statement70


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process (sel,a,b,c,d)begin

case sel is

when 0=> y y y

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y


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Every possible value of the case expression must be covered in

one and only one whenclause.Each choice can be either a static expression ( such as 3 ) or a

static range ( such as 1 to 3 ). we cannot have a when

condition

that changes when it is being evaluated.

Null StatementNull StatementNull StatementNull Statement 72


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Does not perform any action

Can be used to indicate that whensome conditions are met no action is

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to be performed

Example:case a is

when 00 => q1 q2 q3


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Process StatementProcess StatementProcess StatementProcess Statement characteristicscharacteristicscharacteristicscharacteristics

Are executed one after another, in the order in which they arewritten.

Can appear only in a Process or Subprogram. Only sequential statements can use Variables.

Process is the primary concurrent VHDL statement used to

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describe sequential behavior.

Statements in a process, are executed sequentially in zerotime.

All processes in an architecture behave concurrently.

NOTE : SEQUENTIAL STATEMENTS DO NOT GENERATE

SEQUENTIAL HARDWARE

Process StatementProcess StatementProcess StatementProcess Statement

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Process StatementProcess StatementProcess StatementProcess Statement

Process places

only one driver ona signal.

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Value that thesignal is updated

with is the last

value assigned to

it within the

process

Rules About ProcessRules About ProcessRules About ProcessRules About Process 75


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A process with a sensitivity clause must not contain an

explicit wait statement.

Only static signal names for which reading is permitted may

appear in the sensitivity list of a process statement.

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The execution of a process statement consists of therepetitive execution of its sequence of statements.

Sensitivity ListSensitivity ListSensitivity ListSensitivity List76


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Simulator runs a process

when any one of the signals

in the sensitivity list

changes.

Process should either have a

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sensitivity list or a wait

statement at the end.

Only static signal names are

allowed in the sensitivity list.

Process statementProcess statementProcess statementProcess statement


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Two types of processes:

CombinatorialClocked

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Combinatorial Process

Generates combinational logicAll inputs must be present in the sensitivity

list.

Process StatementProcess StatementProcess StatementProcess Statement78


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Clocked Process:

Generates synchronous logic.process (clk)begin

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if (clk event and clk =1 )

thenQ < = D;

end if;

end process;


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Loop statementsLoop statementsLoop statementsLoop statements


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Loop statements are used to iterate through a set of sequentialstatements.

While loop

Syntax: loop_label:while conditionloop

8 0

sequence_of_statements

end loop loop_label

Has a Boolean Iteration Scheme.

Condition is evaluated before execution.

Loop statementsLoop statementsLoop statementsLoop statements 81


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Loop statements are used to iterate through a set of

sequential statements.

While loop Syntax: loop_label:while conditionloopsequence_of_statements

end loop loop_label

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process ( Input )variable i : POSITIVE := 1;

begin

L1: while i


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Syntax: loop_label:forloop_parameterinrange loop

Sequence_of_statements

end looploop_label;

Has an Integer Iteration Scheme. Number of repetitions is

determined by an Integer range

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The loop parameters range is tested at the beginning of the loop, not

at the end.

Example : factorial := 1;

for number in 2 to N loopfactorial := factorial * number;

end loop;

Loop StatementsLoop StatementsLoop StatementsLoop Statements For LOOPFor LOOPFor LOOPFor LOOP 83


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For loop rules

Loop parameter is implicitly defined.

Inside the loop, the loop parameter is a

constant. Thus, it may be used but not

8 3

a tere .

Discrete range of the loop is evaluatedbefore the loop is first executed.

Loop counter only exists within the loop.

Labels in loop parameters enable betterloop control with the next and exit

statements.

Loop statementsLoop statementsLoop statementsLoop statements Next StatementNext StatementNext StatementNext Statement 84


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Syntax:

next;

next loop_labelwhen condition;

Skips the remaining statements in the current iteration of the

8 4

spec e oop.

Execution resumes with the first statement in the next

iteration of the loop.

Loop statementsLoop statementsLoop statementsLoop statements Next StatementNext StatementNext StatementNext Statement85


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Example:

for J in 10 downto 5 loopif sum < total_sum thensum := sum + 2;

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elsif sum = total_sum then

next;else

null;

end if;

k : k+1;

end loop;

Loop statementsLoop statementsLoop statementsLoop statements exit Statementexit Statementexit Statementexit Statement 86


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Exit Statement

Syntax:

exit;

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exit loop_labelwhen condition;

Entirely terminates the execution of the loop in which it is located.

Loop statementsLoop statementsLoop statementsLoop statements exit Statementexit Statementexit Statementexit Statement 87


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Example:

sum := 1; j := 0;L3 : loop

J := J + 21;sum := sum * 10;

if sum > 100 then

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ex t ;

end if;end loop L3;

Note:

Exit : Causes the specified loop to be terminated.

Next :Causes the current loop iteration of the specifiedloop to be prematurely terminated; execution resumes withthe next iteration.

Component InstantiationComponent InstantiationComponent InstantiationComponent Instantiation


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Syntax:

instance_name : component_nameport map (

[ port_name => ] expression

8 8

[port_name => ] expression);

instance_namenames this instance of the component type

component_name - WHY?

port mapconnects each port of this instance of

component_nameto a signal-valued expression in the currententity.

Component InstantiationComponent InstantiationComponent InstantiationComponent Instantiation 89


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entity ND4 ISport ( IN1,IN2,IN3,IN4 : in BIT;

Z : out BIT);end ND4;architecture gate_arch of ND4 is

component ND2port ( A, B: in BIT;

C : out BIT);

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signal TEMP_1,TEMP_2 : BIT;begin

U1: ND2 port map ( A =>IN1, B =>IN2, C=>TEMP_1 );U2: ND2 port map ( A =>IN3, B =>IN4, C=>TEMP_2 );U3: ND2 port map ( A =>TEMP_1, B =>TEMP_2, C=>Z );

Component InstantiationComponent InstantiationComponent InstantiationComponent Instantiation 90


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Ports can be mapped to signals by Positional or mixed

notation.

U1: ND2 port map ( IN1,IN2, TEMP_1 ); --positionalU1: ND2 port map (IN1,IN2, C => TEMP1); --

9 0

Named association is preferred because it makes the codemore readable and pins can be specified in any order.

All positional connections should be placed before any namedconnections.

Generate StatementGenerate StatementGenerate StatementGenerate Statement 91


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Concurrent statements can be conditionally selected or

replicated using generate statement.

Used to create multiple copies of components, processes, or

9 1

oc s.

For ex: Provides a compact description of regularstructures such as memories, registers, and counters.

No simulation semantics are associated.



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Two forms of generate statement

forgenerate

Number of copies is determined by a discrete range

ifgenerate

Zero or one copy is made, conditionally

9 2

Note:Range must be a computableinteger, in either of these

forms:

integer_expression to integer_expression

integer_expression downto integer_expression

Each integer_expression evaluates to an integer.



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Example:

9 3

Generate StatementGenerate StatementGenerate StatementGenerate Statement94


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Example:

9 4



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ExampleExampleExampleExample::::

9 5

Generate StatementGenerate StatementGenerate StatementGenerate Statement96


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Example:

9 6

GENERIC


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It provides a powerful mechanism in VHDL to modelparameterized designs.

Syntex:-entityentityentityentity entity_name is

genericgenericgenericgeneric (

9 7

const. name: const. type;

..

.;

port (signal_name : mode signal_type;

);EndEndEndEnd entity_name;

EXAMPLE OF GENERIC STATEMENT WITH GENERATE

STATEMENT

Library ieee;


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Library ieee;

Use ieee.std-logic_1164;

EntityEntityEntityEntity inv1 isisisis

GenericGenericGenericGeneric ( two : positive := 5 );

portportportport ( I :in bit_vector (two downto 0);o :out vector (two downto 0));

endendendend inv1;

9 8

ArchitectureArchitectureArchitectureArchitecture bus_inv1 ofofofofinv1 isisisis

component inv is

port b ( I : in bit;

o :out bit);

End component;

begin

x : for I in 0 to two generate

u : inv port map (I (i),o(i));End generate;End generate;End generate;End generate;

End bus_inv1;

Wait StatementWait StatementWait StatementWait Statement99


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Wait statement

Suspends the execution of a process or

procedure until some conditions aremet.

9 9

Three basic forms: wait on sensitivity clause

wait until condition clause

wait for timeout clause

Wait StatementWait StatementWait StatementWait Statement100


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Wait statement at the end of the process is equivalent to thesensitivity list at the beginning of the process. -----Why?

Example:

process -- No Sensitivity list

begin

1 0 0

if ( clk'event and clk = '1')

thenq


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Illegal coding

Processes with a wait Statement

and Sensitivity list are illegal.

Example:

process ( clk )

1 0 1

begin

wait until clk = 1;

q


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y p p

active edge of the clock when reset is held active.

process (CLK)

begin

if ( CLK event and CLK =

1 0 2

if ( RST = 1 ) then

Q


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Asynchronous Reset : Flip-flops are cleared as

soon as reset is asserted.

process (CLK, RST)

be in

1 0 3

if ( RST = 1 ) then

Q


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Any assignment within clock statement will

generate a Flip-flop and

all other combinational circuitry will be created at the D

input of the Flip-flop.

1 0 4

beginif (clk'event and clk = '1')

then

out1


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Incompletely specified Conditional expression

infers a latch.

Latch is a combinational circuit which necessarilyhas feedback to hold the output to previous value

for the uns ecified states/conditions.

1 0 5

Avoid the inference of latches in synchronous

designs. As latches infer feedback and they causedifficulties in timing analysis and test insertion

applications. Most synthesizers provide warnings

when latches are inferred.

Hardware modeling ExamplesHardware modeling ExamplesHardware modeling ExamplesHardware modeling Examples LatchLatchLatchLatch

Completely specifiedConditional expression.

106


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incompletely specified

Conditional expression.

process (en,a)begin

Conditional expression.

process (en,a)

begin

if en='1 thenout1


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Need:

1 0 7

ConfigurationConfigurationConfigurationConfiguration 108


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Configuration declaration is used to select one of the many

architectures that an entity may have.

Syntax:

1 0 8

_ _

for architecture_name

for instantiation:component_name

use library_name.entity_name(architecture_name);

end for;

end for;end configuration_name;

PACKAGE

A file containing definations of objects


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A file containing definations of objects.

Objects can be used in other programs.

All objects are global.

Syntex :Syntex :Syntex :Syntex :----

packagepackagepackagepackage package_name isisisis

1 0 9

signal/constant declarations

function/procedure declarationendendendend package_name;

package bodypackage bodypackage bodypackage body package_name isisisis

type declarations

signal/constant declarations

function/procedure definations

endendendend package_name;

Use of package :-


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Use of package :

1 1 0

useuseuseuse work.package_name.allallallall;

Subprograms


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Include :

functionsfunctionsfunctionsfunctions and proceduresproceduresproceduresprocedures

Commonly used pieces of code

Can be placed in a library, and then reused and

1 1 1

s are among var ous pro ects

Abstract operations that are repeatedly performed Type conversions

Use only sequential statements, the same as

processes

Typical Locations of Subprograms

PACKAGELIBRARY


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PACKAGE BODYLIBRARY

global

ENTITY

1 1 2

PROCEDURE

ARCHITECTURE

Declarative part

local for a given architectu

local for all architectures

of a given entity


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1 1 3

Functions basic features

FunctionsAlways return a single value as a result


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Always return a single value as a result

Are called using formal and actual parameters the

same way as componentsNever modify parameters passed to them

1 1 4

generics) and signals (including ports);

variables are not allowed; the default is aCONSTANT

when passing parameters, no range specificationshould be included (for example no RANGE for

INTEGERS, or TO/DOWNTO forSTD_LOGIC_VECTOR)

are always used in some expression, and not calledon their own

FUNCTION/PROCEDURE

FUNCTIONFUNCTIONFUNCTIONFUNCTION


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FUNCTIONFUNCTIONFUNCTIONFUNCTION

It always return a value.

It is used to generalised a perticular program for the use of otherprogram.

Syntax:-

functionfunctionfunctionfunction function_name (

1 1 5

signal names :signal tupe;

..

)returnreturnreturnreturn return_type isisisis

type declarations

const. / variable declarations

.

begin

sequential statements

endendendend function_name;

Type conversion function (1)

LIBRARY ieee;


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USE ieee.std_logic_1164.all;

----------------------------------------

---------------------------------------

------------------

1 1 6

PACKAGE my_package IS

FUNCTION conv_integer (SIGNAL vector:STD_LOGIC_VECTOR)

RETURN INTEGER;

END my_package;----------------------------------------

---------------------------------------

------------------


PACKAGE BODY my_package ISFUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR)


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RETURN INTEGER;

VARIABLE result: INTEGER RANGE 0 TO 2**vectorLENGTH -

1;

VARIABLE carry: STD_LOGIC;

BEGIN

1 1 7

IF vector vector HIGH = 1 THEN result:=1;

ELSE result := 0;

FOR i IN (vectorHIGH-1) DOWNTO (vectorLOW) LOOP

result := result*2;

IF (vector(i) = 1 THEN result := result+1;

END IF;

RETURN result;

END conv_integer;

END my_package;


LIBRARY ieee;USE ieee.std_logic_1164.all;


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_ g _

USE work.my_package.all;USE work.my_package.all;USE work.my_package.all;USE work.my_package.all;

------------------------------------------------

-------------------------------------------------

1 1 8

_

PORT ( a: IN STD_LOGIC_VECTOR (0 TO 3);

y: OUT INTEGER RANGE 0 TO 15);

END conv_int2;

------------------------------------------------

----------------------------------------------

---

ARCHITECTURE my_arch OF conv_int2 IS

BEGIN

y


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1 1 9

Procedures basic features

Procedures do not return a valuedo not return a valuedo not return a valuedo not return a value


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are called using formal and actual parameters the same way ascomponents

maymaymaymay modify parametersmodify parametersmodify parametersmodify parameters passed to them each parameter must have a mode: IN, OUT, INOUTeach parameter must have a mode: IN, OUT, INOUTeach parameter must have a mode: IN, OUT, INOUTeach parameter must have a mode: IN, OUT, INOUT

1 2 0

,(including ports), and variables;variables;variables;variables;the default for inputs (mode in) is a constant, the default fordefault fordefault fordefault foroutputs (modes out and inout) is a variableoutputs (modes out and inout) is a variableoutputs (modes out and inout) is a variableoutputs (modes out and inout) is a variable

when passing parameters, range specification should be includedrange specification should be includedrange specification should be includedrange specification should be included(for example RANGE for INTEGERS, and TO/DOWNTO forSTD_LOGIC_VECTOR)

Procedure calls are statements on their ownProcedure calls are statements on their ownProcedure calls are statements on their ownProcedure calls are statements on their own

PROCEDURE :-


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It is alternate to function .it doesnot return any value.

1 2 1

EXAMAPLE OF FUNCTIONUse library ieee;use ieee.std_logic_1164.all;

use ieee.std-logic_unsigned.all;


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package fun is

function sum1 ( x,y :in std-lofic_vector (1 downto 0))

return std_logic_vector;

end fun;package body fun is

function sum1 ( x,y :in std-lofic_vector (1 downto 0))

1 2 2

re urn s _ og c_vec or s

variable temp : std_logic_vector(2 downto 0);variable x1,y1 : std_logic_vector(2 downto 0);

begin

x1 := 0 & x;

y1 := 0 & y;

temp := x1 +y1;

return (temp);end fun;

Use library ieee;

use ieee.std_logic_1164.all;


Use work.fun.all;

Entity fun2 is


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port (a,b :in std_logic_vector(1 downto 0);

sum : out std_logic_vector(2 downto 0))

End fun2;

Architecture fun2_beh of fun2 is

begin

1 2 3

sum


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package pro isprocedure sum2 ( x,y :in std-lofic_vector (1 downto 0);

signal z :out std_logic_vector(2 downto0))

1 2 4

package body pro is

procedure sum2 ( x,y :in std-lofic_vector (1 downto 0);

signal z :out std_logic_vector(2 downto0))

is

variable x1,y1 : std_logic_vector(2 downto 0);

begin

x1 := 0 & x;y1 := 0 & y;

z1


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Use work.pro.all;

Entity pro2 is

1 2 5

port (a,b :in std_logic_vector(1 downto 0);

sum : out std_logic_vector(2 downto 0))

End profun2;

Architecture pro2_beh of fun2 is

begin

sum2 (a,b,sum) ;End pro2_beh;


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1 2 6

And Gate

Library ieee;


127/187

y ;

Use ieee.std_logic_1164.all;

Use ieee.std_logic_airth.all;

. _ _ .

entity and1 is

Port(a:in std_logic;

b:in std_logic;

c1:out std_logic;End and1;

Architechture behaviuoral of and1 is


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Begin

Process(a,b) Begin

C


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y



. _ _ .

entity nand1 is


b:in std_logic;

c1:out std_logic;End nand1;

Architechture dataflow of nand1 is


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Architechture dataflow of nand1 is

Begin

C


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. _ _ .

entity xor2 is

Port(p:in std_logic;

q:in std_logic;

r:out std_logic);End adder;

Architechture behavioural of xor2 is


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Begin

r


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Use ieee.std_logic_unsigned.all;

entit adder is

Port(a:in std_logic_vector(3 downto 0);

b:in std_logic_vector(3 downto 0);c1:in std_logic;

S:out std_logic_vector(3 downto 0);

C0:out std_logic;

End adder;

Architechture behavioural of adder is

Component fa isPort(a:in std_logic;


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b:in std_logic;

c1: in std_logic;

_

c :out std_logic);End component;

Signal ca :std_logic_vector(4 downto);

Begin

Ca(0)


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Ioop1:for i in 0 to 3 generate

F:fa port mapa i b i ca i a i ca i+1 ;

End generate loop1;

Co


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. _ _ .

entity xor1 is

Port(p:in std_logic;

q:in std_logic;

r:out std_logic);End xor1;

Architechture behavioural of xor1 is


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Component and1 is

Port(a,b:in std_logic;c:out std_logic);

Component halfadder isPort (a,b:in std_logic;

s,c:out std_logic);

End component;

Begin


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U1:and1 port map(a,b,carry);

U2:xor1 portmap(a,b,sum);

End behaviural;

Full Adder

Library ieee;

Use ieee std logic 1164 all;


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entit fa is


b:in std_logic;c1:in std_logic;

S:out std_logic;

C:out std_logic);

End fa;

Architechture behavioural of fa is

Signals1,s2,s3:std logic;


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Signals1,s2,s3 std_logic;

Component ha is

Port(a,b:in std_logic;

s c:out std lo ic ;_

End component;

Begin X:ha port map(a,b,s1,s2);

y:ha port map(s1,c1,s,s3);

C


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Use ieee.std_logic_airth.all;. _ _ .

entity mux is


sel:in std_logic_vector(3 downto 0);

Op:out std_logic;End mux;

Architechture behavioural of mux is

Begin


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Begin

Process(a,sel) Begin

When0000=>

op

op

op


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When0011=>

op


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When1000=>

op

When1010=>

op

op

op

op


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When 1110 =>

op


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entit kff is

Port(j:in std_logic;

k:in std_logic;clk:in std_logic;

q:out std_logic;

q1:out std_logic);

End jkff;

Architechture behavioural of jkff is

Begin


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Prcess(j,k,clk) Variable var:std_logic;

If(clkevent and clk=1)then

If (j=0 and k=1)then var:=0;

elsIf (j=1 and k=0)then

Var:=1;


Var:=not(var);

( )


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Var:=var;

Else null;

End if;

End if; Q


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Use ieee.std_logic_airth.all; Use ieee.std_logic_unsigned.all;

Port(t:in std_logic;

clk:in std_logic;q:out std_logic;

q1:out std_logic);

End tff;

Architechture behavioural of tff is

Begin


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Begin

Process(t,clk)

, _

BeginIf(clkevent and clk=1)then

If(t=1)then

Q


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. _ _ .

entity dff is

Port(d:in std_logic;

clk:in std_logic;

q:out std_logic);End dff;

1 5 1

Architechture behavioural of dff is

Begin

Process(d,clk)

Variable var:std_logic;


152/187

Begin


If(d=0)then

var:=1;

else

null;

end if;

end if;

Q


153/187



Port(r:in std_logic;

clk:in std_logic;count:out std_logic_vector(2 downto 0);

End modc;

Architechture behavioural of modc is

Begin

Prcess(r clk)


154/187

Prcess(r,clk)

Variable var:std_logic_vector(2 down to 0); Be in

If (clkevbent and clk=1)then

If (r=1)then Var:=000;

Else

Var:=var+1;

End if;

If(var:=111)then

Var:=000;


155/187

Var: 000 ;

End if;

End if;

Count


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Generic(words:integer:=8;

Bits:integer:=8); Port(adder:in integer range0 to(words-1)

data:out std_logic_vector((bits-1)

downto 0); End rom;

Architechture behavioural of rom is

Type array1 is array(0 to (words-1))ofstd logic vector((bite-1)down to 0);


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_ g _ (( ) )

Constant memory:array1:=(00000001;) 00000011;

00000111;

00001111;

00011111;

00111111;

01111111;

11111111); Begin

Process(addr)

Begin


158/187

Begin

Data


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Port(r:in std_logic;

clk:in std_logic;updown:in std_logic;

count:out std_logic_vector(3 downto 0);

End udcounter;

Architechture behavioural of udcounter is

Begin

Process(r,updown,clk)


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Variable var:std_logic_vector(3 downto 0); Begin

If (r=1)then

var:=0000; elsIf (updown=1)then

Var:=var+1;

Elsif(updown=0)then

Var:=var-1;

Else

Null;

End if;


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End if;

If(var=1010or var=1111)then

End if;

End if; Count


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Use ieee.std_logic_airth.all;Use ieee.std_logic_unsigned.all;

entity twisted is

Port(r:in std_logic;clk:in std_logic;

count:out std_logic_vector(3 downto

0));End twisted;

Architechture behavioural of twisted is

Signal s:std_logic_vector(2 downto 0);


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Begin

Begin

If(clkevent and clk=1)

If(r=1)then

S


164/187

End if;

Case s is

When000=>;count;count;count;countcount;count


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When110=>;countnull;

End case ;

End process;

End behavioural;

Ram

Library ieee;




166/187

Use ieee.std_logic_unsigned.all; entity ram is

Bits:integer:=4);

Port(clk:in std_logic;Wr_en:in std_logic;

detain:in std_logic_vector(bits-1) downto 0);

Addr:in integer range 0 to (words-1);

Dataout:out std_logic_vector(bits-1)downto 0));End ram;

Architechture behavioural of ram is

Type array1 is array(0 to (words-1)of


167/187

Std_logic_vector(bits-1)downto 0);

BeginProcess(clk,wr_en,datain,addr)

Begin


If(wr_en=1)then

Memory(addr


168/187

Dataout


169/187

Use ieee.std_logic_unsigned.all; entit srla is

Port(s:in std_logic;

r:in std_logic;clk:in std_logic;

q:out std_logic;

q1:out std_logic);

End srla;

Architechture behavioural of srla is

Signal var:std_logic:


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Begin =

If(s=0 and r=1)then

Var


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Var


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Use ieee.std_logic_unsigned.all; entit srla nand ate is_

Port(s:in std_logic;

r:in std_logic;clk:in std_logic;

q:out std_logic;

q1:out std_logic);

End srla_nandgate;

Architechture behavioural ofsrla_nandgate is

Si l b d d l i


173/187

Signal a,b,c,d:std_logic;Com onent nand1 is

port(a,b:in std_logic;

C:out std_logic);End component;

Begin

E;nand1 port map(s,clk,a);

F:nand1 port map(r,clk,c);

G:nand1 port map(a,d,b);

( )


174/187

H:nand1 pot map(c,b,d);

Q


175/187


entity siso is


clk:in std_logic;

b:out std_logic);

End siso;

Architechture behavioural of siso is

Signal s:std_logic_vector(3 downto 0):

Begin

Process(a,clk)

begin


176/187

begin If(clkevent and clk=1)then

=

S(2)


177/187


entity parity is


pg:out std_logic;

pc:out std_logic);

End parity;

Architechture behavioural of parity is

Signal s1:std_logic_vector;

Begin

With a select

S1


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S1


179/187

entity queue is numeric(bits: integer:=4;

=

Port(clk:in std_logic;

r_w: in std_logic;

datain: in std_logic_vector(bits-1) downto 0);dataout: out std_logic_vector(bits-1)downto 0);

pc:out std_logic);

Empty : out std_logic;

Full: out std_logic);

End queue;

Architectural behavioral of queue is

Type stack1 is array(0 to (words)) of

Std_logic_vector((bits-1)downto 0); Signal s1,s2: integer range 0 to (words);

Signal memory: stack1;


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Signal memory: stack1; Begin

Process(clk,r_w:datain)

Begin

If(clkevent and clk =1)then If(r_w=0)then If(s1=8)then Full


181/187

End if; Else

If(s1=0 or s2 =8) then

Empty


182/187

Null;

End if;

End process;End behavioral;

1 8 2

Q1


183/187

End if;

End if;

End process;End behavioural;

Stack

Library ieee;



Use ieee.std_logic_unsigned.all; entity stack is


184/187

entity stack is

words:integer:=8);

Port(clk:in std_logic;

r_w: in std_logic;

datain: in std_logic_vector(bits-1) downto 0);

dataout: out std_logic_vector(bits-1)downto 0);

pc:out std_logic);

Empty : out std_logic;

Full: out std_logic);

End stack; 1 8 4

Architectural behavioral of queue is

Type stack1 is array(0 to (words)) of

Std_logic_vector((bits-1)downto 0);

Signal s: integer range 0 to (words);

Signal memory: stack1;


185/187

Begin

Process(clk,r_w:datain)

Begin

If(clkevent and clk =1)then

If(r_w=0)then

If(s1=8)then

Full


186/187

Else

Empty


187/187

Null;

End if;

End process;End behavioral;

1 8 7

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