Chapter-1 Introduction 1.1 Introduction VGA stands for Video Graphics Array, Video Graphics Array (VGA) refers specifically to the display hardware first introduced with the IBM PS/2 line of computers in 1987. In this design we consider a basic 8 colour display of 640 by 480 resolution using CRT (cathode ray tube) interface. 1.2 CRT working Following figure shows basic diagram of monochrome CRT FIG 1. CATHODE RAY TUBE In CRT these are deflection coils which make the electron beam to move in vertical and horizontal direction. In this project by VHDL we have to design this vertical and 1
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Chapter-1 Introduction
1.1 IntroductionVGA stands for Video Graphics Array, Video Graphics Array (VGA) refers specifically
to the display hardware first introduced with the IBM PS/2 line of computers in 1987.
In this design we consider a basic 8 colour display of 640 by 480 resolution using CRT
(cathode ray tube) interface.
1.2 CRT workingFollowing figure shows basic diagram of monochrome CRT
FIG 1. CATHODE RAY TUBE In CRT these are deflection coils which make the electron beam to move in vertical and
horizontal direction. In this project by VHDL we have to design this vertical and
horizontal counters to control the direction of electron beam and mafe it on – of when we
want to display. Image on next page shows how an electron beam scans full screen to
display objects.
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1.3 Display of objects on CRT Screen
FIG.2 ELECTRON BEAM MOVEMENT
The monitor's internal oscillators and amplifiers generate sawtooth waveforms to control the
two deflection coils. For example, the electron beam moves from the left edge to the right
edge as the voltage applied to the horizontal deflection coil gradually increases. After
reaching the right edge, the beam returns rapidly to the left edge (i.e., retraces) when the
voltage changes to 0. Two external synchronization signals, hsync and vsync, control
generation of the sawtooth waveforms. These signals are digital signals.
The basic operation of a colour CRT is similar except that it has three electron beams, which
are projected to the red, green, and blue phosphor dots on the screen. The three dots are
combined to form a pixel. We can adjust the voltage levels of the three video input signals to
obtain the desired pixel colour
TABLE 1 bit vga colour combination
REG GREEN BLUE COLOUR
0 0 0 BLACK
0 0 1 BLUE
0 1 0 GREEN
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0 1 1 CYAN
1 0 0 RED
1 0 1 MEGANTA
1 1 0 YALLOW
1 1 1 WHITE
.
This scanning of electron beam is done upto 30 or 60 times in a second to make display in a
continuous manner
1.4 Applications of VGA
Vga is most important component of desktop monitors, simple T.Vs and other displays.
These can be used to from static to moving objects.
1.5 Objective of the Project
Main objective of the project is as:
1. To understand the working of vga
2. To design and implement a simple VGA in VHDL and to observe its output on
minitor using Spartan 3 FPGA kit.
3. To enhance design skills in vhdl.
1.6 Organization of project work
Chapter 2 discusses a brief about a internal description of vga, FPGA and tools used. In
chapter 3 we ll show the present work , its simulations and RTLs, giving detailed description
of our work. Then Chapter 4 discusses the Conclusions and future scope of this project.
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Chapter-2 Literature Review
Basic schematic for vga controller is as in figure.
FIG 3. SIMPLE BLOCK DIAGRM OF VGA
Here the work of synchronization circuit is to direct the electron beam to a particular position
on the screen. The pixel generation circuit decides at which pixel we have to display data and
this cumulative data goes to the input of vga port.
2.1 VGA synchronization
The video synchronization circuit generates the hsync signal, which specifies the required
Time to traverse (scan) a row, and the vsync signal, which specifies the required time to
traverse (scan) the entire screen. Subsequent discussions are based on a 640-by-480 VGA
screen with a 25-MHz pixel rate, which means that 25M pixels are processed in a second.
Note that this resolution is also known as the VGA mode.
The screen of a CRT monitor usually includes a small black border. The middle rectangle is
the visible portion. Note that the coordinate of the vertical axis increases downward. The
coordinates of the top-left and bottom-right corners are (0,0) and (639,479), respectively
entity test is Port ( clk,reset : in STD_LOGIC; h_sync,v_sync : out STD_LOGIC; rgb : out STD_LOGIC_VECTOR (02 downto 0));end test;
architecture Behavioral of test iscomponent vga_sync is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; x,y : out STD_LOGIC_VECTOR (09 downto 0);
h_sync,v_sync,video_on : out std_logic);end component;component ch_gen is Port ( clk : in STD_LOGIC; video_on : in STD_LOGIC; p_x, p_y : in STD_LOGIC_VECTOR (09 downto 0); rgb : out STD_LOGIC_VECTOR (02 downto 0));end component;signal pixel_x,pixel_y: std_logic_vector(9 downto 0) ;signal video_on: std_logic ;signal rgb_reg : std_logic_vector(2 downto 0):="000" ;
beginsync:vga_sync port map(clk=>clk,reset=>reset,x=>pixel_x,y=>pixel_y,h_sync=>h_sync,v_sync=>v_sync,video_on=>video_on);font:ch_gen port map(clk,video_on,pixel_x,pixel_y,rgb_reg);process(clk)beginif (clk' event and clk='1')then rgb<=rgb_reg;end if;end process; end Behavioral;
2. For synchronization circuit
entity vga_sync is Port ( clk,reset : in STD_LOGIC; x,y: out STD_LOGIC_vector(9 downto 0);
video_on,h_sync,v_sync: out std_logic); end vga_sync;architecture counter of vga_sync issignal mod2,mod2_next,p_tick,h_end : std_logic ;
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signal count,count_next,count1,count1_next: integer range 0 to 999;beginprocess(clk,reset)beginif(reset='1') thenmod2<='0';count<=0;count1<=0;elsif(clk' event and clk='1') then mod2<=mod2_next;count<=count_next;count1<=count1_next;end if;end process;process(mod2)beginmod2_next<=mod2;p_tick<='0';if(mod2='1') thenmod2_next<='0';p_tick<='1';elsemod2_next<='1';p_tick<='0';end if;end process;-- mod 800process(count,p_tick)begincount_next<=count;if(p_tick='1') thenif(count=799) thencount_next<=0;h_end<='1';else count_next<=count+1;h_end<='0';end if;end if;end process;-- mod-525process(p_tick,h_end,count1)begincount1_next<=count1;if(p_tick='1' and h_end='1') thenif(count1=524) thencount1_next<=0;elsecount1_next<=count1+1;end if;end if;end process;x <= conv_std_logic_vector(count,10); y <= conv_std_logic_vector(count1,10); h_sync<='1' when(count>=656) and (count<=751)
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else '0';v_sync<='1' when(count1>=490) and (count1<=491) else '0';
video_on<='1' when(count<640) and (count1<480) else '0'; end counter;
3. For character generation circuit
entity ch_gen is Port ( clk : in STD_LOGIC; video_on : in STD_LOGIC; p_x, p_y : in STD_LOGIC_VECTOR (09 downto 0); rgb : out STD_LOGIC_VECTOR (02 downto 0));end ch_gen;
architecture char_gen of ch_gen iscomponent font_rom isport (clk : in std_logic;addr : in std_logic_vector(7 downto 0);data : out std_logic_vector(7 downto 0));end COMPONENT;component mux8_1 is Port ( s : in STD_LOGIC_VECTOR (02 downto 0); x : in STD_LOGIC_VECTOR (07 downto 0); y : out STD_LOGIC);end component;signal rom_addr :std_logic_vector(7 downto 0);signal char_addr :std_logic_vector(3 downto 0);signal row_addr :std_logic_vector(3 downto 0);signal bit_addr :std_logic_vector(2 downto 0);signal font_word :std_logic_vector(7 downto 0);signal font_bit,text_on :std_logic ;beginfont_unit: font_rom port map(clk=>clk, addr=>rom_addr , data=>font_word);char_addr<= p_y(5 downto 4) & p_x(4 downto 3);rom_addr<= char_addr & row_addr;row_addr<= p_y(3 downto 0);bit_addr<= p_x(2 downto 0);m1:mux8_1 port map(bit_addr,font_word,font_bit);
text_on<= font_bit when p_x(9 downto 5)="01001" and
entity font_rom isport (clk : in std_logic;addr : in std_logic_vector(7 downto 0);data : out std_logic_vector(7 downto 0));end font_rom;
architecture arch of font_rom issignal addr_reg : integer range 0 to 255;type rom_type is array (0 to 255) of std_logic_vector(7 downto 0);constant rom: rom_type:=( --zero - 0 h