VerilogHDL_Utkarsh_kulshrestha

A Presentation on VLSI Technology

BY:-UTKARSH KULSHRESTHA

CONTENTS

Introduction to VLSIHardware description

language Verilog codingVending machine

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VLSI

VLSI is very large scale integration technology.

It is related to the chip designing. Chip designing is comprises of two

areas:-

1. FRONT END

2. BACK END VLSI uses CMOS technology

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VLSI

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BJT-PNP

BJT-NPN

MOSFET

PMOS

NMOS

CMOS

Hardware Description Languages

Basic idea is a programming language to describe hardware

Synthesis tools allow direct implementation from HDL code.

Combined with modern Field Programmable Gate Array chips large complex circuits (100000s of gates) can be implemented.

There are many HDL’s as:-

1. ABEL

2. AHDL

3. VHDL

4. Verilog HDL

5. System Verilog

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Verilog HDL

Launched in 1984 by CADENCE.Verilog is Unlike VHDL is a case

sensitive language and uses lower case.

It is a CONCURRENT language.COMPLEXITY of Verilog is low.Only used for DIGITAL DESIGNS.

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Module declaration

Module

Circuit

Input

X

Y

Z

Output

O

Wire

module sample (X,Y,Z,O);

input X,Y,Z;output O;

// Describe the circuit using logic symbols assign O = (X^Y)&Z;

endmodule

Module name

Data Types

Nets and Registers Vectors Integer, Real, and Time Register

Data Types Arrays Memories Parameters Strings

Verilog HDL

Operators Arithmetic:*,+,-, /,% Relational<,<=,>,>=,==, != Bit-wise Operators

• Not: ~ • XOR: ^• And : & 5’b11001 & 5’b01101 ==>

5’b01001• OR: | • XNOR: ~^ or ^~

Logical OperatorsReturns 1or 0, treats all nonzero as 1

• ! : Not • && : AND 27 && -3 ==> 1• || : OR

reg [3:0] a, b, c, d;wire[7:0] x,y,z;parameter n =4;

c = a + b;d = a *n;

If(x==y) d = 1; else d =0;

d = a ~^ b;

if ((x>=y) && (z)) a=1; else a = !x;

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Operators

Reduction Operators:Unary operations returns single-bit values• & : and• | :or• ~& : nand• ~| : nor• ^ : xor• ~^ :xnor Shift OperatorsShift Left: <<

Shift right: >> Concatenation Operator

{ } (concatenation)

{ n{item} } (n fold replication of an item) Conditional OperatorImplements if-then-else statement (cond) ? (result if cond true) : (result if cond false)

module sample (a, b, c, d);

input [2:0] a, b;

output [2;0] c, d;

wire z,y;

assign z = ~| a;

c = a * b;

If(a==b) d = 1; else d =0;

d = a ~^ b;

if ((a>=b) && (z)) y=1;

else y = !x;

assign d << 2; //shift left twice

assign {carry, d} = a + b;

assign c = {2{carry},2{1’b0}};

// c = {carry,carry,0,0}

assign c= (inc==2)? a+1:a-1; 10

Verilog Coding Styles

Gate level modellingDataflow modellingBehavioral modellingStructural modelling

Gate level modelling

The gate level structure of digital design is required.

It requires the number of gates in the design. It also requires the way the gates are connected. The keywords defined for gates are as:-

AND XOR

OR XNOR

NOT BUF

NAND BUFIF1

NOR BUFIF0

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Example:Gate level modelling

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Module gatelevel(A,B,C,x,y);Input A,B.C;Output x,y;

Wire e;And(e,A,B);Not(y,C);Or(x,e,y);

Endmodule;

Dataflow modelling

The flow of data should be known from one point to another.

It works on the Boolean expressions.

ASSIGN keyword is used to drive the values.

assign y=a&b;

Usually Boolean operators are used for dataflow modelling and only the output equations are necessary for designing.

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Example:Dataflow modelling 4-bit Adder with instanciation Step 1: build a 1-bit full adder as a module

S = (a) XOR (b) XOR (Cin ) ; ( S = a^b^Cin)

Cout = (a&b) |(Cin&(a+b))

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module FA_1bit (S,Cout,a,b,Cin);begin input a,b,Cin;Output S, Cout;

assign Sum = a^b^Cin;assign Carry = (a&b) | (Cin&(a^b));

endmodule

Module add_1bit

4-bit Adder Step 2: initiate 4 instances of FA_1bit module

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1-bit Full

Adder

A0B0

Cin

S0

1-bit Full

Adder

A1B1

S1

1-bit Full

Adder

A2B2

S2

1-bit Full

Adder

A3B3

S3

Cout

The inputs and the output are 4-bits wide

module FA_4bits (S,Cout,A,B,Cin);input [3:0] A, B;input Cin;output [3:0] S;output Coutwire Cout0, Cout1, Cout2

FA_1bit FA1(S[0], Cout0,A[0],B[0],Cin);FA_1bit FA1(S[1], Cout1,A[1],B[1],Cout0);FA_1bit FA1(S[2], Cout2,A[2],B[2],Cout1);FA_1bit FA1(S[3], Cout,A[3],B[3],Cout2);endendmodule;

Cout0Cout1Cout2

we need wires to propagate the carry from one stage to the nextyou may name the

instances with any name, but you have to maintain the order of the inputs and outputs

Behavioral modelling

The behavior of the circuit should be known in the terms of its inputs and outputs.

This modelling is semi-concurrent in nature.

It uses conditional statements just like in C as “if-else” and “case” statements.

Begin….end statements are used as for sequential execution.

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Example:D Flip-flop with Synchronous reset and Enablealways@(posedge clk)

begin

if (rst) a<=0;

else if (enable) a<=b;

endQ

D

CLKclk

Aenable EN

rstB

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D Flip-Flop with Asynchronous Resetalways@(posedge clk or negedge

rst)

begin

if (!rst) a<=0;

else a<=b;

endQ

D

CLKclk

A

B

rst

clr

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Structural coding

It is basically not a coding style. It is used to connect behavioral

designs components to design more complex circuits.

The components of huge circuitry are designed separately.

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Vending machine

It is based on FSM.

FSM is the heart of any digital design.

According to the input state transition occurs.

The machine has four states like coke,mango,orange and lime with an initial state.

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Vending machine

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Vending machine

InitialState

Insert coin

Enterproduc

t

MangoState 1

orangeState 4

limeState 3

cokeState 2

Standard Form for a Verilog FSM// state flip-flops

reg [2:0] state, nxt_st;

// state definitions

parameter reset=0,S1=1,S2=2,S3=3,..

// NEXT STATE CALCULATIONS

always@(state or inputs or ...)

begin

…

next_state= ...

…

end

// REGISTER DEFINITION

always@(posedge clk)

begin

state<=next_state;

end

// OUTPUT CALCULATIONS

output= f(state, inputs)

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Simulation for vending machine

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THANK YOU

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