10M11D5716 SIMULATION LAB 1 EXPERIMENT: 1 LOGIC GATES AIM: To design all the logic gates using dataflow modeling style and verify the functionalities along with their synthesis and simulation reports. TOOLS USED: Xilinx 9.2i Hardware Tool. DESCRIPTION OF THE MODULE: NOT GATE: Not is a unary operator. It is also called as an Inverter .The output is the complement of the input. AND GATE: The output of the AND gate is logic one only when all the inputs are equal to logic one .An N-input and gate has N inputs and 1 output. OR GATE: Or gate output is logic one if any one of the inputs to the gate is logic one. N-input or gate has N inputs and 1output. NAND GATE: NAND gate output is logic 1 when any one of the input is logic 0.An N- input NAND gate has N inputs and one output. NAND gate is identical to and gate connected to an inverter. NOR GATE: NOR gate is nothing but a combination of OR gate and INVERTER .NOR gate output is logic one only when all the inputs are equal to logic zero. An N- input NOR gate is having N inputs and one output. XOR GATE: The output of XOR gate is logic zero when all the inputs are same. XNOR GATE: The output of XNOR gate is logic one only when both the inputs are at logic one. XNOR gate is nothing but the XOR gate followed by an INVERTER. TRUTH TABLE: a b Y[0] (not) Y[1] (and) Y[2] (or) Y[3] (nand) Y[4] (nor) Y[5] (xor) Y[6] (xnor) 0 0 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 1 0 1 1 0 0 0 1
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10M11D5716 SIMULATION LAB
1
EXPERIMENT: 1 LOGIC GATES
AIM: To design all the logic gates using dataflow modeling style and verify the
functionalities along with their synthesis and simulation reports.
TOOLS USED: Xilinx 9.2i Hardware Tool.
DESCRIPTION OF THE MODULE:
NOT GATE: Not is a unary operator. It is also called as an Inverter .The output is the
complement of the input.
AND GATE: The output of the AND gate is logic one only when all the inputs are equal
to logic one .An N-input and gate has N inputs and 1 output.
OR GATE: Or gate output is logic one if any one of the inputs to the gate is logic one.
N-input or gate has N inputs and 1output.
NAND GATE: NAND gate output is logic 1 when any one of the input is logic 0.An N-
input NAND gate has N inputs and one output. NAND gate is identical to and gate
connected to an inverter.
NOR GATE: NOR gate is nothing but a combination of OR gate and INVERTER .NOR
gate output is logic one only when all the inputs are equal to logic zero. An N- input
NOR gate is having N inputs and one output.
XOR GATE: The output of XOR gate is logic zero when all the inputs are same.
XNOR GATE: The output of XNOR gate is logic one only when both the inputs are at
logic one. XNOR gate is nothing but the XOR gate followed by an INVERTER.
// Inputs reg a; reg b; // Outputs wire [0:6] y; // Instantiate the Unit Under Test (UUT) logicgate_df uut ( .a(a), .b(b), .y(y) ); initial begin a = 0; b = 0;
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#10 a = 0; b = 1; #10 a = 1; b = 0; #10 a = 1; b = 1; end initial begin #50 $finish; end endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION: Basic logic gates NOT, AND, OR, NOR, NAND, XOR, XNOR are designed in dataflow,
behavioral models and outputs are verified using test bench.
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EXPERIMENT: 2 ADDERS
2.1. HALF ADDER
AIM: To design a half adder along with a verilog code in the dataflow model and verify
its functionality and check its simulation report.
TOOLS USED: Xilinx 9.2i Hardware Tool
DESCRIPTION OF THE MODULE:
A combinational circuit that performs the addition of two bits is called half adder.The
half adder operation needs two binary inputs (augends and addend bits)and two binary
outputs (sum and carry). The sum can range from 0 to 2 which require two bits to
express. The lower order bit may be named as half sum and the higher order bit may be
named as carry.
BLOCK DIAGRAM:
TRUTH TABLE:
a b carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
a, b are inputs and carry, sum are outputs
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VERILOG CODE: HALF ADDER USING DATAFLOW MODELING STYLE
`resetall
`timescale 1ns/1ps
module halfadder(a, b, sum, carry);
input a;
input b;
output sum;
output carry;
wire a,b;
assign sum= a^b;
assign carry=a&b;
endmodule
HALF ADDER TEST BENCH
`resetall
`timescale 1ns/1ps
module halfadder_bh_tb_v;
// Inputs
reg a;
reg b;
// Outputs
wire sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
halfadder_beh uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
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initial begin
// Initialize Inputs
a = 0;
b = 0;
#20 a=0; b=1;
#20 a=1; b=0;
#20 a=1; b=1;
end
initial
begin
#100 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION:
HALF ADDER is designed in behavioral and dataflow styles and output is verified
through a test bench.
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2.2 FULL ADDER
AIM: To design a FULL ADDER along with a verilog code in behavioral and dataflow
the two models and verify its functionality and check its simulation report.
TOOLS USED: Xilinx 9.2i Hardware Tool
DESCRIPTION OF THE MODULE:
The FULL ADDER is a combinational circuit that performs the arithmetic sum of three
input bits. It consists of three inputs and two outputs. A FULL ADDER can also be
implemented using two HALF ADDERS and one OR gate.
BLOCK DIAGRAM:
TRUTH TABLE:
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Where a, b, cin are the inputs and sum, carry are outputs
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VERILOG CODE: FULL ADDER USING DATAFLOW MODELING STYLE
output [0:3]s; output co; wire [0:3]a; wire [0:3]b; wire ci; reg [0:3]s; reg co; always@(a or b or ci) begin if(ci==1'b0) begin case({a,b}) 8'b00000000: begin s=4'b0000; co=1'b0;end 8'b00010001: begin s=4'b0010; co=1'b0;end 8'b00100010: begin s=4'b0100; co=1'b0;end 8'b00110011: begin s=4'b0110; co=1'b0;end 8'b01000100: begin s=4'b1000; co=1'b0;end 8'b01010101: begin s=4'b1010; co=1'b0;end 8'b01100110: begin s=4'b1100; co=1'b0;end 8'b01110111: begin s=4'b1110; co=1'b0;end 8'b10001000: begin s=4'b0000; co=1'b1;end 8'b10011001: begin s=4'b0010; co=1'b1;end 8'b10101010: begin s=4'b0100; co=1'b1;end 8'b10111011: begin s=4'b0110; co=1'b1;end 8'b11001100: begin s=4'b1000; co=1'b1;end 8'b11011101: begin s=4'b1010; co=1'b1;end 8'b11101110: begin s=4'b1100; co=1'b1;end 8'b11111111: begin s=4'b1110; co=1'b1;end endcase end else begin case({a,b}) 8'b00000000: begin s=4'b0001; co=1'b0;end 8'b00010001: begin s=4'b0011; co=1'b0;end 8'b00100010: begin s=4'b0101; co=1'b0;end 8'b00110011: begin s=4'b0111; co=1'b0;end 8'b01000100: begin s=4'b1001; co=1'b0;end 8'b01010101: begin s=4'b1011; co=1'b0;end 8'b01100110: begin s=4'b1101; co=1'b0;end 8'b01110111: begin s=4'b1111; co=1'b0;end 8'b10001000: begin s=4'b0001; co=1'b1;end 8'b10011001: begin s=4'b0011; co=1'b1;end 8'b10101010: begin s=4'b0101; co=1'b1;end 8'b10111011: begin s=4'b0111; co=1'b1;end 8'b11001100: begin s=4'b1001; co=1'b1;end
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8'b11011101: begin s=4'b1011; co=1'b1;end 8'b11101110: begin s=4'b1101; co=1'b1;end 8'b11111111: begin s=4'b1111; co=1'b1;end endcase end end endmodule
BIT 4 BINARY PARALLEL ADDER TEST BENCH
`resetall
`timescale 1ns/1ps
module bit4plabh_tb_v; // Inputs reg [0:3] a; reg [0:3] b; reg ci; // Outputs wire [0:3] s; wire co; // Instantiate the Unit Under Test (UUT) bit4pladbh uut ( .a(a), .b(b), .ci(ci), .s(s), .co(co) ); initial begin a = 4'b0000; b=4'b0000; ci=1'b0; #5 a = 4'b0001; b=4'b0001; ci=1'b0; #5 a = 4'b0010; b=4'b0010; ci=1'b0; #5 a = 4'b0011; b=4'b0011; ci=1'b0; #5 a = 4'b0100; b=4'b0100; ci=1'b0; #5 a = 4'b0101; b=4'b0101; ci=1'b0; #5 a = 4'b0110; b=4'b0110; ci=1'b0; #5 a = 4'b0111; b=4'b0111; ci=1'b0; #5 a = 4'b1000; b=4'b1000; ci=1'b0; #5 a = 4'b1001; b=4'b1001; ci=1'b0; #5 a = 4'b1010; b=4'b1010; ci=1'b0; #5 a = 4'b1011; b=4'b1011; ci=1'b0;
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#5 a = 4'b1100; b=4'b1100; ci=1'b0; #5 a = 4'b1101; b=4'b1101; ci=1'b0; #5 a = 4'b1110; b=4'b1110; ci=1'b0; #5 a = 4'b1111; b=4'b1111; ci=1'b0; #5 a = 4'b0000; b=4'b0000; ci=1'b1; #5 a = 4'b0001; b=4'b0001; ci=1'b1; #5 a = 4'b0010; b=4'b0010; ci=1'b1; #5 a = 4'b0011; b=4'b0011; ci=1'b1; #5 a = 4'b0100; b=4'b0100; ci=1'b1; #5 a = 4'b0101; b=4'b0101; ci=1'b1; #5 a = 4'b0110; b=4'b0110; ci=1'b1; #5 a = 4'b0111; b=4'b0111; ci=1'b1; #5 a = 4'b1000; b=4'b1000; ci=1'b1; #5 a = 4'b1001; b=4'b1001; ci=1'b1; #5 a = 4'b1010; b=4'b1010; ci=1'b1; #5 a = 4'b1011; b=4'b1011; ci=1'b1; #5 a = 4'b1100; b=4'b1100; ci=1'b1; #5 a = 4'b1101; b=4'b1101; ci=1'b0; #5 a = 4'b1110; b=4'b1110; ci=1'b1; #5 a = 4'b1111; b=4'b1111; ci=1'b1; end initial begin #200 $finish; end endmodule
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SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION:
4 BIT BINARY PARALLEL ADDER is designed in behavioral style and output is
verified through a test bench.
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EXPERIMENT: 4 DECODERS
4.1---- 2 TO 4 LINE DECODER AIM: To design a 2x4 decoder and to write its verilog code in dataflow, behavioral
models, verify the functionality and its output in the simulation report
TOOLS USED: Xilinx 9.2i Hardware Tool.
DESCRIPTION OF THE MODULE:
A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of unique output lines. The purpose of decoder is to generate ( or
less) minterms of n input variables. A 2 to 4 decoder generates all the minterms of two
input variables. Exactly one of the output lines will be one for each combination of values
of input variables.
BLOCK DIAGRAM
TRUTH TABLE:
a b D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Here a,b are two inputs and D0,D1,D2,D3 denote the outputs of the decoder which
implies minterms of two input variables.
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VERILOG CODE:
2X4 DECODER USING DATA FLOW MODELING STYLE
`resetall
`timescale 1ns/1ps
module decoder24df(a, b, y);
input a;
input b;
output [0:3] y;
wire a,b;
assign y[0]=(~a) & (~b);
assign y[1]=(~a)& (b);
assign y[2]=(a) & (~b);
assign y[3]= a & b;
endmodule
2 TO 4 LINE DECODER TEST BENCH:
`resetall
`timescale 1ns/1ps
module decoder24_tb_v;
// Inputs
reg a;
reg b;
// Outputs
wire [0:3] y;
// Instantiate the Unit Under Test (UUT)
decoder24df uut (
.a(a),
.b(b),
.y(y)
);
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initial begin
// Initialize Inputs
a=0;b=0;
#10 a=0; b=1;
#10 a=1; b=0;
#10 a=1; b=1;
end
initial
begin
#60 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION: 2 to 4 decoder has been designed using behavioral, dataflow models
are verified using Test Bench.
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4.2-----3X8 LINE DECODER
AIM: To design a 3*8 decoder and to write its verilog code in dataflow, behavioral
models, verify the functionality and its out put in the simulation report
TOOLS USED: Xilinx 9.2i Hardware Tool.
DESCRIPTION OF THE MODULE:
A Decoder is a multiple-input ,multiple –output logic circuits and converts the coded
input into coded outputs ,the input and output codes are different. The input has fewer
bits than the output code. In 3 to 8 decoder 3 inputs are decoded into 8 outputs.
BLOCK DIAGRAM:
TRUTH TABLE:
a b c D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
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Here a,b,c are the inputs and D0 to D7 are the outputs.
3TO8 LINE DECODER USING DATA FLOW MODELING STYLE
`resetall
`timescale 1ns/1ps
module dec38data (a,b,c,dout);
input a,b,c;
output [0:7]dout;
assign dout[0]=(~a)&(~b)&(~c);
assign dout[1]=(~a)&(~b)&c;
assign dout[2]=(~a)&b&(~c);
assign dout[3]=(~a)&b&c;
assign dout[4]=a&(~b)&(~c);
assign dout[5]=a&(~b)&c;
assign dout[6]=a&b&(~c);
assign dout[7]=a&b&c;
endmodule
3 TO 8 DECODER USING BEHAVIORAL MODELING STYLE
`resetall
`timescale 1ns/1ps
module decoder38beh(a, b, c, y);
input a;
input b;
input c;
output [0:7] y;
reg [0:7]y;
// wire a,b,c;
always@(a or b or c)
begin
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case({a,b,c})
3'b000:begin y=8'b10000000; end
3'b001:begin y=8'b01000000; end
3'b010:begin y=8'b00100000; end
3'b011:begin y=8'b00010000; end
3'b100:begin y=8'b00001000; end
3'b101:begin y=8'b00000100; end
3'b110:begin y=8'b00000010; end
3'b111:begin y=8'b00000001; end
default :begin y=8'b00000000; end
endcase
end
endmodule
3 TO 8 LINE DECODER TEST BENCH
`resetall
`timescale 1ns/1ps
module decoder38beh_tb_v;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire [0:7] y;
// Instantiate the Unit Under Test (UUT)
decoder38beh uut (
.a(a),
.b(b),
.c(c),
.y(y)
);
initial
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begin
// Initialize Inputs
a =0;b=0;c=0;
#10 a=0; b=0; c=1;
#10 a=0; b=1; c=0;
#10 a=0; b=1; c=1;
#10 a=1; b=0; c=0;
#10 a=1; b=0; c=1;
#10 a=1; b=1; c=0;
#10 a=1; b=1; c=1;
end
initial
begin
#100 $finish;
end
endmodule
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SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION:3 to 8 line decoder has been designed using different modeling styles
and is verified using the Test Bench.
EXPERIMENT: 5 ENCODERS
5.1------4: 2 LINE ENCODER
AIM: To design a 4:2 line encoder using behavioral and data flow modeling styles and
verified using the test bench TOOLS USED: Xilinx 9.2i Hardware Tool.
DESCRIPTION OF THE MODULE:
An encoder is a digital circuit that performs the inverse operation of the decoder. It has
inputs and n outputs.
BLOCK DIAGRAM:
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TRUTH TABLE:
din[0] din[0] din[0] din[0] a b
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
Here din[0],din[1],din[2],din[3] are the inputs and the a,b are the outputs.
VERILOG CODE:
4 TO 2 LINE ENCODER USING BEHAVIORAL MODEL `resetall
`timescale 1ns/1ps
module encoder42beh(din, a, b);
input [0:3] din;
output a;
output b;
reg a;
reg b;
always@(din)
begin
case({din})
4'b1000:begin a=1'b0; b=1'b0; end
4'b0100:begin a=1'b0; b=1'b1; end
4'b0010:begin a=1'b1; b=1'b0; end
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4'b0001:begin a=1'b1; b=1'b1; end
endcase
end
endmodule
4TO2 LINE ENCODER USING DATAFLOW MODELING STYLE:
`resetall
`timescale 1ns/1ps
module encoder42data(din,a,b) ;
input [0:3]din;
output a,b;
assign a=(din[2])|(din[3]);
assign b=(din[1])|(din[3]);
endmodule
4TO 2 LINE ENCODER TEST BENCH
`resetall
`timescale 1ns/1ps
module encoder42beh_tb_v;
// Inputs
reg [0:3] din;
// Outputs
wire a;
wire b;
// Instantiate the Unit Under Test (UUT)
encoder42beh uut (
.din(din),
.a(a),
.b(b)
);
initial
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begin
// Initialize Inputs
din=4'b1000;
#10 din=4'b0100;
#10 din=4'b0010;
#10 din=4'b0001;
end
initial
begin
#50 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION: A 2 to 4 line encoder has been designed using different modeling styles and is verified using test bench.
5.2---8 : 3 LINE ENCODER
AIM: To design a 8 : 3 line encoder using behavioral and data flow modeling styles and
verified using the test bench. TOOLS USED: Xilinx 9.2i Hardware Tool
DESCRIPTION OF THE MODULE:
An encoder is a digital circuit that performs the inverse operation of the decoder. It has
inputs and n outputs.
BLOCK DIAGRAM:
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TRUTH TABLE:
din0 din1 din2 din3 din4 din5 din6 din7 a b c
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Where din0 to din7 are inputs and a,b,c are outputs.
VERILOG CODE:
8 TO 3 ENCODER USING DATAFLOW MODELING STYLE
`resetall
`timescale 1ns/1ps
module encoder83df(din, a, b, c);
input [0:7] din;
output a;
output b;
output c;
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assign a=din[4] | din[5] | din[6] | din[7];
assign b=din[2] | din[3] | din[6] | din[7];
assign c=din[2] | din[4] | din[6] | din[7];
endmodule
8 TO 3 ENCODER USING BEHAVIORAL MODELING STYLE
`resetall
`timescale 1ns/1ps
module encodr83bh (din,a,b,c);
input [0:7]din;
output a,b,c;
reg a,b,c;
always@(din)
begin
case(din)
8'b10000000:begin a=1'b0;b=1'b0,c=1'b0;end
8'b01000000:begin a=1'b0;b=1'b0;c=1'b1;end
8'b00100000:begin a=1'b0;b=1'b1;c=1'b0;end
8'b00010000:begin a=1'b0;b=1'b1;c=1'b1;end
8'b10001000:begin a=1'b1;b=1'b0,c=1'b0;end
8'b10000100:begin a=1'b1;b=1'b0,c=1'b1;end
8'b10000010:begin a=1'b1;b=1'b1,c=1'b0;end
8'b10000001:begin a=1'b1;b=1'b1,c=1'b1;end
default :begin a=1'bz;b=1'bz;c= 1'b1;end
endcase
end
endmodule
8 TO 3 LINE ENCODER TEST BENCH:
`resetall
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`timescale 1ns/1ps
module encoder83df_tb_v;
// Inputs
reg [0:7] din;
// Outputs
wire a;
wire b;
wire c;
// Instantiate the Unit Under Test (UUT)
encoder83df uut (
.din(din),
.a(a),
.b(b),
.c(c)
);
initial
begin
// Initialize Inputs
din=8'b10000000;
#10 din=8'b01000000;
#10 din=8'b00100000;
#10 din=8'b00010000;
#10 din=8'b00001000;
#10 din=8'b00000100;
#10 din=8'b00000010;
#10 din=8'b00000001;
end
initial
begin
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#100 $finish;
end
endmodule
SYNTHESIS RESULTS:
SIMULATION RESULTS:
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CONCLUSION: 8 to 3 line encoder has been designed using behavioral and data flow modeling styles
and verified using the test bench.
EXPERIMENT: 6 MULTIPLEXER
6.1---4:1 MULTIPLEXER
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AIM: To design a 4:1 multiplexer using behavioral, dataflow models and verify its
functionality using the test bench.
TOOLS USED: Xilinx 9.2i Hardware Tool.
DESCRIPTION OF THE MODULE:
A multiplexer has a group of data inputs and a group of control inputs. It is also called as
data selector. The control inputs are used to select one of the data inputs and connect it to
the output terminal. A 4:1 mutliplexer has four inputs ,2 selection line and 1 output.
BLOCK DIAGRAM:
TRUTH TABLE:
S1 S0 Y
0 0 din[0]
0 1 din[1]
1 0 din[2]
1 1 din[3]
VERILOG CODE:
4:1 MUX USING DATA FLOW MODELING STYLE:
`resetall
`timescale 1ns/1ps
module mux41data (din,s,y);
input [0:3] din;
input[0:1]s;
output out;
assign out=din[s];
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endmodule
4:1 MUX USING BEHAVIORAL MODELING STYLE:
`resetall
`timescale 1ns/1ps
module mux42beh(din, s0, s1, y);
input [0:3] din;
input s0;
input s1;
output y;
reg y;
wire s0,s1;
always@(s0 or s1)
begin
case({s0,s1})
2'b00:y=din[0];
2'b01:y=din[1];
2'b10:y=din[2];
2'b11:y=din[3];
default:y=1'b1;
endcase
end
endmodule
4:1 MUX TEST BENCH:
`resetall
`timescale 1ns/1ps
module mux42beh_tb_v;
// Inputs
reg [0:3] din;
reg s0;
reg s1;
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// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux42beh uut (
.din(din),
.s0(s0),
.s1(s1),
.y(y)
);
initial
begin
din=4'b0011;
s0=1'b0; s1=1'b0;
#5 s0=1'b0; s1=1'b1;
#5 s0=1'b1; s1=1'b0;
#5 s0=1'b1; s1=1'b1;
end
initial
begin
#50 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION: A 4:1 multiplexer is designed using behavioral, dataflow models are
verified using test bench.
6.2---8:1 MULTIPLEXER
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AIM: To design a 8:1 multiplexer using behavioral ,dataflow models and verify its
functionality using the test bench. TOOLS USED: Xilinx 9.2i Hardware Tool
DESCRIPTION OF THE MODULE:
A multiplexer has a group of data inputs and a group of control inputs. It is also called as
data selector. The control inputs are used to select one of the data inputs and connect it to
the output terminal. A 8:1 mux has eight inputs ,3 selection lines and 1 output.
BLOCK DIAGRAM:
TRUTH TABLE:
S0 S1 S2 Y
0 0 0 Y[0]
0 0 1 Y[1]
0 1 0 Y[2]
0 1 1 Y[3]
1 0 0 Y[4]
1 0 1 Y[5]
1 1 0 Y[6]
1 1 1 Y[7]
Where S0,S1,S2 are inputs and Y is output
VERILOG CODE:
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8:1 MUX USING DATA FLOW MODEL
`resetall
`timescale 1ns/1ps
module mux81data1(s,din,y) ;
input [0:2]s;
input [0:7]din;
output y;
wire [0:7]t;
assign t[0]=(~s[0])&(~s[1])&(~s[2]&i[0]);
assign t[1]=(~s[0])&(~s[1])&(s[2]&i[1]);
assign t[2]=(~s[0])&(s[1])&(~s[2]&i[2]);
assign t[3]=(~s[0])&(s[1])&(s[2]&i[3]);
assign t[4]=(s[0])&(~s[1])&(~s[2]&i[4]);
assign t[5]=(s[0])&(~s[1])&(s[2]&i[5]);
assign t[6]=(s[0])&(s[1])&(~s[2]&i[6]);
assign t[7]=(s[0])&(s[1])&(s[2]&i[7]);
assign y=t[0]|t[1]|t[2]|t[3]|t[4]|t[5]|t[6]|t[7];
endmodule
8:1 MUX USING BEHAVIORAL MODELING STYLE:
`resetall
`timescale 1ns/1ps
module mux81bh(i,s,o) ;
input [0:7]i;
input [0:2]s;
output o;
wire [0:7]i;
wire [0:2]s;
wire [0:7]y;
reg o;
always@(s)
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begin
case(s)
3'b000: o=i[0];
3'b001: o=i[1];
3'b010: o=i[2];
3'b011: o=i[3];
3'b100: o=i[4];
3'b101: o=i[5];
3'b110: o=i[6];
3'b111: o=i[7];
endcase
end
endmodule
8:1 MUX TEST BENCH:
`resetall
`timescale 1ns/1ps
module mux81df_tb_v;
// Inputs
reg [0:7] din;
reg [0:2] s;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux81df uut (
.din(din),
.y(y),
.s(s)
);
initial
begin
// Initialize Inputs
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din=8'b01010101;
s=3'b000;
#10 s=3'b001;
#10 s=3'b010;
#10 s=3'b011;
#10 s=3'b100;
#10 s=3'b101;
#10 s=3'b110;
#10 s=3'b111;
end
initial
begin
#100 $finish;
end
endmodule
SYNTHESIS RESULTS:
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SIMULATION RESULTS:
CONCLUSION: A 8:1 multiplexer is designed using behavioral, dataflow models are
verified using test bench.
EXPERIMENT: 7 DEMULTIPLEXER
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7.1. 1:4 DEMULTIPLEXER
AIM: To design a 1X4 DEMULTIPLEXER and verify its functionality and check its
simulation report.
TOOLS USED: Xilinx 9.2i Hardware Tool.
DESCRIPTION OF THE MODULE:
The demultiplexer is the exact opposite to the multiplexer. In this, the data form one line
can be sent onto any one of many lines. The block diagram of multiplexer is given below
and the associated truth table.1:4 demultiplexer has one input and 4 output lines.
BLOCK DIAGRAM:
A
TRUTH TABLE:
S1 S0 Z0 Z1 Z2 Z3
0 0 A 0 0 0
0 1 0 A 0 0
1 0 0 0 A 0
1 1 0 0 0 A
VERILOG CODE FOR 1:4 DEMULTIPLEXER:
DEMULTIPLEXER
Z0
Z1
Z3
Z2
S0 S1
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`resetall
`timescale 1ns/1ps
module demux14bh(din,s,y) ;
input [0:1]s;
input din;
output [0:3]y;
wire [0:1]s;
wire din;
reg [0:3]y;
always @(s or din)
begin
case(s)
2'b00: begin y[0]=din;y[1]=4'b0;y[2]=4'b0;y[3]=4'b0;end
2'b01: begin y[1]=din;y[0]=4'b0;y[2]=4'b0;y[3]=4'b0;end
2'b10: begin y[2]=din;y[1]=4'b0;y[0]=4'b0;y[3]=4'b0;end
2'b11: begin y[3]=din;y[1]=4'b0;y[2]=4'b0;y[0]=4'b0 ;end
endcase
end
endmodule
TEST BENCH FOR 1:4 DEMULTIPLEXER:
`resetall
`timescale 1ns/1ps
module demux14bh_tb;
// Inputs
reg din;
reg [0:1] s;
// Outputs
wire [0:3] y;
// Instantiate the Unit Under Test (UUT)
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demux14bh uut (
.din(din),
.s(s),
.y(y)
);
initial begin
// Initialize Inputs
din = 1;
s=2'b00;
#10 s=2'b01;
#10 s=2'b10;
#10 s=2'b11;
end
initial
begin
#50 $finish;
end
endmodule
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SYNTHESIS RESULTS:
SIMULATION RESULTS:
CONCLUSION:
A 1:4 demultiplexer is designed and is verified using test bench.
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7.2--- 1:8 DEMULTIPLEXER
AIM: To design a 1:8 DEMULTIPLEXER and verify its functionality and check its
simulation report.
TOOLS USED: Xilinx 9.2i Hardware Tool.
DESCRIPTION OF THE MODULE:
The demultiplexer is the exact opposite to the multiplexer. In this, the data form one line
can be sent onto any one of many lines. The block diagram of multiplexer is given below
and the associated truth table.1:8 demultiplexer has one input and 8 output lines.