Verilog -A models of building blocks

Verilog-A models Verilog-A models of building blocksof building blocks

E. Atkin, Y. Bocharov, A. Gumenjuk, A.Kluev, A. Simakov (MEPHI),

A.Voronin (SINP MSU)

Outline (part 1)Outline (part 1)

I.I. ADCADC Verilog models:Verilog models:

• Basic model features

• Designed models

• Simulation time

• “Black-box” model

• Behavioral model

• Model test setup

• Model test examples

11th CBM collaboration meeting, 26.02.08, GSI, Darmstadt

Outline (part 2)Outline (part 2)II.II. CSACSA

• Background

• CSA macromodel

• Frequency domain (AC) model – small signal one

• Noise model

• Input transistor

• Time domain (TRAN) model – large signal one

• Leakage current compensation

• Both polarities of input pulses

III.III. SummarySummary


ADC models ADC models (part 1)(part 1)

The two pipelined 9 bit ADC Verilog models are presented

A. Gumenjuk, Y. Bocharov, A. Simakov

• Range of accuracy – how does model performance satisfy the reality?

• Detailing degree – how many parameters are taken into account?

• Used description tools – what simulators are needed to perform model analysis?

• Required machine resources – how much time is needed to simulate the model?

The basic model features


The designed models

“black-box”

Behavioral level

Transistor level

Extracted level

accuracy Low Medium High Highest

detailing Low Medium High Highest

tools Verilog-AVerilog-A /

Verilogspectre (Verilog)

spectre

machine resources

Low Medium High excessive


Required simulation time

“black-box”

Behavioral level

Transistor level

Extracted level

Simulation time

8 s 1m 30s 10 hseveral weeks!

ADC models have been simulated on a 3.2 GHz 1Gb RAM Pentium 4 processor for receiving 4096 FFT points


• The ideal sampling and quantization ADC functions

• The actual conversion latency

The “black-box” model

ADC is modeled as “black box”, that demonstrates the same functionality as a real one

We describe only:


The model is very simple and fast for simulationThe model is very useful for early system simulationThe model is ideal and doesn’t take into account the real ADC performance

ADC is modeled as “black box”, that demonstrates the same functionality as a real one

The model features:

The “black-box” model (cont)


Verilog-A as an extension of Spice*

* D.FitzPatrick, I.Miller. Analog_Behavioral_Modeling_With The_Verilog-A_Language. Kluwer Academic Publisher, 2003


The behavioral modelADC is modeled using a set of Verilog-A and Verilog blocks

Sample-and-Hold circuit

1.5-bit stages2-bit flash

ADC

Digital delay and RSD

11th CBM Collaboration Meeting, 26.02.08, GSI, Darmstadt

The behavioral model (cont)

The model takes into account a set of static block parameters and inaccuracy of ADC stage, such

as:• OpAmp performance (dc gain,

bandwidth, offset)

• Comparator performance (resolution, offset)

• Stage capacitor mismatches

• Reference voltage inaccuracy


The model test setup

Differential sine voltage

source

The ADC model

9 bit digital output

Ideal 9 bit DAC

analog equivalent of ADC result


The model test example 1The simulated output spectrum of a 9-bit 20 MSps ADC model at Nyquist input frequency

SNR = 56.0 dB

SFDR = 68.3 dB

ENOB = 9.0 bit

9.77MHz input signal


The simulated output spectrum with a normally distributed capacitor mismatch

SNDR = 55.4 dB

SFDR = 67.6 dB

ENOB = 8.9 bit

The model test example 2

σ=0.1% σ=10%

SNDR = 35.7 dB

SFDR = 36.0 dB

ENOB = 5.6 bit


CSA modelsCSA models

E. Atkin, A. Kluev (MEPHI),

A.Voronin (SINP MSU)

Starting point and background

At the moment there are two general problems:1. Officially UMC 0.18 um DKs can not be used with Cadence OA2. No MonteCarlo models for 0.18 um technology

• CSA prototype of 2005 (UMC 0.18, IC 5.1.41 CDBA)

• All we have shifted into IC 6.1 OA, but…


Prototype CSA versus CBM-XYTER specsPrototype Specs

Channel size (w x l), µm 50 x 1000 40 x 1000 max (?)

No. of chs. 8100-200

(for ex.128 typ+2 dummies)

Detector capacitance, pF 0-100 0-30

ENC, el. @ 30pF2250 (no shaper)

(SNR=10 @ 1 mip)800

DC coupling, leakage current compensation

Yes Yes

Polarity Both Both

Input PMOS (NMOS ?), µm 600 x 0.18 @ 360 µA W↑ => noise↓

Power consumption, mW(current consumption, µA)

~0.7 typ

(550 @ -0.9V

180 @ +0.9V)

<1

CSA rise time, @10%-90%, ns20 @20pF

100@100pF--

Output noise, µV rms 400 --


2 reasons of the need for higher levels of abstraction to describe analog circuits

1. A need for higher-level models,

describing the pin-to-pin behaviour of the

circuits, rather than the internal structural

implementation

2. A need to allow a full simulation of the

entire mixed-signal design, being usually a

computationally too complex

Different Analog Hardware Description Levels

G.Gielen, R. Rutenbar Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits Proc. of IEEE, vol.88, no.12, 2000


Description

Large-signal module definition

Large-signal module definition

Time domain – main type

DC transfer curve

AC small-signal

Other…

Parameters of interestGainIntegral NoiseLarge signal non-linearityDC accuracyPower consumptionExternal interfaces to detector and back-end

CrosstalksDetailed noise (1/f, parallel, serial)Programmability (peaking time, biasing)Detailed substitution circuit for multistrip (including double sided) detector interface

Model elaboration flowTransistor

circuit

Transistorcircuit

Behaivioral modelling

Behaivioral modelling

Qualification of parameters and characteristics

Qualification of parameters and characteristics

Macro modelling

Macro modelling

Functional modelling

Functional modelling

Type of model

Type of model

Feedback splitting

Gain=800F-3db=1e5rmsNoise=400e-6

Gm=1uA/VF-3db=1

AC small-signal model

(simplified example)


AC Noise model (simplified)

• E1noise – sum of leakage currents, existing on the preamp input ~eI (shot noise)

• E1noise serial noise 1/F+4kTReq

• Enoise of R13 4kTR13

• I2noise shot parallel noise of FB (1/F?)

• Enoise_fb noise of active FB 1/F^n+4rTRact

• Isig – signal source

CdetIsig Inoise

E1NOISEI1

C13P

R1279r

Enoise R1

gm 3.8m

V1

Uout

Vnoise fb R2

10M

gain 0.79

C2

1pI2noise


Large signal model (example)

Modeled are: Gain, Small-signal AC response Pos. and neg. clamps, Consumption


Required simulation time

“black-box”

Behavioral level

Transistor level

Extracted level

Simulation time

20 ms 30 ms 100 msnot

modeled

CSA models have been simulated on a 2.4 GHz 1.5Gb RAM Pentium 4 processor for passing

1us TRAN analysis


Summary and Outlook• Written are, but not shown here, Veilog-A code for

relevant blocks (CSA and ADC)• Designed are very simple Verilog-A ADC and CSA

models for fast System simulation • Also designed are behavioral ADC and CSA

models, taking into account some static inaccuracies

• It is planed to advance the models for raising their accuracy (e.g. considering the dynamic ADC nonlinearity, CSA large signal behavior and detailed noise modeling)

• Also it is planed to prototype the ADC. GDSII file is ready and waiting for the MPW (miniASIC) chance.


Verilog -A models of building blocks

Documents

darmstadtthe model

model analysis

adc verilog models

real onethe model features

black box

real adc performance

set of verilog

verilog blockssample