V - Ashwin JS · 2017. 4. 7. · SCHMITT TRIGGER (regenerative comparator) Schmitt trigger is an inverting comparator with positive feedback. It converts an irregular-shaped waveform

SCHMITT TRIGGER (regenerative comparator)

Schmitt trigger is an inverting comparator with positive feedback. It

converts an irregular-shaped waveform to a square wave or pulse, also called

as squaring circuit. The input voltage Vin triggers the output V0 every time it

exceeds certain voltage levels called the upper threshold voltage Vut and lower

threshold voltage Vlt, These threshold voltages are obtained by using the

voltage divider where the voltage across R1 is fed back to the input. The

voltage across R1 is a variable reference threshold voltage that depends on the

value and polarity of the output voltage V0

When Vo = +VSat, the voltage across R1 is

called the upper threshold voltage, Vut The input

voltage Vin must be slightly more positive than Vut

in order to cause the output switch from +VSat to -VSat.

As long as Vin <Vut, Vo is at +Vsat.

Vut =R1/R1+R2 (+VSat)

On the other hand, when V0 = -Vsat, the

voltage across R1 is referred to as lower threshold

voltage, vin be slightly more negative than vlt in order

to switch V0 from +Vsat to -Vsat. In other words, for

vin values greater than vlt, vo is at -Vsat. Vlt is given

by the following equation

Vlt =R1/R1+R2 (-VSat)

Thus, if the threshold voltages are made larger than the input noise voltages, the positive feedback will

eliminate the false output transitions. Resistance ROM used to minimize the offset problems. In the triangular wave

and sawtooth wave generators a noninverting comparator is used as a Schmitt trigger. When the input is a triangular

wave, the output of the Schmitt trigger is a square wave, whereas if the input is a sawtooth wave, the output is a pulse

waveform.

The comparator with positive feedback is said to exhibit hysteresis, a dead-band condition That is, when the

input of the comparator exceeds Vut, its output switches from +Vsat to -Vsat and reverts back to its original state,

+Vsat, when the input goes below Vlt.

== 𝑅1

𝑅1+𝑅2(𝑉𝑆𝐴𝑇)

COMPARATOR CHARACTERISTICS

The important characteristics of a comparator are these:

1. Speed of operation

2. Accuracy

3. Compatibility of output

Fig : I/O waveform (c) Vo vs Vin plot of

. hysteresis voltage

vp

Vut

Vut

-vp

+vsat

-vsat

The output of the comparator must switch rapidly between saturation levels and also respond instantly to any

change of conditions at its inputs. This implies that the bandwidth of the op-amp comparator must be rather wide; in

fact, the wider the bandwidth, the higher is the speed of operation. The speed of operation of the comparator is

improved with positive feedback (hysteresis)

The accuracy of the comparator depends on its voltage gain, common-mode rejection input offsets, and

thermal drifts. High voltage gain requires a smaller difference voltage (hysteresis voltage to cause the comparator's

output voltage to switch between saturation levels, On the other hand, a high CMRR helps to reject the common-

mode input voltages, such as noise, at the input terminals. Finally, to minimize the offset problems, the input offset

current and input offset voltage must be negligible; also, the changes in these offsets due to temperature variations

should be very slight.

Since the comparator is a form of analog-to-digital converter, its output must swing between two logic levels

suitable for a certain logic family such as transistor-transistor logic (TTL).

LIMITATIONS OF OP-AMPS AS COMPARATORS

A general-purpose op-amp such as the 741 can be used in relatively less critical comparator applications in which

speed and accuracy are not major factors. With positive feedback (hysteresis), the switching speed of the op-amp

comparator can be improved and false transition due to noise can be eliminated. In addition, an offset voltage-

compensating network and offset minimizing resistor can be used to minimize offset problems.

However, the output voltage swing of an op-amp is relatively large because it is designed primarily as an

amplifier. In other words, the output of an op-amp comparator is generally not compatible with a particular logic

family such as the TTL, which requires input voltages of either approximately +5 V or 0 V. Therefore, to keep the

output voltage swing within specific limits, op-amps are used with externally wired components such as zeners or

diodes. The resulting circuits, in which the outputs are limited to predetermined values, are called limiters.

555 TIMER

One of the most versatile IC is 555 timer. It can be used in a number novel and useful application.

Applications

Monostable and Astable multivibrators, dc to dc converters, digital logic probes, waveform generators, analog

frequency meters and tachometers, temperature measurement and control, infrared transmitters, burglar and toxic gas

alarms, voltage regulators, electric eyes, and many other.

555 timer can produce accurate and highly stable time delays

or oscillation. The timer basically operates in one of two as a

monostable (one-shot) multivibrator or as an astable (free running

multivibrator). The device is available as an 8-pin metal can, an 8-pin

mini DIP, or a 14-pin DIP. Operating temperature range of SE555 is

-55 to +125 and NEE is 0 to +70C. It operates on +5 to +18 V supply

voltag; It has an adjustable duty cycle; timing is from microseconds

through hours; it has a high current output it can source or sink 200

mA

PIN CONFIGURATION

Pin 1: Ground. All voltages are measured with respect to this terminal.

Pin 2: Trigger. The output of the timer depends on the amplitude of the external trigger pulse applied to this

pin. The output is low if the voltage at this pin is greater than 2/3 Vcc. However, when a negative going pulse of

amplitude larger than 1/3 Vcc is applied to this pin, the comparator 2 output goes low, which in turn switches the

output of the timer high. The output remains high as long as the trigger terminal is held at a low voltage.

Pin 3: Output, There are two ways a load can be

connected to the output terminal: either between pin 3

and ground (pin 1) or between pin 3 and supply voltage

Vcc (pin 8).

when the output is low the load current flows

through the load connected between pin 3 and Vcc into

the output terminal and is called the sink current.

However, the current through the grounded load is zero

when the output is low. For this reason, the load

connected between pin 3 and Vcc is called the normally

on load and that connected between pin 3 and ground is

called the normally off load. On the other hand, when

the output is high, the current through the load connected

between pin 3 and Vcc (normally on load) is zero.

However the output terminal supplies current to the

normally off load. This current is called the source

current. The maximum value of sink or source current is

200 mA

Pin 4: Reset. The 555 timer can be reset (disabled) by applying a negative pulse to this pin. When the reset

function is not in use, the reset terminal should be connected to Vcc to avoid any possibility of false triggering.

Pin 5: Control voltage. An external voltage applied to this terminal changes the threshold as well as the trigger

voltage. In other words, imposing a voltage on this by connecting a pot between this pin and ground, the pulse width

of the output waveform can be varied. When not used, the control pin should be bypassed to ground with a 0.01-µF

capacitor to prevent any noise problems.

Pin 6: Threshold. This is the noninverting input terminal of comparator 1 which monitors the voltage across

the external capacitor. When the voltage at this pin is 2 threshold voltage 2/3 Vcc, the output of comparator 1 goes

high, which in turn switches the output of the low.

Pin 7: Discharge. This pin is connected internally to the collector of transistor Q1. When the output is high,

Q1 is off and acts as an open circuit to the external capacitor C connected across it. On the other hand, when the

output is low, Q1 is saturated and acts as a short circuit, shorting out the external capacitor C to ground.

Pin 8: +Voc. The supply voltage of +5 v to +18 is applied to this pin with respect to ground (pin 1)

555 TIMER AS MONOSTABLE MULTIVIBRATOR

A monostable multivibrator, often called a one-shot

multivibrator, is a pulse-Generating circuit in which the

duration of the pulse is determined by the RC Network

connected externally to the 555 timer. In a stable or standby

state the output of circuit is zero os at logic low level. When

an Trigger pulse is applied, the output is forced to go high

(≈Vcc). The time the Output remains high is determined by

the external RC network connected to the timer. At the end

of the timing interval, the output automatically reverts back

to its logic-low state. The output stays low until the trigger pulse is applied. Then the cycle repeats.

Monostable operation.

Initially when the output is low, that is, the circuit is in a stable state, transistor Q1 is on and capacitor C is

shorted out to ground. However, upon application of a negative trigger pulse to pin 2, transistor Q1 is turned off,

which releases the short circuit across the external capacitor C and drives the output high. The capacitor C now starts

charging up toward Vcc through RA.

However, when the voltage across the capacitor equals 2/3

Vcc, comp1’s o/p switches from low to high, which in turn drives the

output to its low state via the output of the flip-flop.

At the same time, the output of the flip-flop turns transistor Q1 on, and hence capacitor C rapidly discharges

through the transistor. The output of the monostable remains low until a trigger pulse is again applied. Then the cycle

repeats.

As shown here, the pulse width of the trigger input must be smaller than the expected pulse width of the output

waveform. Also, the trigger pulse must be a negative-going input signal with an amplitude larger than 1/3 Vcc

The time during which the output remains high is given

by

Once triggered, the circuit's will remain in the high state

until the set time T elapses. The output will not change state even if an input trigger is applied again during this time

interval to. However, the circuit can be reset during the timing cycle by applying a negative pulse to the reset terminal.

The output will then remain in the low state until a trigger is again applied.

Often in practice a decoupling capacitor (10µF) is used

between Vcc (pin 8) and ground (pin 1) to eliminate unwanted

voltage spikes in the output waveform. Sometimes, to prevent

any possibility of mistriggering the monostable multivibrator

on positive pulse edges, a waveshaping circuit consisting of

R, C2, and diode D is connected between the trigger input pin

2 and Vcc pin 8. The values of R and C2 should be selected so

that the time constant RC2 is smaller than the output pulse

width T

APPLICATION OF MONOSTABLE

MULTIVIBRATOR

Missing Pulse Detector

Whenever, input trigger is low, the emitter diode of the transistor Q is forward biased. The capacitor C gets

clamped to few tenths of a volte

(0.7V). The output of the timer goes

HIGH. The circuit is designed so

that the time period of the

monostable circuit is slightly

greater (1/3 longer) than that of the

triggering pulses, So long the

trigger pulse train keeps coming at

pin 2, the output remains HIGH.

However,if a pulse misses, the

trigger input is high and transistor Q

is cut off. The 555 timer enters into normal state of monostable operation. The output goes Low after time T of the

mono-shot. Thus this type circuit can be used to detect missing heartbeat. It can also be used for speed control and

measurement.

Frequency Divider

A continuously triggered monostable circuit when

triggered by a square wave generator can be used as a frequency

divider, if the timing interval is adjusted to be longer than the

period of the triggering square wave input signal. The monostable

multivibrator will be triggered by the first negative going edge of the

square wave input but the output will remain HIGH (because of

greater timing interval) for next negative going edge of the input

square wave. The mono-shot will however be triggered

on the third negative going input, depending on the

choice of the time delay. In this way, the output can be

made integral fractions of the frequency of the input

triggering square wave.

Pulse width Modulation

This is basically a monostable multivibrator with

a modulating input signal applied at pin-5. By the

application of continuous trigger at pin-2, a series of

output pulses are obtained, the duration of which

depends on the modulating input at pin-5. The modulating signal applied at pin-5 gets superimposed upon the already

existing voltage (2/3) Vcc at the inverting input terminal of comparator1. This in turn changes the threshold level of

Comparator1 and the output pulse width modulation takes place.

It may be noted from the output waveform that the pulse duration, that is, the duty cycle only varies, keeping

the frequency same as that of the continuous input pulse train trigger.

THE 555 AS AN ASTABLE MULTIVIBRATOR

In astable multivibrator, often called a

free-running multivibrator, is a rectangular-

wave-generating circuit. Unlike the

monostable multivibrator, this circuit does not

require an external trigger to change the state

of the output, hence the name free-running.

However, the time during which the output is

either high or low is determined by the two

resistors and a capacitor, which are externally

connected to the 555 timer.

Initially, when the output is high,

capacitor C starts charging toward Vcc through

RA and RB. However as soon as voltage across the capacitor equals

2/3 Vcc, comparator 1 triggers the flip-flop, and the output switches

low. Now capacitor C starts discharging through transistor Q1.

When the voltage across C equals l /3 Vcc, comparator 2's output

triggers the flip-flop, and the output goes high. Then the cycle

repeats.

The capacitor is periodically charged and discharged between 2/3

Vcc and 1/3 Vcc, respectively.

Fig. free running freq. vs RA,RB and C

The duty cycle of the square wave is

50%. The astable multivibrator will not

produce square-wave output unless the

resistance RA =0Ω. However, there is a

danger in shorting resistance RA to zero.

With RA =0Ω, terminal 7 is connected

directly to Vcc. When the capacitor

discharges through RB and Q1 (pin 7), an

extra current is supplied to Q1 by Vcc

through a short between terminal 7 and cc,

which may damage Q1 and hence the timer.

Fortunately, an alternative is available,

Astable multivibrator can be used to

produce a square wave output simply by

connecting diode D across resistor RB. The capacitor C charges through RA and diode D to approximately 2/3 Vcc

and discharges through Ra and terminal 7 (transistor Q1) until the capacitor voltage equals approximately 1/3 Vcc;

then the cycle repeats. To obtain a square wave output (50% duty cycle), R must be a combination of a fixed resistor

and potentiometer so that the potentiometer can be adjusted for the exact square wave.

Astable Multivibrator Applications

FSK Generator: In digital data communication, binary code is transmitted by shifting a carrier frequency

between two preset frequencies. This type of transmission is called frequency shift keying (FSK) technique. A 555

timer in astable mode can be used to generate FSK signal. The standard digital data input frequency is 150 Hz. When

input is HIGH, transistor Q1 is off and 555 timer works in the normal astable mode of operation. The frequency of

the output waveform given as

𝑓𝑜 = 1.45

(𝑅𝐴 + 2𝑅𝐵)𝐶

When the input is Low, Q1 goes ON and connects the

resistance Rc across RA. The output frequency is now

given by

𝑓𝑜 = 1.45

(𝑅𝐴||𝑅𝐶 + 2𝑅𝐵)𝐶

Pulse-Position Modulator

The pulse-position modulator can be constructed

by applying a modulating signal to pin 5 of a 555 timer

connected for astable operation. The output pulse position

varies with the modulating signal, since the threshold

voltage and hence the time delay is

PHASE LOCKED LOOPS

The phase-locked loop principle has been used in applications such as FM (frequency modulation) stereo

decoders, motor speed controls, tracking filters, frequency synthesized transmitters and receivers, FM

demodulators, frequency shift keying (FSK) decoders, and a generation of local oscillator frequencies in TV and in

FM tuners.

The phase-locked loop consists of (1)

a phase detector, (2) a low-pass filter, and,

(3) Error amp. 4) voltage controlled oscillator.

The phase detector or comparator

compares the input frequency fIN with feedback

frequency fOUT.

• The output of the phase detector is

proportional to the phase difference between

fIN& fOUT. The output of the phase detector is a

dc voltage & therefore is often referred to as the

error voltage.

• The output of the phase detector is then applied to the LPF, which removes the high frequency noise and

produces a dc level. This dc level in turn, is input to the VCO.

• The output frequency of VCO is directly proportional to the dc level. The VCO frequency is compared with

input frequency and adjusted until it is equal to the input frequencies.

• PLL goes through 3 states, i) free running ii) Capture iii) Phase lock.

Before the input is applied, the PLL is in free running

state. Once the input frequency is applied the VCO frequency

starts to change and PLL is said to be in the capture mode.

The VCO frequency continuous to change until it equals the

input frequency and the PLL is in phase lock mode. When

Phase locked, the loop tracks any change in the input

frequency through its repetitive action. If an input signal vs

of frequency fs is applied to the PLL, the phase detector

compares the phase and frequency of the incoming signal to

that of the output Vo of the VCO. If the two signals differ in

frequency of the incoming signal to that of the output vo of

the VCO. If the two signals differ in frequency and/or phase, an error voltage Ve is generated.

Lock in range(Tracking range):

Once PLL is locked it can track frequency changes in incoming signal. The lock range is defined as the range

of frequencies over which the PLL system maintain lock with incoming signal

Capture range:

Capture range is the frequency range in which the PLL acquires phase lock. Capture range is always smaller

than the lock range

Pull in time :

Total time taken by PLL to establish lock is called pill in time

The phase detector is basically a multiplier and produces the sum (fs + fo) and difference (fs - fo) components

at its output. The high frequency component (fs + fo) is removed by the low pass filter and the difference frequency

component is amplified then applied as control voltage Vc to VCO. The signal Vc shifts the VCO frequency in a

direction to reduce the frequency difference between fs and fo. Once this action starts, we say that the signal is in the

capture range. The VCO continues to change frequency till its output frequency is exactly the same as the input signal

frequency. The circuit is then said to be locked.

PHASE DETECTOR/COMPARATOR

Phase detection is the most important part of the PLL system. There are two types of detectors used, analog

and digital.

Analog Phase Detector

The principle of analog phase detection using switch type phase

detector is shown in Fig.. An electronic switch S is opened and closed by

signal coming from VCO (normally a square wave) . The input signal is,

therefore, chopped at a repetition rate determined by VCO frequency.

positive, the output waveform ve will be half sinusoids (shown hatched).

Similarly, the output waveform for 90 and 180" is shown in Fig, 9.3 (d, e). This type of phase detector is called a half

wave detector, since the phase information for only one-half of the input waveform is detected and averaged. The

output of the phase comparator when filtered through a low pass filter gives an error signal which is the average value

of the output waveform shown by dotted line. It may be seen that

the error voltage is zero when the shift between the two inputs phase

is 90%. So, for perfect lock, the VCO output Bhould be 90° out of

phase with to the input signal.

Analysis

A phase comparator is basically a multiplier which

multiplies the input signal by the VCO signal. Thus the phase

comparator output is

where K is the phase comparator gain (or attenuation

constant) and is

the phase shift

between the input

signal and the VCO output. It can be simplified as,

Digital Phase Detector:

This uses an exclusive OR gate. The output of the Ex-OR gate is high only when Fin or fOUT is high. The DC output

voltage of the Ex-OR phase detector is a function of the phase difference between its two outputs. The maximum dc

output voltage occurs when the phase difference is Π radians or 180 degrees. The slope of the curve between 0 or Π

radians is the conversion gain kφ of the phase detector for eg; if the Ex-OR gate uses a supply voltage Vcc = 5V, the

conversion gain K φ is`

K φ = Π/ 5 = 1.59 V / RAD

Low – Pass filter:

The low pass filter not only removes the high

frequency components and noise, but also controls the

dynamic characteristics of the PLL. These

characteristics include capture range, lock range,

band-width and transient response. If filter band-width

is reduced, the response time increases. However, reducing the band-width of the filter also reduces the capture range

of the PLL. The filter serves one more important

purpose. The charge on the filter capacitor gives a short time

'memory' to the PLL. Thus, even if the signal becomes less than the

noise for a few cycles, the dc voltage on the capacitor continues to

shift the frequency of the VCO till it picks up signal again.

This produces a high noise immunity and lock in range

stability.

VCO

Referring to the circuit in the above figure, the capacitor C1 is linearly charged or discharged by a Constant

current source/sink. The amount of current can be controlled by changing the voltage Vc Applied at the modulating

input (pin 5) or by changing the timing resistor R1 external to the IC Chip. The voltage at pin 6 is held at the same

voltage as pin 5. Thus, if the modulating voltage at Pin 5 is increased, the voltage at pin 6 also increases, resulting in

less voltage across R1 and Thereby decreasing the charging current.

The voltage across the capacitor C1 is applied to the inverting input terminal of Schmitt Trigger via buffer

amplifier. The output voltage swing of the schmitt trigger is designed to VCC and 0.5 VCC. If RA= Rb in the positive

feedback loop, the voltage at the non-inverting input terminal of Schmitt trigger swings from 0.5 VCC to 0.25 VCC.

When the voltage on the capacitor C1 exceeds 0.5 Vcc during charging, the output of the schmitt trigger goes low

(0.5 vcc). The capacitor now Discharges and when it is at 0.25 vcc, the output of schmitt trigger goes high (v cc).

Since the

This gives a triangular voltage waveform across C1 which is also available at pin 4. The square Wave output

of the schmitt trigger is inverted by buffer amplifier at pin 3. The output waveforms are shown near the pins 4 and 3.

The output frequency of the vco can be given as follows:

The output frequency of the VCO can be changed either by (i) R1, (ii) c1 or (iii) the voltage Vc at the modulating input

terminal pin 5. The voltage vc can be varied by connecting a R1-R2circuit. The components R1 and c1 are first selected so that

VCO output frequency lies in the centre of the operating frequency range. Now the modulating input voltage is usually varied

from 0.75 Vcc to Vcc which can produce a frequency variation of about 10 to 1.

MONOLITHIC PHASE LOCKED LOOPS (PLL IC 565)

It consists of phase detector, amplifier, low pass filter and VCO.As shown in the block diagram the

phase locked feedback loop is not internally connected. Therefore, it is necessary to connect output of VCO to

the phase comparator input, externally. The PLL can lock to and track an input signal over typically ±60% bandwidth

w.r.t fo as the center frequency. The lock range fL and the capture range fC of the PLL are given by the following

equations

The important electrical characteristics of the 565 PLL

are,

Operating frequency range: 0.001Hz to 500 Khz.

• Operating voltage range: ±6 to ±12v

• Input level required for tracking: 10mv rms min to 3 Vpp max

• Input impedance: 10 K ohms typically.

• Output sink current: 1mA

• Output source current: 10 mA

The center frequency of the PLL is determined by the free running frequency of the VCO, which is given by

where R1&C1 are an external resistor & a

capacitor connected to pins 8 & 9.

• The VCO free-running frequency fOUT is

adjusted externally with R1 & C1 to be at

the center of the input frequency range.

• C1 can be any value, R1 must have a

value between 2 k ohms and 20 K ohms.

• Capacitor C2 connected between 7 &

+V.

• The filter capacitor C2 should be large

enough to eliminate variations in the

demodulated output voltage in order to

stabilize the VCO frequency.

APPLICATION

Frequency Multiplier:

In this application, the loop is broken and a frequency divider network is inserted between VCO and phase detector

as shown in figure below.

The multiplication factor can be

obtained by selecting a proper Input scaling

factor N of the counter.

Frequency multiplication can also be

obtained by using PLL in its harmonic locking

mode. If the input signal is rich in harmonics

e.g. square wave, pulse train etc., then VCO can be directly locked to the n-th harmonic of the input signal without

connecting any frequency divider in between. However, as the amplitude of the higher order harmonics becomes less,

effective locking may not take place for high values of n. Typically n is kept less than 10.

The circuit can also be used for frequency division. Since the VCO output square wave is rich in harmonics, it is

possible to lock the m-th harmonic of the VCO out with the input signal f. The output fo of VCO is now given by

Frequency Translation

A schematic for shifting the

frequency of an oscillator by a small factor

is shown.

It can be seen that a mixer (or multiplier) and

a low pass filter are connected external to the

PLL. The signal fa which has to be shifted

and the output frequency of the VCO are

applied as inputs to the mixer. The output of

the mixer contains the sum and difference of

fs and fo. However, the output of LPF

contains only the difference signal. The translation or offset frequency f1 is applied to the phase comparator

AM DETECTOR

PLL may be used to demodulate AM signals as

shown in Fig. 9.14. The PLL is locked to the

carrier frequency of the incoming AM signal.

unmodulated is fed to the multiplier, Since

VCO output is always 90" out of phase with

the incoming AM signal under the locked

condition, the AM input signal is also shifted

in phase by 90o before being fed to the

multiplier, This makes both the signals applied

to the multiplier in same phase, The output of

the multiplier contains both the sum and the difference signals, the demodulate output is obtained after filtering high

frequency components by the LPF, since the PLL responds only to the career frequency which are very close to the

VCO output

FM detector

There is shift in carrier frequency about the mean value according to modulating signal at FM transmitter. The

deviation or shift in carrier frequency from centre value is converted to low voltage or high voltage, is demodulation.

Assume the loop is in locked condition, so VCO frequency and input frequency is same. FM signal is applied as input

to phase detector. Phase detector produce error voltage proportional to frequency shift. This signal is passed through

LPF and amplifier to give controlled voltage. Thus controlled voltage is proportional to change in frequency. As input

frequency is shifted up or down, VCO voltage also varies accordingly

SERIES OP-AMP REGULATOR

A voltage regulator is an electronic circuit that provides a stable de voltage independent of the load current,

temperature and ac line voltage variations. The circuit consists of following four parts:

1. Reference voltage circuit

2. Error amplifier

3. Series pass transistor

4. Feedback network.

It can be seen from

that the power transistor Q1 is

in series with the unregulated

dc voltage Vin and the

regulated output voltage Vo.

So it must absorb the

difference between these two

voltages whenever any

fluctuation in output voltage

VO occurs. The transistor Q1

is also connected as an

emitter follower and therefore provides sufficient current gain to drive the load. The output voltage is sampled by the

R1 -R2 divider and fed back to the (-) input terminal of the op amp error amplifier. This sampled voltage is compared

with the reference voltage Vref (usually obtained by a zener diode). The output VO’. of the error amplifier drives the

series transistor Q1.

If the output voltage increases, say, due to variation in load current, the sampled voltage also increases where

B

This, in turn, reduces the output voltage VO’ of the diff-amp due to the 1800 phase difference provided by the op amp

amplifier. VO’ is applied to the base of Q1, which is used as an emitter follower. So VO follows VO’ that is V0 reduces.

Hence the increase in V0 is nullified. Similarly, reduction in output voltage also regulated.

IC VOLTAGE REGULATORS

With the advent of micro-electronics, it is possible to incorporate the complete circuit on a monolithic silicon

chip. This gives low cost, high reliability, reduction in size and excellent performance.

Examples of monolithic regulators are 78 xx/79 XX series and 723 general purpose regulators.

Fixed Voltage Series Regulator

78 xx series are three terminal, positive fixed voltage regulators. There are seven output voltage options available

such as 5, 6, 8, 12. 18 v. 78 xx, the last two numbers XX indicate the output voltage. Thus 7815 represents a 15 V

regulator. There are also available 79 XX series of fixed output, negative voltage regulators which are complements

to the 78 XX series devices. There are two extra voltage options of -2 V and -5.2 V available in 79 XX series.

These regulators are available in two types of packages

.Metal package (TO 3 type)

Plastic package (TO 220 type)

A capacitor C (0.33 HF) is usually

connected between input terminal and

ground to cancel the inductive effects

due to long distribution leads. The

output capacitor Co (1µF) improves the

transient response.

Characteristics

There are four characteristics of three terminal IC regulators which must be mentioned.

1. Vo The regulated output voltage is fixed at a value as specified by the manufacturer. There are a number of

models available for different output voltages, for example, 78 XX series has output voltage at 5, 6, 8 etc.

2. |vin| > |Vo|+ 2 volts: The unregulated input voltage must be at least 2 V more than the regulated output voltage.

For example, if Vo 5 V, then Vin = 7v

3. Io( max) :The load current may vary from 0 to rated maximum output current. The IC usually provided with a heat

sink, otherwise it may not provide the rated maximum output current.

4. Thermal shutdown: The IC has a temperature sensor (built-in) which turns off the when it becomes too hot

(usually 125. C to 150 C). The output current will drop and remains there until the IC has cooled significantly.

Line/Input Regulation

It is defined as the percentage change in the output voltage for a change in the input voltage. It is usually expressed

in millivolts or as a percentage of the output voltage. Typical value of line regulation from the data sheet of 7805 is

3 mv.

Load Regulation

It is defined as the percentage change in the output voltage for a change in the load current. It is usually

expressed in millivolts or as a percentage of the output voltage. Typical value of load regulation from the data sheet

of 7805 is 15 mv for 5mA < Io < 1.5A.

Ripple Rejection

IC regulator not only keeps the output voltage constant but also reduces the amount of ripple voltage. It is

usually expressed in dB. Typical value for 7805 is 78dB.

Current Source

Three terminal regulator can be used as a current source. The circuit where 7805 has been wired to supply a

current of 1ampere to a 10 ohm, 10 watt load

IQ is the quiescent current and is about 4.2 mA for

7805

So the value of R required is

R = 5V/1a = 5Ω

Thus choose R = 5Ω to deliver 1A current to a load of

10Ω

Boosting IC Regulator output Current

It is possible to boost the output current of a three terminal regulator simply by connecting an external pass

transistor in parallel with the regulator as shown in Fig. 6.4 (b). Let us now see how the circuit works. For low load

currents, the voltage drop across R1 is insufficient to drive the transistor Q1 and the regulator itself is able to supply

the load current. However, as IL increases, the voltage drop across R1 increases. When this voltage drop is

approximately 0.7 V, the transistor Q1 turns on. It can be easily seen that if IL = 100 mA, the voltage drop across R1

is equal to 7 Q x 100 mA = 0.7v. if IL increases more than 100 mA, the transistor Q1 turns on and supplies the extra

current required. Since VEB (ON) remains fairly constant, the excess current comes from Q1’s Base after

amplification by B. The regulator adjusts IB so that

Adjustable Regulator

In the laboratory, one may need variable regulated or a voltage that is not available as standard fixed voltage

regulator. This can be achieved by using a fixed three terminal regulator. Note that the ground (GND) terminal of the

fixed three terminal regulator is floating. The output voltage

where VR is the regulated voltage

difference Between the OUT and GND terminals.

The effect of lQ is minimized by choosing R2 small

enough to minimize the term IQR2. The minimum

output voltage is the value of the fixed voltage

available from the regulator. The LM117, 217, 17

positive regulators and LM137, 237, 337 negative

regulators have been specially designed to be used

for obtaining adjustable output voltages. It is

possible to adjust output voltage from 1.2 v to 40

V and current upto 1.5 A.

723 GENERAL PURPOSE REGULATOR

The three terminal regulators discussed earlier have the following limitations:

1. No short circuit protection

2. output voltage (positive or negative) is fixed.

These limitations have been overcome in the 723 general purpose regulator, which can adjusted over a wide range

of both positive or negative regulated voltage. This IC is inherently low current device, but can be boosted to provide

5 amps or more current by connect external components. The limitation of 723 is that it has no in-built thermal

protection also has no short circuit current limits. It has two separate sections. The zener diode, a constant current

source and reference amplifier produce a fixed voltage of about 7 volts at the terminal Vref. The constant current

source forces the zener operate at a fixed point so that the zener outputs a fixed voltage.

The other section of the IC consists of an error amplifier, a series pass transistor Q1 and a current limit

transistor Q2. The error amplifier compares a sample of the output voltage applied at the INV input terminal to the

reference voltage Vref applied at the NI input terminal. The error signal controls the conduction of Q1. These two

sections are not internally connected but the various points are brought out on the IC package. 723 regulated IC is

available in a 14-pin dual-in-line package or pin metal-can.

The difference between VNI and the

output voltage Vo which is directly fed back

to the INV terminal is amplified by the error

amplifier. The output of the error amplifier

drives the pass transistor Q1 so as to

minimize the difference between the NI and

INV inputs of error amplifier. Since Q1 is

operating as an emitter follower

The output voltage becomes low, the

voltage at the INV terminal of error amplifier

also goes down. This makes the output error

amp become more positive, driving transistor

Q1 more into conduction. This reduces the

across and drives current into the load

causing voltage across load to increase. So

the initial drop in the load voltage has compensated. Similarly, any increase in load voltage, or changes in the input

voltage get regulated.

The reference voltage is typically 7.15 v. So the output voltage Vo is

which will always be less than 7.15 v, So in the circuit is used as low voltage regulator

If it is desired to produce regulated output voltage

greater than 7 V, then the below circuit can be used. The NI

terminal is connected directly to Vref through R3. So the

voltage at the NI terminal is Vref .The error amplifier

operates as a non-inverting amplifier with a voltage gain of

So the output voltage for the circuit is

Current Limit Protection

The circuits of for 723 regulator have no protection.

If the load demands more current e.g. under short circuit conditions, the IC tries to provide it at a constant output

voltage getting hotter all the time. This may ultimately burn the IC. The IC is, therefore, provided with a current limit

facility. Current limiting refers to ability of a regulator to prevent the load current from increasing above a present

value. Characteristic curve of a current limited power supply is shown The voltage remains constant for load current

below Ilimit. As current approaches to the limit, output voltage drops. The current limit Ilimit is set by connecting

external resistor also between the terminals CL and CS terminals. The CL terminal is connected to the output terminal

V0 and CS terminal to the load.

The load current produces a small voltage drop Vsense, across Rsc. This voltage Vsense applied directly across

the base emitter junction of Q2. When this voltage is 0.5 volt, transistor Q2 begins to turn ON. Now a part of the

current from error amplifier reduces emitter current of Q1. So any increase in the load current will get nullified.

Similarly, if the load current decreases, VBE of Q2 drops, repeating the cycle in such a manner that the load current

is held constant to produce a voltage across Rsc sufficient to turn ON Q2. This voltage is typically 0.5v

This method of current limiting is also referred to as current sensing technique.

current Foldback

In

current limiting

technique, the

load current is

maintained at a

present value

and when

overload

condition

occurs, the

output voltage

Vo drops to

zero. However,

if the load is

short circuited, maximum current does flow through the regulator. To protect the

regulator, one must devise a method which will limit the short circuit current and yet

allow higher currents to the load.

Current foldback is the method used for this. As current demand increases, the output

voltage is held constant till a present current level (knee) is reached. If the current

demand exceeds this level, both output voltage and output current decrease. In order to

understand the operation of the circuit, consider the circuit, voltage at terminal CL is

divided by R3-R4, network. The current limit transistor Q2 conducts only when the drop

across the resistance Rsc is large enough to produce a base-emitter voltage of Q2 to be

at least 0.5 V. As Q2 starts conducting, transistor Q1 begins to turn off and the current

I, decreases. This reduces the voltage V1 at the emitter of Q1 and also the output voltage Vo. The voltage at the base

of Q2 (CL) will be V1R4/(R3+R4).

Current Boosting

The maximum current that 723 IC regulator

can provide is 140 mA. For many application this is

not sufficient. It is possible to boost the current level

simply by adding boosting transistor Q1 to the

voltage regulator. The collector current of the pass

transistor Q1 comes from the unregulated dc supply.

The output current from drives the base of the pass

transistor Q1. This base current gets multiplied by

the beta of the pass transistor, so that 723 has to

provide only the base current. So,

Iload = βpass transistor x Io