Uttam Singisetti*, Man Hoi Wong, Jim Speck, and Umesh Mishra ECE and Materials Departments

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Uttam Singisetti*, Man Hoi Wong, Jim Speck, and Umesh Mishra

ECE and Materials DepartmentsUniversity of California, Santa Barbara, CA

2011 Device Research ConferenceSanta Barbara, CA, USA

*[email protected]

Vertically scaled 5 nm GaN channel Enhancement-mode N-polar GaN MOS-HFET with 560 mS/mm gm and 0.76 -mm Ron

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Outline

• Next generation GaN electronic devices

• N-polar GaN HEMTs

• Vertically scaled channel devices

• Results and Conclusion

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− GaN HEMTs: Power-switching, microwave, W-band power amplifiers

−Future GaN devices for beyond mm-wave and to sub-mm-wave bands

−Higher operating voltages than traditional III-Vs and Si robust and rugged mixed signal ICs

Next-generation mm-wave GaN devices

John Albrecht, DARPA

1.3 W at 75 GHz

Fujitsu, CSIC 2010

3 W at 87 GHz

Caltech, HRLISSSTT, 2011

W-band GaN power amplifiers

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−Aggressive dimensional scaling (Lg and Lsd )

−Vertical scaling with back-barrier and high-k dielectric

− Parasitic resistances and capacitances scaling

−Maintain high breakdown voltage

Device goals and structure

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− No barrier to electron on top of 2-DEG grading to narrowgap InN low resistance contacts (0.027 -mm)1

− AlGaN back confinement of 2-DEG, control short channel effects2

− Record high gm = 1105 mS/mm demonstrated4 in D-mode

− E-mode devices

N-polar GaN

Ultra-scaled N-polar HEMTs

1. S.Dasgupta, APL 2010,

N-polar inverted HEMT

No electron barrier

2. S. Rajan, IEEE TED 2011 3. NIdhi, DRC 2011

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Under gate

0 20 40 60 80 100

-4

-3

-2

-1

0

1

2

3

4

InN

n+ Graded InGaN(In: 0% to 65%)

GaN:SiAlN

GaN channel

EF

Ener

gy (e

V)

Depth (nm)

Under S/D contacts*

* S.Dasgupta, APL 2010

Under sidewall

AlN removed under sidewall

20 40 60 80 100

-4-3

-2-101

23

4 n(x)n

(x10

19 c

m-3)

EF

EV

EC

AlN

GaN:SiSiNx

GaN

GaN

Ener

gy (e

V)

Depth (nm)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

E-mode device structure and design

Top AlN depletes 2-DEG under gate

Under gate

0 5 10 15 20 25 30 35 40

-6

-4

-2

0

2

4 AlN

EV

EF

EC

Depth (nm)

Ener

gy (e

V)

AlxGa1-xN:Si0.05<x<0.25

GaN

AlN

Al2O

3

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Short channel effect and vertical scaling

• Vth roll off with gate length

• Vertical scaling needed to maintain E-mode at sub-50 nm gate lengths • Vertical scaling for high Rds at sub-50-nm gate lengths

Vt roll-off with gate length

20 nm GaN channel1 8 nm GaN channel2

Poor saturation at sub-100nm Lg

1. U.Singisetti, EDL 2010, 2. U.Singisetti, APEX 2011

Need 5 nm GaN channel for sub-50 nm devices

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Ultra-thin channel challenges: Mobility

• Need 5 nm thick GaN channel for sub-50 nm devices

• Mobility drops with decreasing GaN channel thickness

• Interface roughness, surface roughness scattering increases*

* U.Singisetti, ISCS 2011

QW thickness flutuations

GaN

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Mobility dependence on Si doping

• Low mobility in high-3D Si density samples

• High Si density may lead to rougher interface

Si : 5 e18 cm-3

Si : 2 e 19 cm-3

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Ultra-thin channel challenges: surface depletion

• Surface depletion increases in thin channels

• Lower charge in the access regions lead to higher source resistance

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5nm-GaN channel device design

• Graded back-barrier high mobility and t reduce the effect of trap*

• 4.5 nm of Al2O3 gate dielectric

• 1.6×1013 cm-2 in the sidewall access regions after top-AlN etch* M -H Wong, DRC 2011.

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Device fabrication process*

* U.Singisetti, EDL 2010.

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DC characteristics

• Reduced short channel effects due to vertical scaling and graded barrier1

• Peak gm = 560 mS/mm, peak Id = 1.3 A/mm

• Positive threshold voltage of 1.3 V

* M -H Wong, DRC 2011.

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DC characteristics: Ron and Rs

• Record low Ron = 0.61 -mm* for Lg = 115 nm

• InN growth optimization for complete coverage near the gate

• Regrowth sheet resistance = 100 /sq, c = 5 -mm

GateInN

Gate

No InN

InN

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RF performance: peak ft

• peak ft = 115 GHz at Vds = 4.5 V and Vgs = 2.5 V

• low fmax = 30 GHz due to thin W gate ( ~ 1500 /sq)

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RF performance : small-signal model

• Equivalent circuit model

TermTerm2

Z=50 OhmNum=2

RR4R=Rs Ohm

RR8R=Rg Ohm

TermTerm1

Z=50 OhmNum=1

CC1C=Cgs fF

RR22R=Rch Ohm

RR2R=Rd Ohm

CC2C=Cgd fF

CC3C=Cds fF

VCCSSRC2

F=F THzR2=0R1=0T=T psecG=G mS

RR11R=Rds OhmS21/5

S22

S12*3

S11

Measured (circles)

Modeled (line)

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• Vgs corrosponding to peak ft is 2.5 V

• Absence of drain delay

RF performance: bias dependence

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Conclusions and future work• Demonstrated vertically scaled 5-nm GaN channel MOS-HFET devices

• E-mode with Vth = 1.3 V, peak gm = 560 mS/mm, peak Id = 1.3 A/mm

• Record low Ron = 0.61 -mm, for 115 nm E-mode GaN HEMTs

• peak ft = 115 GHz for 120 nm gate length device

This work was supported by DARPA NEXT program

Future work• Scale the gate length to 50 nm

• Top gate for fmax

• Scale the gate dielectric (HfO2, ZrO2)

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New measurements post DRC

• peak ft = 122 GHz at Vds = 5.5 V and Vgs = 2.5 V

• ft-Lg product of 14 GHz-m

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New measurements post DRC

• maximum Ion/Ioff ratio ~ 2×105

• Breakdown voltage 8. 6 V • dielectric breakdown