Using the STGW35HF60WD advanced PT IGBT in … 2010 Doc ID 17151 Rev 1 1/14 AN3161 Application note Using the STGW35HF60WD advanced PT IGBT in parallel Introduction When two or more

May 2010 Doc ID 17151 Rev 1 1/14

AN3161Application note

Using the STGW35HF60WD advanced PT IGBT in parallel

IntroductionWhen two or more IGBTs are connected in parallel to improve the total efficiency in high output power systems, special care is required to ensure that current sharing between the devices is as equal as possible. Current sharing is mainly influenced by differences in IGBT static parameters, circuitry layout (both driving and power) and thermal imbalances. All of these elements must be considered, especially when PT (punch-through) IGBTs work in parallel, due to their negative VCE(sat) coefficient. In order to provide the most efficient IGBT to the market while supporting reliable and easier paralleling for higher power level applications, ST offers the STGW35HF60WD 35 A, 600 V ultra fast IGBT with VCE(sat) selection. This device is explained in greater detail in Section 3: New advanced planar PT STGW35HF60WD.

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Contents AN3161

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Contents

1 Saturation voltage impact on parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1 PT, NPT and trench field stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 General guidelines on paralleling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1 Thermal system impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 New advanced planar PT STGW35HF60WD . . . . . . . . . . . . . . . . . . . . . . 73.1 Notes on technology and VCE(sat) grouping . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 EOFF impact on parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 The STGW35HF60WD on the test bench . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

AN3161 List of figures

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List of figures

Figure 1. ∆IC (@TJ = 25 °C) of two paralleled IGBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Figure 2. ∆IC (@TJ > 25 °C) of two paralleled IGBT without negative feedback . . . . . . . . . . . . . . . . . 5Figure 3. Static VCE(sat)(@20 A,15 V) derating for STGW35HF60WD . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 4. EOFF vs. VCE(sat) for the STGW35HF60WD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 5. DC-DC boost scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 6. VCE(sat)(@20 A, 25 °C, 15 V) grouping for the STGW35HF60WD . . . . . . . . . . . . . . . . . . . . 9Figure 7. ∆IC at TC = 25 °C (board startup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 8. ∆IC at TC = 100 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 9. ∆IC at TC = 25 °C (board startup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 10. ∆IC at TC = 100 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 11. ∆IC at TC = 25 °C (board startup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 12. ∆IC at TC = 100 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Saturation voltage impact on parallel AN3161

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1 Saturation voltage impact on parallel

1.1 PT, NPT and trench field stopPT IGBTs (including those offered by STMicroelectronics) have typically negative VCE(sat) coefficients at current operative levels. This has a very important effect when two devices work in parallel. Due to their difference in static output characteristics, the one with the lowest static VCE(sat) carries more current than the other, as shown in Figure 1. The ∆IC is the static current difference established at the beginning.

Figure 1. ∆IC (@TJ = 25 °C) of two paralleled IGBT

Assuming the same TJ at the beginning, the IGBT carrying higher current dissipates more power than the other, and its TJ increases. As a consequence, its VCE(sat) decreases and the current of the IGBT increases further. The IGBT carrying less current also decreases its static VCE(sat) as a consequence of the common VCE, and its current must satisfy the following equation:

Equation 1

AM06441v1

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25

Vce collector emitter voltage (V)

I c c

olle

ctor

cur

rent

(A

)

ΔIC

IC1

IC2

VCE1=VCE2

ICTOT=IC1+IC2

ICTOT IC1 T1( ) IC2 T2( )+=

AN3161 Saturation voltage impact on parallel

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Figure 2. ∆IC (@TJ > 25 °C) of two paralleled IGBT without negative feedback

As a consequence of the negative VCE(sat) coefficient, a higher ∆IC is established at high TJ (Figure 2). This can cause thermal instability if an accurate negative feedback is not implemented. NPT and field stop IGBTs have positive VCE(sat) coefficients (the latter typically starting from low current levels). When working in parallel the one carrying the higher current increases its temperature, which causes a VCE(sat) increase. This means that, at the same on-state voltage level, the current does not increase with temperature as in PT IGBTs; this guarantees an intrinsic balancing mechanism, preventing thermal runaway.

AM06440v1

Tj>25°C, VGE =15V

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25

Vce collector emitter voltage (V)

Ic c

olle

ctor

cur

rent

(A)

ΔIC

IC1

VCE1=VCE2

ICTOT=IC(T1)+IC(T2)

IC2

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2 General guidelines on paralleling

2.1 Thermal system impactIn order to guarantee the satisfactory performance of paralleled devices, regardless of the IGBT technology used, it is recommended to place them on the same heatsink, very close together. If the IGBTs are sufficiently close, the one with the higher TJ will heat its neighbor, improving temperature and current sharing. PT IGBTs in particular benefit from the common heatsink, as it balances the negative VCE(sat) coefficient, which prevents thermal runway. If the thermal system impact is considered on paralleling, the mutual thermal resistance between the two junctions is the most important factor impacting on the dynamic ∆IC at high temperatures. If a thin layer of silicon grease is used between the IGBT case and the heatsink, power sharing greatly improves, leading to a significant ∆IC reduction at operating temperatures. This occurs because the silicon grease significantly decreases the thermal resistance between the relative junctions.

2.2 Layout considerationsGeneral rules during the design phase should be adopted to minimize unavoidable asymmetries occurring under transient conditions (turn-on and turn-off). First, it is recommended to make the gate drive circuit as symmetrical as possible, and to use individual gate resistors. Individual driving stages provide two advantages:

● They avoid imbalances during the turn-on and turn-off phase. They mainly occur when the two IGBTs have different Vplateau values and the same forced VGE due to the common gate. As a consequence, one of the two IGBTs turns on before the other, and turns off later.

● They damp oscillations during the transient state, caused by the cross-capacitive coupling of the paralleled devices with the driving loop inductances. If parasitic oscillations are still present due to layout inductances, ferrite beads added to each gate wire can help to drastically reduce the oscillations.

Additionally, voltage overshoot can appear across the devices due to the di/dt and to stray inductances in the power circuit. It is suggested to make these loop inductances as short as possible in order not to exceed the absolute maximum rating of the IGBT voltage, rather than make them symmetrical. If not perfectly matched, the collector and emitter inductances can cause different current slopes during switch-off. Any IGBT technology can benefit from this layout optimization.

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3 New advanced planar PT STGW35HF60WD

3.1 Notes on technology and VCE(sat) groupingAn advanced PT IGBT has been introduced to enhance the previous 600 V, 35 A IGBT STGW35NC60WD, tailored for high-frequency applications. From a technology point of view, two main improvements have been implemented on this IGBT:

1. The innovative double-drift process which changed the doping profile

2. The advanced planar strip layout

Both factors allow the reduction of the effective resistance in the drift (N ¯) region and significantly improve the dynamic performance, especially at high temperature. The changes performed on the horizontal and vertical structure and their effect on this IGBT are clearly shown in its datasheet: the new STGW35HF60WD shows a lower VCE(sat) typical value than the equivalent STGW35NC60WD, and its Eoff max value (at IC = 20 A,TJ = 125 °C) is guaranteed as per the datasheet. Tests performed on a significant number of STGW35HF60WD samples show that the static temperature coefficient (see Equation 2), changes in relation to the absolute VCE(sat) value, as shown in Figure 3.

Equation 2

Figure 3. Static VCE(sat)(@20 A,15 V) derating for STGW35HF60WD

Figure 3 also explains how the total VCE(sat) population has been split to guarantee well-balanced and reliable paralleling. The ∆ symbol beside group A, whose VCE(sat) values belong to the interval (1.68 V − 1.92 V [@20 A, 25 °C]), satisfies the equation:

VCE sat( ) TJ 25°C=( ) VCE sat( ) TJ 125°C=( )–⋅ VCE sat( ) TJ 125°C=( )⁄

AM06442v1

VCE(sat) at 20 A, 25 °C

VCE(sat) at 20 A, 125 °C

1.4

1.5

1.6

1.7

1.8

1.9

2

2.1

2.2

2.3

2.4

2.5

0 25 50 75 100 125 150

Tj (°C)

VC

ES

AT(V

)

Δ≈15.5%

Δ≈14.3%

Δ≈13%

Δ≈ 6%

"A" GROUP

"B" GROUP

"C" GROUP

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Equation 3

The same equation can be written for groups B and C. From Figure 3 it is clear that each group has been chosen with a specific ∆ value at TJ = 25 °C. Despite the original imbalance at TAMB, the ∆ of each group moves towards the same value at high temperature. This balancing mechanism helps to keep a very low and stable ∆IC when two or more IGBTs of the same group work in parallel.

3.2 EOFF impact on parallelIt is well known that the EOFF contribution of IGBTs on high-frequency DC-DC conversion cannot be neglected. This impact becomes significant when high TJ and high current levels are considered. The STGW35HF60WD guarantees that the EOFF thermal derating can be controlled and that its value is in the range of 80% −110%. Low VCE(sat) samples show the worst thermal derating (∼ 110%), while high VCE(sat) samples have the lowest thermal derating (∼ 80%), which is clearly illustrated in Figure 4.

Figure 4. EOFF vs. VCE(sat) for the STGW35HF60WD

The difference in EOFF derating has been considered on the VCE(sat) selection, and also explains why the selected groups have different widths.

∆ MaxValue MinValue–( ) MaxValue MinValue+( )⁄ 2⁄= 13= %

AM06443v1

100

150

200

250

300

350

400

450

1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6

VCESAT (V)

Eof

f (µ

J)

Tj=25°C Tj=125°C

Vcl=390V, Ic=20A, Rg=10 ohm, VGE=15V

AN3161 The STGW35HF60WD on the test bench

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4 The STGW35HF60WD on the test bench

A DC-DC boost converter (Figure 5) has been used as a test vehicle to evaluate two STGW35HF60WD IGBTs working in parallel.

Figure 5. DC-DC boost scheme

Boost specifications:

– VIN(DC) = 250 V

– ITAV = 20 A

– VOUT = 380 V

– Fsw = 30 kHz

– Duty = 0.33%

– CCM operation

A preliminary analysis has been performed to measure the dynamic ∆IC established between several couples of paralleled IGBTs. To target the best current sharing, the static VCE(sat)(@20 A,15 V, 25 °C) has been chosen as selection criteria to split the total IGBT population (as illustrated in Figure 6) and three sets of tests are reported in this document.

Figure 6. VCE(sat)(@20 A, 25 °C, 15 V) grouping for the STGW35HF60WD

The STGW35HF60WD on the test bench AN3161

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Couple n.1 and n.3 tested have ∆VCE(sat)@20 A, 25 °C different from its relative group. For example, couple n.1, has been chosen with ∆VCE(sat) = 270 mV (wider than ∆VCE(sat) = 200 mV for group A) in order to guarantee a more reliable result in terms of ∆IC. The same consideration applies for couple n.3.

● Couple n.1

– device n.1: VCE(sat) = 1.75 V (@20 A, 25 °C,15 V)

– device n.2: VCE(sat)t = 2.02 V (@20 A, 25 °C, 15 V)

∆VCE(sat) = 270 mV

● Couple n.2

– device n.1: VCE(sat) = 1.84 V (@20 A, 25 °C,15 V)

– device n.2: VCE(sat) = 2.09 V (@20 A, 25 °C, 15 V)

∆VCE(sat) = 250 mV

● Couple n.3

– device n.1: VCE(sat) = 1.94 V (@20 A, 25 °C,15 V)

– device n.2: VCE(sat) = 2.34 V (@20 A, 25 °C, 15 V)

∆VCE(sat) = 400 mV

The goal of the on-board tests was to evaluate how the dynamic ∆IC of each group moves from board startup (TC = 25 °C) to a steady-state condition in terms of thermal sharing (TC = 100 °C). After board startup, the two paralleled devices share the total power, taking advantage of the common heatsink and layout optimization (as suggested in Section 2.1 and Section 2.2). Thanks to the negative thermal feedback introduced by the common heatsink, the dynamic ∆IC decreases despite of its initial value of TC = 25 °C, and remains stable even at high TJ temperatures.

Couple n.1

Figure 7. ∆IC at TC = 25 °C (board startup) Figure 8. ∆IC at TC = 100 °C

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Couple n.2

Couple n.3

If an acceptable value of ∆IC/ITOT = 10% −14% is considered in terms of efficiency, Table 1 shows that three VCE(sat) grouping allows the paralleling of the IGBTs with excellent performance results.

Figure 9. ∆IC at TC = 25 °C (board startup) Figure 10. ∆IC at TC = 100 °C

Figure 11. ∆IC at TC = 25 °C (board startup) Figure 12. ∆IC at TC = 100 °C

Table 1. ∆IC/ITOT % summary

Couple 1 (∆VCE(sat) = 270 mV)

Couple 2(∆VCE(sat) = 250 mV)

Couple 3(∆VCE(sat) = 400 mV)

∆IC (25 °C)/ITOT % 20% 21% 25.4%

∆IC (100 °C)/ITOT % 14% 12.9% 11%

Conclusion AN3161

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5 Conclusion

Several tests performed on the new advanced planar PT STGW35HF60WD show that STMicroelectronics’ advanced PT technology can be paralleled with satisfactory performance in terms of thermal and current sharing. Reliable paralleling, however, requires good thermal feedback implementation and VCE(sat) selection of the total IGBT population. Both of these factors provide a balancing mechanism to reduce and keep stable the dynamic ∆IC at operating conditions. Finally, the STGW35HF60WD is offered in three different VCE(sat) groups, as shown in Table 2: Suggested VCE(sat) (@20 A, 25 °C, 15 V) selection as per datasheet and as reported in the datasheet, for a safe parallel connection without risk of thermal runaway.

Table 2. Suggested VCE(sat) (@20 A, 25 °C, 15 V) selection as per datasheet (1)

1. The VCE(sat) grouping reported above is slightly different from the one in Figure 6, in order to meet the testing rules.

Group “A” Group “B” Group “C”

1.68 V − 1.92 V 1.88 V − 2.17 V 2.13 V − 2.5 V

@20 A, 25 °C, 15 V @20 A, 25 °C, 15 V @20 A, 25 °C, 15 V

AN3161 Revision history

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6 Revision history

Table 3. Document revision history

Date Revision Changes

05-May-2010 1 Initial release.

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