Using PL485 to Implement a Fully Featured G3-PLC/PRIME Modemww1.microchip.com/downloads/en/Appnotes/AN3495-Using-PL485-t… · P L _ E M I T [ 0 . . 3 ] PL C Co u pl i ng PLC_Coupling

AN3495 Using PL485 to Implement a Fully Featured G3-PLC/PRIME

Modem

IntroductionThe PL485 is a fully programmable Power Line Communication (PLC) System On Chip (SOC). It is able to run anynarrowband-PLC (NB-PLC) protocol in the frequency band up to 500 kHz. By means of selecting the proper firmware,the PL485 is able to support applications requiring basic connectivity (point to point, star) or complex PLC networks(mesh topologies with routing).

Microchip provides firmware examples for basic PLC connectivity, as well as implementations of state-of-the-art PLCprotocols such as ITU-T G.9903 (G3-PLC®) and ITU-T G.9904 (PRIME®). The PL485 is a future-proof modem ableto support the evolution of the implemented NB-PLC standards.

Microchip also provides a series of optimized reference designs for the coupling stage of the PLC transmission whichallows the PL485 to work in the different standardized working bands with different performance from the simplifiedcoupling stage for CENELEC-B to the full-featured PLC modem for multiband (CENELEC-A / FCC).

The PL485-EK mounts a PLC coupling for CENELEC-B working band without external amplification stage, which issimpler and more cost efficient than the reference designs with external amplifier, although the resulting performanceis also lower. In case of requiring a higher signal level or PLC transmission in a frequency band different fromCENELEC-B, this application note describes what firmware and hardware changes need to be performed.

This application note describes how to use the PL485 with the coupling designs based on the external amplifier andthe firmware modifications required for each working band and protocol. The following figure shows the frequencybands supported by the coupling reference designs available for PL485 SoC

Figure 1. PLC Bands Supported by PL485

G3-PLC

CEN-A

0 100 200 300 400 500 Frequency

(kHz)

G3-

PLC

CEN-B

CENELEC [3...148,5 kHz]

G3-PLC ARIB

ARIB [10...450 kHz]

G3-PLC FCC

FCC [10...490 kHz]

USA

JAPAN

EUROPE

CH3 CH4 CH5 CH6 CH7 CH8

CH3 CH4 CH5 CH6 CH7PRIME 1.4

CH1 CH2

PRIME 1.3 & 1.4

PRIME 1.4

© 2020 Microchip Technology Inc. Application Note DS00003495A-page 1

Table of Contents

Introduction.....................................................................................................................................................1

1. Hardware.................................................................................................................................................3

1.1. CENELEC-A.................................................................................................................................41.2. CENELEC-B.................................................................................................................................51.3. FCC..............................................................................................................................................61.4. Multiband (CENELEC-A / FCC)................................................................................................... 8

2. Firmware............................................................................................................................................... 10

2.1. Board Support Package (BSP)...................................................................................................102.2. Working Band.............................................................................................................................132.3. Coupling Configuration...............................................................................................................152.4. PL360 Binary (optional)..............................................................................................................16

3. References............................................................................................................................................20

4. Revision History.................................................................................................................................... 21

4.1. Rev A - 05/2020......................................................................................................................... 21

The Microchip Website.................................................................................................................................22

Product Change Notification Service............................................................................................................22

Customer Support........................................................................................................................................ 22

Microchip Devices Code Protection Feature................................................................................................ 22

Legal Notice................................................................................................................................................. 22

Trademarks.................................................................................................................................................. 23

Quality Management System....................................................................................................................... 23

Worldwide Sales and Service.......................................................................................................................24

AN3495


1. HardwareThe PLC technology of the PL485 does not require external DAC/ADC, simplifying the external required circuitry.Microchip provides a series of reference designs for the coupling to mains which make use of a few passivecomponents plus a Class D amplification stage for transmission.

The reference designs of the PLC coupling stage are generally composed of:

• Transmission stage: adapts the EMIT signals and amplifies them if required.• Reception stage: adapts the received analog signal to be properly captured by the PL485.• Filtering stage: reduces spurious emission and blocks potential interferences from other transmission channels

without distorting the injected signal.• Coupling stage: blocks the DC component of the line and can also isolate the coupling circuitry electrically from

the external world.

Figure 1-1. PLC Coupling Block Diagram

TO MAINS

RECEPTION STAGE

TRANSMISSION STAGE

COUPLING STAGE

PL360

FILTERING STAGE

VDD

AGC

VIN

EMIT0EMIT1EMIT2EMIT3

TXRX0TXRX1

To decide which reference design is needed for the Microchip PLC coupling stage, take the following requirementsinto account:

• PLC working band (CENELEC-A, CENELEC-B, FCC,…)• Electrical isolation• In case of CENELEC-B band, the desired transmission performance

These requirements define the transmission, filtering and coupling stages for the transmission circuit. The receptioncircuit does not depend on the PLC working band or performance, and it is almost the same circuit for all thereference designs; it just requires some additional components on the non-isolated designs due to impedanceadaptation.

Microchip has designed different coupling reference designs to implement a fully featured G3-PLC / PRIME modemwith variations in the BOM cost and the communication performance. The following table summarizes the mainfeatures of the available designs.

Table 1-1. Features of the PLCOUPxxx reference designs

ReferenceDesign

FrequencyBand (kHz) Branch

ElectricalIsolation

PRIMEChannel G3-PLC Band

ApplicableRegulation

PLCOUP007 35 - 91 Single Yes 1 CENELEC-ACENELEC

EN 50065

PLCOUP008 35 - 91 Single No 1 CENELEC-ACENELEC

EN 50065

PLCOUP014Iso 98 - 121 Single Yes - CENELEC-B

CENELEC

EN 50065

AN3495Hardware


...........continuedReference

DesignFrequencyBand (kHz) Branch

ElectricalIsolation

PRIMEChannel G3-PLC Band

ApplicableRegulation

PLCOUP014Non-iso 98 - 121 Single No - CENELEC-B

CENELEC

EN 50065

PLCOUP006Iso 151-488 Double Yes 3, 4, 5, 6, 7, 8 FCC

FCC part 15 -91905

PLCOUP006Non-iso 151-488 Double No 3, 4, 5, 6, 7, 8 FCC

FCC part 15 -91905

PLCOUP011Iso

35-91

151-488Double Yes 1, 3, 4, 5, 6, 7,8

CENELEC-A &FCC

CENELEC

EN 50065

PLCOUP011Non-iso

35-91

151-488Double No 1, 3, 4, 5, 6, 7,8

CENELEC-A &FCC

CENELEC

EN 50065

Since Microchip provides reference designs for the different options of PLC coupling stages with an externalamplifier, the following chapters describe how to use them with the PL485, starting from the PL485-EK schematicdesign, whose coupling stage schematic sheet is replaced by the ones proposed in this document.

1.1 CENELEC-AThe European regulations concerning Power Line Communications are described in CENELEC standard EN 50065.This standard applies to electrical equipment using signals in the frequency range 3 kHz to 148.5 kHz to transmitinformation on low-voltage electrical systems, either on the public supply system or within installations on consumers'premises. Microchip provides two different circuit versions, with and without electrical isolation, to operate as a fully-featured modem compliant with EN50065 in CENELEC-A:

• Coupling for electrically isolated circuitry in CENELEC-A (PLCOUP007)Figure 1-2. PLCOUP007

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

1 of 1

PL485 - Coupling

19/04/2020 11:47:12

PLCOUP007.SchDoc

Project Title

Sch #: Date:

File:Revision: Sheet

Designed with

Drawn By:JPL

Sheet TitlePLC Coupling

Engineer:JPL

03-PL4851

Size A3

PL485PartNumber:

Variant Name[No Variations]

Altium.com

1k

R22

1 2

3PMBD7000

D7AGND

4.02k1%

R23

10000pF

C8

16RR24

100pFC9

AGND

YELLOWD51k

R20

1

23

BC807Q3

GND

3V3

GND

33k

R16

300RR17

330uHL4

3

12

DMN2056UQ4

3

12

DMN2056UQ2

12

3 BAT54SLT1D2

10kR8

10kR6

GND

PL_TXRX0PL_TXRX1

PL_AGCPL_VIN

PL_VZC

PL_EMIT[0..3]PLC Coupling

PLC_Coupling

PL_VIN

Isolated PLC coupling for CENELEC-A

PL_EMIT0

GND

10uHL2

1uFC7

10uHL3

1uFC3

12V

GND

10kR3

10kR14

3kR2

3kR11

BAT54D1

BAT54D4

GND

12V

0.1uF

C1

0.1uF

C61

5

6FDC6420CQ1A

3

4

2

FDC6420CQ1B

12V

3V3

3V3

10kR1

10kR15

GND

GND

33kR5

33kR10

7.5R

R4

7.5R

R13 PL_EMIT1

3V3

GND

4.7kR18

BAT54D6 3 4

1 6

TLP183(GB-TPL,E

U156k

R19

56k

R21

PL_VZC

PL_AGC

GND

12V

0.1uFC5

100uFC4

Zero crossing circuit

Reception circuit

PL_VIN

PL_VZCPL_AGC

1

45

8

T60403-K5024-X044

TR1 15uHL1

SMBJ12CAD3

L

N

275VMOV1

0.47uFC2

270k

R7

270kR12

270kR9

4AF1

Place capacitors C4 and C5 as near as possible of the transistor Q1

• Coupling for electrically non-isolated circuitry in CENELEC-A (PLCOUP008)

AN3495Hardware


Figure 1-3. PLCOUP008

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

1 of 1

PL485 - Coupling

19/04/2020 11:47:22

PLCOUP008.SchDoc

Project Title

Sch #: Date:


Designed with

Drawn By:JPL


Engineer:JPL

03-PL4851

Size A3

PL485PartNumber:


Altium.com

1k

R23

1 2

3PMBD7000

D7AGND

4.02k1%

R24

10000pF

C8

16RR25

100pFC9

AGND

YELLOWD51k

R20

1

23

BC807Q3

GND

3V3

GND

33k

R16

300RR17

470uHL4

3

12

DMN2056UQ4

3

12

DMN2056UQ2

12

3 BAT54SLT1D2

10kR8

10kR6

GND

PL_TXRX0PL_TXRX1

PL_AGCPL_VIN

PL_VZC


PLC_Coupling

PL_VIN

Non-isolated PLC coupling for CENELEC-A

PL_EMIT0

10R

R22

10uHL2

1uFC7

10uHL3

1uFC3

12V

GND

10kR3

10kR14

3kR2

3kR11

BAT54D1

BAT54D4

GND

12V

0.1uF

C1

0.1uF

C61

5

6FDC6420CQ1A

3

4

2

FDC6420CQ1B

12V

3V3

3V3

10kR1

10kR15

GND

GND

33kR5

33kR10

7.5R

R4

7.5R

R13 PL_EMIT1

3V3

GND

4.7kR18

BAT54D6 3 4

1 6

TLP183(GB-TPL,E

U156k

R19

56k

R21

PL_VZC

PL_AGC

GND

12V

0.1uFC5

100uFC4


Reception circuit

PL_VIN

PL_VZCPL_AGC

15uHL1

GND

SMBJ12CAD3

L

N

275VMOV1

0.47uFC2

270k

R7

270kR12

270kR9

4AF1

Place capacitors C4 and C5 as near as possible of the transistor Q1

Both circuitries are a one-branch coupling using EMIT0 and EMIT1 lines to transmit PLC signal and controlled by theTXRX0 line. These lines are already configured in the PL360 firmware binary when the CENELEC-A configuration isrunning.

1.2 CENELEC-BThe PL485-EK evaluation board mounts a simplified coupling stage which makes use of the internal driver of thePL485 to work in the CENELEC-B band. In order to use PL485 in the CENELEC-B working band (from 98 to 121kHz) as a fully-featured modem, Microchip provides two different reference designs with an external amplifier:

• Coupling for electrically isolated circuitry in CENELEC-B (PLCOUP0014 Iso)Figure 1-4. PLCOUP014 Iso

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

1 of 1

PL485 - Coupling

19/04/2020 11:47:30

PLCOUP014 iso.SchDoc

Project Title

Sch #: Date:


Designed with

Drawn By:JPL


Engineer:JPL

03-PL4851

Size A3

PL485PartNumber:


Altium.com

1k

R23

1 2

3PMBD7000

D7AGND

4.02k1%

R24

10000pF

C8

16RR25

100pFC9

AGND

YELLOWD51k

R21

1

23

BC807Q3

GND

3V3

33k

R17

300RR18

3

12

DMN2056UQ4

3

12

DMN2056UQ2

12

3 BAT54SLT1D2

10kR8

10kR6

GND

PL_TXRX0PL_TXRX1

PL_AGCPL_VIN

PL_VZC


PLC_Coupling

PL_VIN

Isolated PLC coupling for CENELEC-B

PL_EMIT0

GND

SMBJ12CAD3

12V

GND

10kR3

10kR15

3kR2

3kR12

BAT54D1

BAT54D4

GND

12V

0.1uF

C1

0.1uF

C61

5

6FDC6420CQ1A

3

4

2

FDC6420CQ1B

12V

3V3

3V3

10kR1

10kR16

GND

GND

33kR5

33kR11

7.5R

R4

7.5R

R14 PL_EMIT1

3V3

GND

4.7kR19

BAT54D6 3 4

1 6

TLP183(GB-TPL,E

U156k

R20

56k

R22

PL_VZC

PL_AGC

GND

12V

0.1uFC3

100uFC2


Reception circuit

PL_VIN

PL_VZCPL_AGC

1

45

8

T60403-K5024-X044

TR1

10uH

L2

1uHL3

2.2uFC7

0.22uF

C5

510R0603

R10

4.7uH

L1

0.47uF

C4L

N

275VMOV1 270k

R7

270kR13

270kR9

4AF1

Place C2 and C3 capacitors as near as possible of the transistor Q1

AN3495Hardware


• Coupling for electrically non-isolated circuitry in CENELEC-B (PLCOUP014 Non-iso)Figure 1-5. PLCOUP014 Non-iso

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

1 of 1

PL485 - Coupling

19/04/2020 11:47:54

PLCOUP014 non-iso.SchDoc

Project Title

Sch #: Date:


Designed with

Drawn By:JPL


Engineer:JPL

03-PL4851

Size A3

PL485PartNumber:


Altium.com

1k

R24

1 2

3PMBD7000

D7AGND

4.02k1%

R25

10000pF

C8

16RR26

100pFC9

AGND

YELLOWD51k

R21

1

23

BC807Q3

GND

3V3

33k

R17

300RR18

3

12

DMN2056UQ4

3

12

DMN2056UQ2

12

3 BAT54SLT1D2

10kR8

10kR6

GND

PL_TXRX0PL_TXRX1

PL_AGCPL_VIN

PL_VZC


PLC_Coupling

PL_VIN

Non-isolated PLC coupling for CENELEC-B

PL_EMIT0

GND

12V

GND

10kR3

10kR15

3kR2

3kR12

BAT54D1

BAT54D4

GND

12V

0.1uF

C1

0.1uF

C61

5

6FDC6420CQ1A

3

4

2

FDC6420CQ1B

12V

3V3

3V3

10kR1

10kR16

GND

GND

33kR5

33kR11

7.5R

R4

7.5R

R14 PL_EMIT1

3V3

GND

4.7kR19

BAT54D6 3 4

1 6

TLP183(GB-TPL,E

U156k

R20

56k

R22

PL_VZC

PL_AGC

GND

12V

0.1uFC3

100uFC2


Reception circuit

PL_VIN

PL_VZCPL_AGC

10uH

L2

1uHL3

2.2uFC7

0.22uF

C5

510R0603

R10

GND

470uHL410R

R23

SMBJ12CAD3

4.7uH

L1

0.47uF

C4L

N

275VMOV1 270k

R7

270kR13

270kR9

4AF1

Place C2 and C3 capacitors as near as possible of the transistor Q1

Both circuitries are a one-branch coupling using EMIT0 and EMIT1 lines to transmit a PLC signal and controlled bythe TXRX0 line. These lines are already configured in the PL360 firmware binary when the CENELEC-Bconfiguration is running.

1.3 FCCFCC section 15 defines the 10-490 kHz frequency band for PLC in North America and Canada. The FCC band(10-490 kHz) is not yet regulated in Europe. This standard applies to electrical equipment using signals to transmitinformation on low-voltage electrical systems, either on the public supply system or within installations on consumers'premises. Microchip provides two different circuit versions, with and without electrical isolation, to operate as a fully-featured modem compliant with FCC section 15 in the frequency range 151 kHz to 488 kHz.

• Coupling for electrically isolated circuitry in FCC (PLCOUP006 Iso)

AN3495Hardware


Figure 1-6. PLCOUP006 Iso

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

1 of 1

PL485 - Coupling

19/04/2020 11:46:53


Project Title

Sch #: Date:


Designed with

Drawn By:JPL


Engineer:JPL

03-PL4851

Size A3

PL485PartNumber:


Altium.com

1k

R35

1 2

3PMBD7000

D9AGND

4.02k1%

R36

10000pF

C13

16RR38

100pFC14

AGND

YELLOWD51k

R20

1

23

BC807Q3

GND

3V3

33k

R16

300RR17

3

12

DMN2056UQ4

3

12

DMN2056UQ2

12

3 BAT54SLT1D8

10kR29

10kR27

GND

PL_TXRX0PL_TXRX1

PL_AGCPL_VIN

PL_VZC


PLC_Coupling

PL_VIN

Isolated PLC coupling for FCC

PL_EMIT0

GND

SMBJ12CAD3

L

N

275VMOV1

12V

GND

10kR3

10kR14

3kR2

3kR11

BAT54D1

BAT54D4

GND

12V

0.1uF

C1

0.1uF

C7

12V

3V3

3V3

10kR1

10kR15

GND

GND

33kR5

33kR10

7.5R

R4

7.5R

R13 PL_EMIT1

YELLOWD111k

R40

1

23

BC807Q8

GND

3V3

33k

R37

300RR39

2.2uHL2

0.33uFC3

0.15uFC8

1uHL1

3

12

DMN2056UQ9

3

12

DMN2056UQ7

3V3

GND

4.7kR18

BAT54D6 3 4

1 6

TLP183(GB-TPL,E

U156k

R19

56k

R21

PL_VZC

PL_AGC

GND

12V

0.1uFC5

100uFC4

0.1uFC6

PL_EMIT2

12V

GND

10kR24

10kR33

3kR23

3kR31

BAT54D7

BAT54D10

GND

12V

0.1uF

C9

0.1uF

C11

1

5

6FDC6420CQ1A

3

4

2

FDC6420CQ1B

3V3

3V3

10kR22

10kR34

GND

GND

33kR26

33kR30

7.5R

R25

7.5R

R32 PL_EMIT1

12

3 BAT54SLT1D2

10kR8

10kR6

GND

12V


Reception circuit

PL_VIN

PL_VZCPL_AGC

1

45

8

T60403-K5024-X044

TR1

33R

R28

0.015uF

C10

0.015uFC12

33uHL3

33uHL4 2

1

6BSD235CQ6A

2

1

6 BSD235CQ5A

0.47uFC2

270k

R7

270kR12

270kR9

4AF1

Place C4, C5 and C6 capacitors as near as possible of the FDC6420 transistors

• Coupling for electrically non-isolated circuitry in FCC (PLCOUP006 Non-iso)Figure 1-7. PLCOUP006 Non-iso

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

1 of 1

PL485 - Coupling

19/04/2020 11:47:04


Project Title

Sch #: Date:


Designed with

Drawn By:JPL


Engineer:JPL

03-PL4851

Size A3

PL485PartNumber:


Altium.com

1k

R36

1 2

3PMBD7000

D9AGND

4.02k1%

R37

10000pF

C13

16RR39

100pFC14

AGND

YELLOWD51k

R20

1

23

BC807Q3

GND

3V3

33k

R16

300RR17

3

12

DMN2056UQ4

3

12

DMN2056UQ2

12

3 BAT54SLT1D2

10kR8

10kR6

GND

PL_TXRX0PL_TXRX1

PL_AGCPL_VIN

PL_VZC


PLC_Coupling

PL_VIN

Non-isolated PLC coupling for FCC

PL_EMIT0

GND

12V

GND

10kR3

10kR14

3kR2

3kR11

BAT54D1

BAT54D4

GND

12V

0.1uF

C1

0.1uF

C7

12V

3V3

3V3

10kR1

10kR15

GND

GND

33kR5

33kR10

7.5R

R4

7.5R

R13 PL_EMIT1

YELLOWD111k

R41

1

23

BC807Q8

GND

3V3

33k

R38

300RR40

3

12

DMN2056UQ9

3

12

DMN2056UQ7

3V3

GND

4.7kR18

BAT54D6 3 4

1 6

TLP183(GB-TPL,E

U156k

R19

56k

R21

PL_VZC

PL_AGC

GND

12V

0.1uFC5

100uFC4

0.1uFC6

PL_EMIT2

12V

GND

10kR24

10kR33

3kR23

3kR31

BAT54D7

BAT54D10

GND

12V

0.1uF

C9

0.1uF

C11

1

5

6FDC6420CQ1A

3

4

2

FDC6420CQ1B

3V3

3V3

10kR22

10kR34

GND

GND

33kR26

33kR30

7.5R

R25

7.5R

R32 PL_EMIT1

12

3 BAT54SLT1D8

10kR29

10kR27

GND

12V


Reception circuit

PL_VIN

PL_VZCPL_AGC

2

1

6BSD235CQ6A

2

1

6 BSD235CQ5A

GND

470uHL510R

R35

2.2uHL2

0.33uFC3

0.15uFC8

1uHL1

33R

R28

0.015uF

C10

0.015uFC12

33uHL3

33uHL4

SMBJ12CAD3

L

N

275VMOV1

0.47uFC2

270k

R7

270kR12

270kR9

4AF1


Both circuitries are a two-branch coupling using:• EMIT0 and EMIT1 lines to transmit a PLC signal controlled by the TXRX0 line against high-impedance lines• EMIT2 and EMIT3 lines to transmit a PLC signal controlled by the TXRX1 line against low-impedance lines

PL360 automatically selects in every moment which branch is more adequate by means of an internal algorithm.These lines are already configured in the PL360 firmware binary when the FCC configuration is running.

AN3495Hardware


1.4 Multiband (CENELEC-A / FCC)Microchip provides a reference design to simultaneously address the 35 to 91 KHz band (CENELEC-A) and the 151kHz to 488 kHz sub-band (higher section of the FCC band). The user can configure the PLC firmware to select eitherband. This reference design is available in two different versions, with and without electrical isolation:

• Coupling for electrically isolated circuitry for multiband (PLCOUP011 Iso)Figure 1-8. PLCOUP011 Iso

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

1 of 1

PL485 - Coupling

19/04/2020 11:47:39


Project Title

Sch #: Date:


Designed with

Drawn By:JPL


Engineer:JPL

03-PL4851

Size A3

PL485PartNumber:


Altium.com

1k

R34

1 2

3PMBD7000

D9AGND

4.02k1%

R35

10000pF

C13

16RR37

100pFC14

AGND

YELLOWD51k

R20

1

23

BC807Q3

GND

3V3

GND

33k

R16

300RR17

330uHL6

3

12

DMN2056UQ4

3

12

DMN2056UQ2

12

3 BAT54SLT1D2

10kR8

10kR6

GND

PL_TXRX0PL_TXRX1

PL_AGCPL_VIN

PL_VZC


PLC_Coupling

PL_VIN

Isolated PLC coupling for Multiband (CENELEC-A / FCC)

PL_EMIT0

GND

15uHL1

10uHL2

1uFC8

10uHL3

1uFC3

12V

GND

10kR3

10kR14

3kR2

3kR11

BAT54D1

BAT54D4

GND

12V

0.1uF

C1

0.1uF

C71

5

6FDC6420CQ1A

3

4

2

FDC6420CQ1B

12V

3V3

3V3

10kR1

10kR15

GND

GND

33kR5

33kR10

7.5R

R4

7.5R

R13 PL_EMIT1

YELLOWD111k

R39

1

23

BC807Q7

GND

3V3

33k

R36

300RR38

2.2uHL5

0.33uFC10

0.15uFC12

1uHL4

3

12

DMN2056UQ8

3

12

DMN2056UQ6

3V3

GND

4.7kR18

BAT54D6 3 4

1 6

TLP183(GB-TPL,E

U156k

R19

56k

R21

PL_VZC

PL_AGC

GND

12V

0.1uFC5

100uFC4

0.1uFC6

PL_EMIT212V

GND

10kR24

10kR32

3kR23

3kR30

BAT54D7

BAT54D10

GND

12V

0.1uF

C9

0.1uF

C111

5

6FDC6420CQ5A

3

4

2

FDC6420CQ5B

3V3

3V3

10kR22

10kR33

GND

GND

33kR26

33kR29

7.5R

R25

7.5R

R31 PL_EMIT11

2

3 BAT54SLT1D8

10kR28

10kR27

GND

12V


Reception circuit

PL_VIN

PL_VZCPL_AGC

1

45

8

T60403-K5024-X044

TR1

SMBJ12CAD3

L

N

275VMOV1

0.47uFC2

270k

R7

270kR12

270kR9

4AF1


• Coupling for electrically non-isolated circuitry for multiband (PLCOUP011 Non-iso)Figure 1-9. PLCOUP011 Non-iso

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

1 of 1

PL485 - Coupling

19/04/2020 11:47:46


Project Title

Sch #: Date:


Designed with

Drawn By:JPL


Engineer:JPL

03-PL4851

Size A3

PL485PartNumber:


Altium.com

1k

R35

1 2

3PMBD7000

D9AGND

4.02k1%

R36

10000pF

C13

16RR38

100pFC14

AGND

YELLOWD51k

R20

1

23

BC807Q3

GND

3V3

GND

33k

R16

300RR17

470uHL6

3

12

DMN2056UQ4

3

12

DMN2056UQ2

12

3 BAT54SLT1D2

10kR8

10kR6

GND

PL_TXRX0PL_TXRX1

PL_AGCPL_VIN

PL_VZC


PLC_Coupling

PL_VIN

Non-isolated PLC coupling for Multiband (CENELEC-A / FCC)

PL_EMIT0

15uHL1

10R

R34

10uHL2

1uFC8

10uHL3

1uFC3

12V

GND

10kR3

10kR14

3kR2

3kR11

BAT54D1

BAT54D4

GND

12V

0.1uF

C1

0.1uF

C71

5

6FDC6420CQ1A

3

4

2

FDC6420CQ1B

12V

3V3

3V3

10kR1

10kR15

GND

GND

33kR5

33kR10

7.5R

R4

7.5R

R13 PL_EMIT1

YELLOWD111k

R40

1

23

BC807Q7

GND

3V3

33k

R37

300RR39

2.2uHL5

0.33uFC10

0.15uFC12

1uHL4

3

12

DMN2056UQ8

3

12

DMN2056UQ6

3V3

GND

4.7kR18

BAT54D6 3 4

1 6

TLP183(GB-TPL,E

U156k

R19

56k

R21

PL_VZC

PL_AGC

GND

12V

0.1uFC5

100uFC4

0.1uFC6

PL_EMIT212V

GND

10kR24

10kR32

3kR23

3kR30

BAT54D7

BAT54D10

GND

12V

0.1uF

C9

0.1uF

C111

5

6FDC6420CQ5A

3

4

2

FDC6420CQ5B

3V3

3V3

10kR22

10kR33

GND

GND

33kR26

33kR29

7.5R

R25

7.5R

R31 PL_EMIT1

12

3 BAT54SLT1D8

10kR28

10kR27

GND

12V


Reception circuit

PL_VIN

PL_VZCPL_AGC

SMBJ12CAD3

L

N

275VMOV1

0.47uFC2

270k

R7

270kR12

270kR9

4AF1

GND


Both circuitries are a two-branch coupling using:• EMIT0 and EMIT1 lines to transmit a PLC signal controlled by the TXRX0 line for CENELEC-A band

AN3495Hardware


• EMIT2 and EMIT3 lines to transmit a PLC signal controlled by the TXRX1 line for FCC band

The adequate binary must be loaded into PL360 to work in the selected band. These lines are already configured inthe PL360 firmware binary.

Regarding the FCC band, the coupling is tuned to work fine against low impedance. If better performancetransmitting in the FCC working band against high impedance is required, it is not possible to use the multibandcoupling and the FCC coupling should be used.

AN3495Hardware


2. FirmwareThe Microchip evaluation kit PL485-EK mounts a PLC coupling for the CENELEC-B working band without an externalamplification stage (PLCOUP012) using the internal driver of the PL485. Thus, the PL485-EK firmware examples areconfigured for G3-PLC CENELEC-B and PLCOUP012. This section describes how to adapt the Microchip PLCfirmware in order to use the PL485 with an external amplifier using G3-PLC (CENELEC-A, CENELEC-B or FCC) orPRIME (channels 1 to 8).

The PL360G55CF-EK or PL360G55CB-EK firmware examples will be used as a starting point for the firmwareadaptation.

• PL360G55CB-EK mounts a PLC coupling for the CENELEC-B working band with an external amplification stage(PLCOUP014).

• PL360G55CF-EK mounts a PLC coupling for the CENELEC-A and FCC working bands with an externalamplification stage (PLCOUP011).

The following table shows the board on which the example project shall be based for the firmware adaptation,depending on the PLC protocol and band to use.

Table 2-1. Board Used for Firmware Adaptation

PLC Protocol and Band Board

G3-PLC CENELEC-A PL360G55CF-EK

G3-PLC CENELEC-B PL360G55CB-EK

G3-PLC FCC PL360G55CF-EK

G3-PLC Multiband (CENELEC-A / FCC) PL360G55CF-EK

PRIME PL360G55CF-EK

The changes to adapt the firmware are summarized in four steps:• 2.1 Board Support Package (BSP)• 2.2 Working Band• 2.3 Coupling Configuration• 2.4 PL360 Binary (optional)

Important: This guide focuses on firmware changes related exclusively to PLC. Other changes (such asports of UART, USB, etc.) should be reviewed by the customer depending on their specific board designand needs.

2.1 Board Support Package (BSP)The Board Support Package (BSP) defines and initializes the microcontroller pins and peripherals for a specific boarddesign. This subsection describes how to modify the PL360G55CF-EK / PL360G55CB-EK BSP in order to use thePL485.

The PL485-EK and Microchip firmware examples use the recommended pin connections given in the PL485datasheet; whereas, PL360G55CF/CB-EK BSPs define a different connection between pins. The section belowexplains how to modify these BSPs following PL485 requirements. Table 2-2 summarizes the BSP configuration forPL360G55CF-EK / PL360G55CB-EK and PL485-EK.

Table 2-2. Pin and Peripheral Connection between SAMG55 and PL360

PL360 SAMG55 (PL360G55Cx-EK) PL485

Pin/Function I/O Line Function I/O Line Function

AN3495Firmware


...........continuedPL360 SAMG55 (PL360G55Cx-EK) PL485

PA9/MISO PA4 SPI3_MISO PA27 SPI7_MISO

PA8/MOSI PA3 SPI3_MOSI PA28 SPI7_MOSI

PA7/SPCK PB13 SPI3_SPCK PA29 SPI7_SPCK

PA6/NPCS0 PB14 SPI3_NPCS0 PA30 SPI7_NPCS0

NRST PA29 GPIO PA25 GPIO

LDO_ENABLE PA30 GPIO PB13 GPIO

TST - - PB15 GPIO

PA3/INT PA0 GPIO PA26 GPIO

PA0/CD PA31 GPIO PA24 GPIO

In the firmware packages provided by Microchip, the BSPs are located at sam\boards\. The files to be modified arelocated in the folders pl360g55cf_ek or pl360g55cb_ek and they are the following:

• pl360g55cf_ek.h / pl360g55cb_ek.h: Pins and peripherals definition. See section 2.1.1 BSP Header File.• init.c: Pins and peripherals initialization. See section 2.1.2 BSP Initialization File.

2.1.1 BSP Header FileThe original code to be replaced in the files pl360g55cf_ek.h or pl360g55cb_ek.h is the following:

/** * \name SPI 3 pin definitions [ATPL360] * @{ */#define SPI3_MISO_GPIO (PIO_PA4_IDX)#define SPI3_MISO_FLAGS (IOPORT_MODE_MUX_A)#define SPI3_MOSI_GPIO (PIO_PA3_IDX)#define SPI3_MOSI_FLAGS (IOPORT_MODE_MUX_A)#define SPI3_SPCK_GPIO (PIO_PB13_IDX)#define SPI3_SPCK_FLAGS (IOPORT_MODE_MUX_A)#define SPI3_NPCS0_GPIO (PIO_PB14_IDX)#define SPI3_NPCS0_FLAGS (IOPORT_MODE_MUX_A)

#define BOARD_FLEXCOM_SPI3 FLEXCOM3#define ATPL360_SPI SPI3#define ATPL360_SPI_CS 0/* @} */

/** * \name PL360 GPIO pin definitions * @{ */#define ATPL360_GPIO0 (PIO_PA31_IDX)#define ATPL360_GPIO1 (PIO_PA5_IDX)#define ATPL360_GPIO2 (PIO_PA1_IDX)#define ATPL360_GPIO3 (PIO_PA0_IDX)#define ATPL360_GPIO4 (PIO_PA16_IDX)#define ATPL360_GPIO5 (PIO_PA06_IDX)/* @} */

/** * \name ATPL360 Reset pin definition * @{ */#define ATPL360_RESET_GPIO PIO_PA29_IDX#define ATPL360_RESET_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW#define ATPL360_RESET_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH/* @} */

/** * \name ATPL360 LDO Enable pin definition

AN3495Firmware


* @{ */#define ATPL360_LDO_EN_GPIO PIO_PA30_IDX#define ATPL360_LDO_EN_ACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH#define ATPL360_LDO_EN_INACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW/* @} */

/** * \name ATPL360 Carrier Detect Enable pin definition * @{ */#define ATPL360_CD_EN_GPIO ATPL360_GPIO0/* @} */

/** * \name ATPL360 interrupt pin definition * @{ */#define ATPL360_INT_GPIO ATPL360_GPIO3#define ATPL360_INT_FLAGS IOPORT_MODE_DEBOUNCE#define ATPL360_INT_SENSE IOPORT_SENSE_FALLING

#define ATPL360_INT {PIO_PA0, PIOA, ID_PIOA, PIO_INPUT, PIO_DEGLITCH | PIO_IT_LOW_LEVEL}#define ATPL360_INT_MASK PIO_PA0#define ATPL360_INT_PIO PIOA#define ATPL360_INT_ID ID_PIOA#define ATPL360_INT_TYPE PIO_INPUT#define ATPL360_INT_ATTR (PIO_DEGLITCH | PIO_IT_LOW_LEVEL)#define ATPL360_INT_IRQn PIOA_IRQn/* @} */

The code block shown above must be replaced by the following code block:

/* ! \name PL360 Internal Connection *//* @{ *//** PL360 MISO pin definition. */#define ATPL360_MISO_GPIO (PIO_PA27_IDX)#define ATPL360_MISO_FLAGS (IOPORT_MODE_MUX_B)/** PL360 MOSI pin definition. */#define ATPL360_MOSI_GPIO (PIO_PA28_IDX)#define ATPL360_MOSI_FLAGS (IOPORT_MODE_MUX_B)/** PL360 SPCK pin definition. */#define ATPL360_SPCK_GPIO (PIO_PA29_IDX)#define ATPL360_SPCK_FLAGS (IOPORT_MODE_MUX_B)/** PL360 chip select pin definition. */#define ATPL360_NPCS0_GPIO (PIO_PA30_IDX)#define ATPL360_NPCS0_FLAGS (IOPORT_MODE_MUX_B)

#define BOARD_FLEXCOM_ATPL360 FLEXCOM7#define ATPL360_SPI SPI7#define ATPL360_SPI_CS 0

/** PL360 Reset pin definition. */#define ATPL360_RESET_GPIO PIO_PA25_IDX#define ATPL360_RESET_ACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW#define ATPL360_RESET_INACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH

/** PL360 LDO Enable pin definition. */#define ATPL360_LDO_EN_GPIO PIO_PB13_IDX#define ATPL360_LDO_EN_ACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH#define ATPL360_LDO_EN_INACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW

/** PL360 TEST (Low Power Enable) pin definition. */#define ATPL360_TEST_GPIO PIO_PB15_IDX#define ATPL360_TEST_ACTIVE_LEVEL IOPORT_PIN_LEVEL_HIGH#define ATPL360_TEST_INACTIVE_LEVEL IOPORT_PIN_LEVEL_LOW

/** PL360 Carrier Detect Enable pin definition. */#define ATPL360_CD_EN_GPIO PIO_PA24_IDX

/** PL360 Interrupt pin definition. */#define ATPL360_INT_GPIO PIO_PA26_IDX#define ATPL360_INT_FLAGS IOPORT_MODE_DEBOUNCE#define ATPL360_INT_SENSE IOPORT_SENSE_FALLING

AN3495Firmware


#define ATPL360_INT {PIO_PA26, PIOA, ID_PIOA, PIO_INPUT, PIO_DEGLITCH | PIO_IT_LOW_LEVEL}#define ATPL360_INT_MASK PIO_PA26#define ATPL360_INT_PIO PIOA#define ATPL360_INT_ID ID_PIOA#define ATPL360_INT_TYPE PIO_INPUT#define ATPL360_INT_ATTR (PIO_DEGLITCH | PIO_IT_LOW_LEVEL)#define ATPL360_INT_IRQn PIOA_IRQn

/* @} */

2.1.2 BSP Initialization FileThe original code to be replaced in the file init.c is the following:

/* Configure ATPL360 SPI pins */ ioport_set_pin_peripheral_mode(SPI3_MISO_GPIO, SPI3_MISO_FLAGS); ioport_set_pin_peripheral_mode(SPI3_MOSI_GPIO, SPI3_MOSI_FLAGS); ioport_set_pin_peripheral_mode(SPI3_SPCK_GPIO, SPI3_SPCK_FLAGS); ioport_set_pin_peripheral_mode(SPI3_NPCS0_GPIO, SPI3_NPCS0_FLAGS); /* Enable FLEXCOM */ flexcom_enable(BOARD_FLEXCOM_SPI3); flexcom_set_opmode(BOARD_FLEXCOM_SPI3, FLEXCOM_SPI);

The code block shown above must be replaced by the following code block:

/* Configure PL360 connection */ ioport_set_pin_peripheral_mode(ATPL360_MISO_GPIO, ATPL360_MISO_FLAGS); ioport_set_pin_peripheral_mode(ATPL360_MOSI_GPIO, ATPL360_MOSI_FLAGS); ioport_set_pin_peripheral_mode(ATPL360_SPCK_GPIO, ATPL360_SPCK_FLAGS); ioport_set_pin_peripheral_mode(ATPL360_NPCS0_GPIO, ATPL360_NPCS0_FLAGS); ioport_set_pin_dir(ATPL360_TEST_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(ATPL360_TEST_GPIO, ATPL360_TEST_INACTIVE_LEVEL); /* Enable FLEXCOM */ flexcom_enable(BOARD_FLEXCOM_ATPL360); flexcom_set_opmode(BOARD_FLEXCOM_ATPL360, FLEXCOM_SPI);

2.2 Working BandThe appropriate working band must be configured in the firmware depending on the PLC protocol and hardwarecoupling design to be used.

Table 2-3. Supported Working Bands by Hardware Coupling Design

Hardware Coupling DesignWorking Band

G3-PLC PRIME

PLCOUP006 FCC Channels 3 to 8 (FCC)

PLCOUP007 CENELEC-A Channel 1 (CENELEC-A)

PLCOUP011 CENELEC-A / FCC Channels 1 to 8 (CENELEC-A /CENELEC-BCD1 / FCC)

PLCOUP014 CENELEC-B -

Notes: 1. Currently, none of the Microchip coupling reference designs is optimized for PRIME channel 2 (CENELEC-

BCD). It is supported in the firmware for PLCOUP011 in order to cover all PRIME channels, but take intoaccount that this coupling is not optimized for channel 2 and the transmitted signal level and quality may belower than in other channels.

2.2.1 Configure G3-PLC Working BandModify the following definitions if they already appear in the corresponding configuration header file.

AN3495Firmware


• Select the corresponding working band (in case of multiband projects, it is the initial working band) inconf_atpl360.h:

/* ! Select work band by default (see definitions in "general_defs.h") */#define ATPL360_WB ATPL360_WB_CENELEC_A

/* ! @{ *//* ! CENELEC A Band Plan (35 - 91 Khz) */#define ATPL360_WB_CENELEC_A 1/* ! FCC Band Plan (154 - 488 Khz) */#define ATPL360_WB_FCC 2/* ! ARIB Band Plan (154 - 404 Khz) */#define ATPL360_WB_ARIB 3/* ! CENELEC-B Band Plan (98 - 122 Khz) */#define ATPL360_WB_CENELEC_B 4/* ! @} */

• Select the corresponding working band (in case of multiband projects, it is the initial working band) inconf_project.h. Only one CONF_BAND_x must be defined:/* Define work band */#define CONF_BAND_CENELEC_A//#define CONF_BAND_CENELEC_B//#define CONF_BAND_FCC

• Disable the multiband functionality, if needed, by commenting the following definition in conf_project.h:

#define CONF_ENABLE_MULTIBAND

2.2.2 Configure PRIME Working Band• For PLC&Go example application, select the initial PRIME channel (from 1 to 8) and the allowed channels in

conf_app_example.h:– PLCOUP007 (Channel 1, CENELEC-A):

/* PLCOUP007: Only allow Channel 1 (CENELEC-A) */#define CONF_PRIME_ALLOWED_CHANNELS (CHN_1_USED)#define CONF_PRIME_CHANNEL_INI 1

– PLCOUP006 (Channels 3 to 8, FCC):/* PLCOUP006: Allow Channels 3-8 (FCC) */#define CONF_PRIME_ALLOWED_CHANNELS (CHN_3_USED | CHN_4_USED | CHN_5_USED | CHN_6_USED | CHN_7_USED | CHN_8_USED)#define CONF_PRIME_CHANNEL_INI 3

– PLCOUP011 (Channels 1 to 8, CENELEC-A / CENELEC-BCD / FCC):/* PLCOUP011: Allow all channels (Branch 0 for Channel 1; Branch 1 for Channels 2 to 8). CONF_ENABLE_C11_CFG should also be defined */#define CONF_PRIME_ALLOWED_CHANNELS (CHN_1_USED | CHN_2_USED | CHN_3_USED | CHN_4_USED | CHN_5_USED | CHN_6_USED | CHN_7_USED | CHN_8_USED)#define CONF_PRIME_CHANNEL_INI 1

• For Phy Tester Tool example application, select the initial PRIME channel (from 1 to 8) inconf_app_example.h:

/* PRIME channel configured at initialization */#define CONF_APP_PRIME_CHANNEL_INI 1

• For full-stack applications, configure the user band plan (allowed channels) in conf_pal.h:– PLCOUP007 (Channel 1, CENELEC-A):

/* Define the band plan */#define USER_BAND_PLAN (CHANNEL1)

AN3495Firmware


– PLCOUP006 (Channels 3 to 8, FCC):/* Define the band plan */#define USER_BAND_PLAN (CHANNEL3 | CHANNEL4 | CHANNEL5 | CHANNEL6 | CHANNEL7 | CHANNEL8)

– PLCOUP011 (Channels 1 to 8, CENELEC-A / CENELEC-BCD / FCC):/* Define the band plan */#define USER_BAND_PLAN (CHANNEL1 | CHANNEL2 | CHANNEL3 | CHANNEL4 | CHANNEL5 | CHANNEL6 | CHANNEL7 | CHANNEL8)

2.3 Coupling ConfigurationThere are several parameters related to coupling configuration and calibration (please refer to the PL360 HostController document for more information about these parameters). The PL360 binary loads a coupling configurationby default. This default configuration is different for each binary and depends on the working band, as shown in Table2-3.

Table 2-4. Default Coupling Configuration and PL360 Binary for each Working Band

Working BandDefault

CouplingConfiguration

PL360 Binary

PHY PHY+MAC Real Time

G3-PLC CENELEC-A PLCOUP007 ATPL360B_G3_CENA.bin ATPL360B_G3_MAC_RT_CENA.bin

G3-PLC CENELEC-B PLCOUP014 ATPL360B_G3_CENB.bin ATPL360B_G3_MAC_RT_CENB.bin

G3-PLC FCC PLCOUP006 ATPL360B_G3_FCC.bin ATPL360B_G3_MAC_RT_FCC.bin

PRIME PLCOUP007(channel 1)1ATPL360B_PRIME.bin N/A

Notes: 1. In the PL360 binary for PRIME, the default channel is 1 (CENELEC-A) and therefore the default coupling

parameters are for PLCOUP007. Thus, if the channel is changed, the coupling parameters must also beupdated through the PL360 Host Controller. The examples provided by Microchip implement this mechanismin the same way that it is described below.

When the hardware coupling used (e.g: PLCOUP011) is different from the default one, the coupling configurationmust be updated through the PL360 Host Controller.

The PL360 parameters related to the coupling are configured in the layer immediately above the PL360 HostController. Depending on the Microchip example application, this layer is:

• PHY applications: Application Layer• PLC&Go+: Application Layer• Full-stack applications: Physical Abstraction Layer (PAL)

There are two steps to adapt the coupling configuration properly:1. 2.3.1 Disable PLCOUP011 Configuration2. 2.3.2 PL360 Physical Calibration (optional)

2.3.1 Disable PLCOUP011 ConfigurationInformation: This step is only required in the case of using the hardware coupling design PLCOUP006 for the FCCworking band because the starting point is a project for the PL360G55CF-EK.

PLCOUP011 is a double-branch coupling design:• The first branch to work in the CENELEC-A band• The second branch to work in the FCC band

AN3495Firmware


For the FCC working band, the PL360 binary loads by default the coupling configuration for PLCOUP006 (see Table2-3). PL360G55CF-EK projects modify the coupling configuration to work with PLCOUP011, so the first step to adaptPL360G55CF-EK projects to PL485 and PLCOUP006 is to disable the configuration of PLCOUP011.

The configuration of PLCOUP011 affects the following parameters:• Transmission Mode: PLCOUP011 does not have the PLCOUP006 branch optimized for high impedance, so the

transmission mode is forced to VERY_LOW:– Auto-Detect Impedance Mode set to value 0 or 2 in order to disable the Automatic Transmission Mode

Control– Transmission Mode set to value 2 in order to set VERY_LOW mode

• DACC Table: The PL360 is configured to use only the second branch

Information: Please refer to the PL360 Host Controller document for more information about these parameters.

In the Microchip firmware examples, the PLCOUP011 configuration is set at compilation time. Depending on theexample application, the definition to enable the PLCOUP011 configuration may vary:

• CONF_ENABLE_C11_CFG• CONF_APP_ENABLE_C11_CFG• PAL_ENABLE_C11_CFG

In order to use PLCOUP006, the PLCOUP011 configuration must be disabled:1. Find all references to the macro definitions in the example code shown above.2. Make sure that all the code enabled by those references is not compiled (i.e., commenting the #define

directive and/or deleting the blocks of code controlled by the #ifdef directive).

2.3.2 PL360 Physical Calibration (optional)The coupling configuration provided by Microchip is calibrated for Microchip hardware coupling reference designs(PLCOUP006, PLCOUP007, PLCOUP011, PLCOUP012, PLCOUP014, etc.). For other hardware coupling designs,the customer may need to perform a calibration and update the coupling configuration parameters through the PL360Host Controller.

Info: Please refer to the PL360 Physical Calibration document for more information about theseparameters.

2.4 PL360 Binary (optional)Depending on the PLC protocol and working band, the appropriate binary must be loaded to the PL360. In theworkspaces provided by Microchip, the PL360 binaries are located in folder atpl/bin.

The G3-PLC example projects for the PL360G55CF-EK are configured by default as multiband (CENELEC-A / FCC).Thus, both G3-PLC CENELEC-A and FCC PL360 binaries are loaded in the flash memory. If the application does notrequire the multiband functionality, the non-used binary can be removed to save flash memory. In the case of theCENELEC-A working band, the G3-PLC FCC binary can be removed from the project, while in the case of FCCworking band, the G3-PLC CENELEC-A binary can be removed from the project.

In order to remove one of the binaries from the project, i.e., change from a multiband to a single band project, followthese steps:

1. Modify source code: 2.4.1 Binary Addressing Function2. Modify linker configuration: 2.4.2 Linker Configuration

2.4.1 Binary Addressing FunctionFirst, the function that gets the PL360 binary address has to be modified. This function is called_get_pl360_bin_addressing() and is located at the layer immediately above the PL360 Host Controller (seechapter 2.3 Coupling Configuration).

AN3495Firmware


Important: The function _get_pl360_bin_addressing() may slightly differ depending on theapplication, but the purpose is the same.

For G3-PLC full-stack applications, the function code is:

/** * \brief Get ATPL360 binary addressing. * * \param pul_address Pointer to store the initial address of ATPL360 binary data * \param u8Band PHY band: MAC_WRP_BAND_FCC = 2, Otherwise MAC_WRP_BAND_CENELEC_A * * \return Size of ATPL360 binary file */static uint32_t _get_atpl360_bin_addressing(uint32_t *pul_address, uint8_t u8Band){ uint32_t ul_bin_addr; uint8_t *puc_bin_start; uint8_t *puc_bin_end;

#if defined(CONF_LINK_MULTIPLE_PL360_BIN) || BOARD == PL360G55CF_EK #if defined (__CC_ARM) if (u8Band == MAC_WRP_BAND_FCC) { extern uint8_t atpl_bin_fcc_start[]; extern uint8_t atpl_bin_fcc_end[]; ul_bin_addr = (int)(atpl_bin_fcc_start - 1); puc_bin_start = atpl_bin_fcc_start - 1; puc_bin_end = atpl_bin_fcc_end; } else { extern uint8_t atpl_bin_cena_start[]; extern uint8_t atpl_bin_cena_end[]; ul_bin_addr = (int)(atpl_bin_cena_start - 1); puc_bin_start = atpl_bin_cena_start - 1; puc_bin_end = atpl_bin_cena_end; }

#elif defined (__GNUC__) if (u8Band == MAC_WRP_BAND_FCC) { extern uint8_t atpl_bin_fcc_start; extern uint8_t atpl_bin_fcc_end; ul_bin_addr = (int)&atpl_bin_fcc_start; puc_bin_start = (uint8_t *)&atpl_bin_fcc_start; puc_bin_end = (uint8_t *)&atpl_bin_fcc_end; } else { extern uint8_t atpl_bin_cena_start; extern uint8_t atpl_bin_cena_end; ul_bin_addr = (int)&atpl_bin_cena_start; puc_bin_start = (int)&atpl_bin_cena_start; puc_bin_end = (int)&atpl_bin_cena_end; }

#elif defined (__ICCARM__) if (u8Band == MAC_WRP_BAND_FCC) { #pragma section = "P_atpl_bin_fcc" extern uint8_t atpl_bin_fcc; ul_bin_addr = (int)&atpl_bin_fcc; puc_bin_start = __section_begin("P_atpl_bin_fcc"); puc_bin_end = __section_end("P_atpl_bin_fcc"); } else { #pragma section = "P_atpl_bin_cena" extern uint8_t atpl_bin_cena; ul_bin_addr = (int)&atpl_bin_cena; puc_bin_start = __section_begin("P_atpl_bin_cena"); puc_bin_end = __section_end("P_atpl_bin_cena"); }

#else #error This compiler is not supported for now. #endif#else (void)u8Band; #if defined (__CC_ARM) extern uint8_t atpl_bin_start[];

AN3495Firmware


extern uint8_t atpl_bin_end[]; ul_bin_addr = (int)(atpl_bin_start - 1); puc_bin_start = atpl_bin_start - 1; puc_bin_end = atpl_bin_end; #elif defined (__GNUC__) extern uint8_t atpl_bin_start; extern uint8_t atpl_bin_end; ul_bin_addr = (int)&atpl_bin_start; puc_bin_start = (int)&atpl_bin_start; puc_bin_end = (int)&atpl_bin_end; #elif defined (__ICCARM__) #pragma section = "P_atpl_bin" extern uint8_t atpl_bin; ul_bin_addr = (int)&atpl_bin; puc_bin_start = __section_begin("P_atpl_bin"); puc_bin_end = __section_end("P_atpl_bin"); #else #error This compiler is not supported for now. #endif#endif *pul_address = ul_bin_addr; /* cppcheck-suppress deadpointer */ return ((uint32_t)puc_bin_end - (uint32_t)puc_bin_start);}

Notice: The code is divided in two blocks (multiband and single band), but only one of them is compiled.

In order to use only one binary, make sure that the single band version of _get_pl360_bin_addressing() iscompiled.

2.4.2 Linker ConfigurationThe G3-PLC example projects for PL360G55CF-EK are configured as multiband (CENELEC-A / FCC). Thus, bothG3-PLC CENELEC-A and FCC binaries are linked in the project. If only one band is going to be used, one of thebinaries can be unlinked from the project.

Instructions to do so are detailed for each of the supported toolchains in the following sections:• 2.4.2.1 IAR Embedded Workbench®• 2.4.2.2 Atmel Studio• 2.4.2.3 Keil μVision®

2.4.2.1 IAR Embedded Workbench®Go to Project → Options → Linker → Extra Options.

In Command line options the following can be seen:

--image_input $PROJ_DIR$\..\..\..\..\..\..\atpl\bin\ATPL360B_G3_MAC_RT_CENA.bin,atpl_bin_cena,P_atpl_bin_cena,8--keep atpl_bin_cena--image_input $PROJ_DIR$\..\..\..\..\..\..\atpl\bin\ATPL360B_G3_MAC_RT_FCC.bin,atpl_bin_fcc,P_atpl_bin_fcc,8--keep atpl_bin_fcc

To use G3-PLC in single band with CENELEC-A, the code should be changed to:

--image_input $PROJ_DIR$\..\..\..\..\..\..\atpl\bin\ATPL360B_G3_MAC_RT_CENA.bin,atpl_bin,P_atpl_bin,8--keep atpl_bin

To use G3-PLC in single band with FCC, the code should be changed to:

--image_input $PROJ_DIR$\..\..\..\..\..\..\atpl\bin\ATPL360B_G3_MAC_RT_FCC.bin,atpl_bin,P_atpl_bin,8--keep atpl_bin

AN3495Firmware


Notice: This example corresponds to a G3-PLC full stack application which uses a MAC RT binary. Incase of Physical Layer applications, the PHY binary is used (see Table 2-4).

2.4.2.2 Atmel Studio1. Go to Project → Properties → Build Events.

In Pre-build event command line the following can be seen:

"$(DevEnvDir)/shellutils/cp" $(SolutionDir)\..\..\..\..\..\..\atpl\bin\ATPL360B_G3_MAC_RT_CENA.bin $(MSBuildProjectDirectory)\src\ATPL360CENA.bin "$(DevEnvDir)/shellutils/cp" $(SolutionDir)\..\..\..\..\..\..\atpl\bin\ATPL360B_G3_MAC_RT_FCC.bin $(MSBuildProjectDirectory)\src\ATPL360FCC.bin

To use G3-PLC in single band with CENELEC-A, the code should be changed to:

"$(DevEnvDir)/shellutils/cp" $(SolutionDir)\..\..\..\..\..\..\atpl\bin\ATPL360B_G3_MAC_RT_CENA.bin $(MSBuildProjectDirectory)/src/ATPL360.bin

To use G3-PLC in single band with FCC, the code should be changed to:

"$(DevEnvDir)/shellutils/cp" $(SolutionDir)\..\..\..\..\..\..\atpl\bin\ATPL360B_G3_MAC_RT_FCC.bin $(MSBuildProjectDirectory)/src/ATPL360.bin

Notice: This example corresponds to a G3-PLC full stack application which uses a MAC RTbinary. In case of Physical Layer applications, the PHY binary is used (see Table 2-4).

2. In the project workspace, replace file samg55j19_pl360g55cf_ek\atpl_bin_multi.S, which loads twobinaries in the flash memory, with samg55j19_pl360g55cb_ek\atpl_bin.S, which only loads one binary.

2.4.2.3 Keil μVision®1. In the project directory (samg55j19_pl360g55cf_ek\keil) there are two binaries:

• ATPL360CENA.bin• ATPL360FCC.bin

These binaries are copies from the ones in atpl/bin (see Table 2-4).

To use G3-PLC in single band with CENELEC-A, rename ATPL360CENA.bin to ATPL360.bin and removeATPL360FCC.bin.

To use G3-PLC in single band with FCC, rename ATPL360FCC.bin to ATPL360.bin and removeATPL360CENA.bin.

2. In the project workspace, replace the file samg55j19_pl360g55cf_ek\keil\atpl_bin_multi.S, whichloads two binaries in the flash memory, with samg55j19_pl360g55cb_ek\keil\atpl_bin.S, which onlyloads one binary.

AN3495Firmware


3. References• Microchip Power Line Communications• Microchip Design Support• PL485 Datasheet, 2020• PL360 Datasheet, 2019• PL360 Host Controller, 2019• PL360 Physical Calibration, 2019• PL360G55CB-EK User Guide, 2019• PL360G55CF-EK User Guide, 2019• PLC-AC-Coupler User Guide, 2020• Atmel Studio• Advanced Software Framework• G3-PLC Alliance• PRIME Alliance

AN3495References


http://www.microchip.com/design-centers/smart-energy-products/power-line-communications/overviewhttp://www.microchip.com/support/hottopics.aspxhttp://www.microchip.com/avr-support/atmel-studio-7https://asf.microchip.com/docs/latest/http://www.g3-plc.com/http://www.prime-alliance.org/

4. Revision History

4.1 Rev A - 05/2020Document Initial release.

AN3495Revision History


The Microchip WebsiteMicrochip provides online support via our website at http://www.microchip.com/. This website is used to make filesand information easily available to customers. Some of the content available includes:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’sguides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQs), technical support requests, onlinediscussion groups, Microchip design partner program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing ofseminars and events, listings of Microchip sales offices, distributors and factory representatives

Product Change Notification ServiceMicrochip’s product change notification service helps keep customers current on Microchip products. Subscribers willreceive email notification whenever there are changes, updates, revisions or errata related to a specified productfamily or development tool of interest.

To register, go to http://www.microchip.com/pcn and follow the registration instructions.

Customer SupportUsers of Microchip products can receive assistance through several channels:

• Distributor or Representative• Local Sales Office• Embedded Solutions Engineer (ESE)• Technical Support

Customers should contact their distributor, representative or ESE for support. Local sales offices are also available tohelp customers. A listing of sales offices and locations is included in this document.

Technical support is available through the website at: http://www.microchip.com/support

Microchip Devices Code Protection FeatureNote the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.• Microchip believes that its family of products is one of the most secure families of its kind on the market today,

when used in the intended manner and under normal conditions.• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these

methods, to our knowledge, require using the Microchip products in a manner outside the operatingspecifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft ofintellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code

protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protectionfeatures of our products. Attempts to break Microchip’s code protection feature may be a violation of the DigitalMillennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, youmay have a right to sue for relief under that Act.

Legal NoticeInformation contained in this publication regarding device applications and the like is provided only for yourconvenience and may be superseded by updates. It is your responsibility to ensure that your application meets with

AN3495


http://www.microchip.com/http://www.microchip.com/pcnhttp://www.microchip.com/support

your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHEREXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from suchuse. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unlessotherwise stated.

TrademarksThe Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip TechnologyIncorporated in the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom,CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial QuadI/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks ofMicrochip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of MicrochipTechnology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.© 2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 978-1-5224-6096-1

Quality Management SystemFor information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality.

AN3495


http://www.microchip.com/quality

AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPECorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200Fax: 480-792-7277Technical Support:http://www.microchip.com/supportWeb Address:http://www.microchip.comAtlantaDuluth, GATel: 678-957-9614Fax: 678-957-1455Austin, TXTel: 512-257-3370BostonWestborough, MATel: 774-760-0087Fax: 774-760-0088ChicagoItasca, ILTel: 630-285-0071Fax: 630-285-0075DallasAddison, TXTel: 972-818-7423Fax: 972-818-2924DetroitNovi, MITel: 248-848-4000Houston, TXTel: 281-894-5983IndianapolisNoblesville, INTel: 317-773-8323Fax: 317-773-5453Tel: 317-536-2380Los AngelesMission Viejo, CATel: 949-462-9523Fax: 949-462-9608Tel: 951-273-7800Raleigh, NCTel: 919-844-7510New York, NYTel: 631-435-6000San Jose, CATel: 408-735-9110Tel: 408-436-4270Canada - TorontoTel: 905-695-1980Fax: 905-695-2078

Australia - SydneyTel: 61-2-9868-6733China - BeijingTel: 86-10-8569-7000China - ChengduTel: 86-28-8665-5511China - ChongqingTel: 86-23-8980-9588China - DongguanTel: 86-769-8702-9880China - GuangzhouTel: 86-20-8755-8029China - HangzhouTel: 86-571-8792-8115China - Hong Kong SARTel: 852-2943-5100China - NanjingTel: 86-25-8473-2460China - QingdaoTel: 86-532-8502-7355China - ShanghaiTel: 86-21-3326-8000China - ShenyangTel: 86-24-2334-2829China - ShenzhenTel: 86-755-8864-2200China - SuzhouTel: 86-186-6233-1526China - WuhanTel: 86-27-5980-5300China - XianTel: 86-29-8833-7252China - XiamenTel: 86-592-2388138China - ZhuhaiTel: 86-756-3210040

India - BangaloreTel: 91-80-3090-4444India - New DelhiTel: 91-11-4160-8631India - PuneTel: 91-20-4121-0141Japan - OsakaTel: 81-6-6152-7160Japan - TokyoTel: 81-3-6880- 3770Korea - DaeguTel: 82-53-744-4301Korea - SeoulTel: 82-2-554-7200Malaysia - Kuala LumpurTel: 60-3-7651-7906Malaysia - PenangTel: 60-4-227-8870Philippines - ManilaTel: 63-2-634-9065SingaporeTel: 65-6334-8870Taiwan - Hsin ChuTel: 886-3-577-8366Taiwan - KaohsiungTel: 886-7-213-7830Taiwan - TaipeiTel: 886-2-2508-8600Thailand - BangkokTel: 66-2-694-1351Vietnam - Ho Chi MinhTel: 84-28-5448-2100

Austria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4485-5910Fax: 45-4485-2829Finland - EspooTel: 358-9-4520-820France - ParisTel: 33-1-69-53-63-20Fax: 33-1-69-30-90-79Germany - GarchingTel: 49-8931-9700Germany - HaanTel: 49-2129-3766400Germany - HeilbronnTel: 49-7131-72400Germany - KarlsruheTel: 49-721-625370Germany - MunichTel: 49-89-627-144-0Fax: 49-89-627-144-44Germany - RosenheimTel: 49-8031-354-560Israel - Ra’ananaTel: 972-9-744-7705Italy - MilanTel: 39-0331-742611Fax: 39-0331-466781Italy - PadovaTel: 39-049-7625286Netherlands - DrunenTel: 31-416-690399Fax: 31-416-690340Norway - TrondheimTel: 47-72884388Poland - WarsawTel: 48-22-3325737Romania - BucharestTel: 40-21-407-87-50Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91Sweden - GothenbergTel: 46-31-704-60-40Sweden - StockholmTel: 46-8-5090-4654UK - WokinghamTel: 44-118-921-5800Fax: 44-118-921-5820

Worldwide Sales and Service


http://www.microchip.com/supporthttp://www.microchip.com

IntroductionTable of Contents1. Hardware1.1. CENELEC-A1.2. CENELEC-B1.3. FCC1.4. Multiband (CENELEC-A / FCC)

2. Firmware2.1. Board Support Package (BSP)2.1.1. BSP Header File2.1.2. BSP Initialization File

2.2. Working Band2.2.1. Configure G3-PLC Working Band2.2.2. Configure PRIME Working Band

2.3. Coupling Configuration2.3.1. Disable PLCOUP011 Configuration2.3.2. PL360 Physical Calibration (optional)

2.4. PL360 Binary (optional)2.4.1. Binary Addressing Function2.4.2. Linker Configuration2.4.2.1. IAR Embedded Workbench®2.4.2.2. Atmel Studio2.4.2.3. Keil μVision®

3. References4. Revision History4.1. Rev A - 05/2020

The Microchip WebsiteProduct Change Notification ServiceCustomer SupportMicrochip Devices Code Protection FeatureLegal NoticeTrademarksQuality Management SystemWorldwide Sales and Service

Using PL485 to Implement a Fully Featured G3-PLC/PRIME Modemww1.microchip.com/downloads/en/Appnotes/AN3495-Using-PL485-t… · P L _ E M I T [ 0 . . 3 ] PL C Co u pl i ng PLC_Coupling

Documents