Page 1
Using IBIS-AMI in the Modeling of Advanced SerDes Equalization for Serial Link Simulation
CDNLive Boston
August 2013
Mark Marlett and Mahesh Tirupattur, Analog Bits
Ken Willis and Kumar Keshavan, Cadence Design Systems
Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. All other trademarks and logos are the property
of their respective holders.
Page 2
2 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Agenda
• Introduction
• Motivation for AMI modeling
• Why channel simulation?
• What is IBIS-AMI?
• Case study > Analog Bits SerDes
Page 3
3 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Agenda
• Introduction
• Motivation for AMI modeling
• Why channel simulation?
• What is IBIS-AMI?
• Case study > Analog Bits SerDes
Page 4
4 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Broadest Portfolio of Differentiated IP Billions in Silicon
Page 5
5 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
• Multi-Rate Multi-Protocol SERDES
– Lowest power & latency
– Smallest area
– Programmable for numerous channel environments
• SOC applications
Lowest Power SERDES
FPGA Consumer
Cables
Mobile
Computing
Supercomputers &
Communications
Flat Panel
Display
Page 6
6 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
10 Years of SERDES Track Record 1st Time Right in over 10 processes
2005 2006 2007 2010 2011 / 2012 2002
4Gb/s
2Gb/s 0.18um
ISP
0.13um
SATA & PCI Qual
7Gb/s 65nm
7G Performance
7mW/
Gbps
12Gb/s 45/40nm
10G+ Speeds
5mW/
Gbps
32nm/28nm 14Gb/s
4.2mW/
Gbps
5Gb/s 90nm/80nm
SATA, PCI-E, Backplanes
10mW/
Gbps
Page 7
7 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
SERDES differentiates Networking to Consumer SoCs
100Terabits/sec. Supercomputer
28 SERDES implemented in 7 Quads
27 chips in board, 36 boards in chassis
Measured Bit Error Rate <10-23
Modern Fanless PC Graphics Card
x16 PCI Express SERDES Pixel Class PLLs,
Low Jitter X-tal oscillators and multiport RAMs
Multi-core processor with
72 Lanes of 10G+ SERDES under 3 sq.mm
DDR3 IOs and Clocking IPs
V-by-One SERDES in 3D Display TV’s
Low Power 4 x 10.315Gbps
Wire-bond package
Page 8
8 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Agenda
• Introduction
• Motivation for AMI modeling
• Why channel simulation?
• What is IBIS-AMI?
• Case study > Analog Bits SerDes
Page 9
9 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Analog Bits Motivation for AMI
• Strong demand from chip customers to provide AMI models for SerDes IP – Considered part of doing SerDes IP business today
– Systems customers of those chips strongly demand AMI to support simulation efforts
• Enables up-front feasibility analysis with customer channels during pre-sales phase
• Enables in-house system simulation for package and test board designs
Page 10
10 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Why Analog Bits partnered with Cadence/Sigrity for AMI
• Technical Experience – IBIS-AMI spec driven by Dr. Kumar Keshavan of Cadence in 2007
• Strong AMI IP Library base to work from – Many top-level modules for SerDes equalization could be
leveraged
– Accelerates turnaround and reduces time-to-customer
• Spirit of partnership – Close collaboration by Sigrity with Analog Bits engineering team
Page 11
11 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Agenda
• Introduction
• Motivation for AMI modeling
• Why channel simulation?
• What is IBIS-AMI?
• Case study > Analog Bits SerDes
Page 12
12 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Why is Channel Simulation + AMI required?
• Multi-gigabit serial links need to pass LOTS of data traffic to give reliable eye diagrams
• Multi-gigabit serial links need to pass LOTS of data traffic to provide enough samples to accurately predict BER
• Multi-gigabit SerDes devices often utilize adaptive equalization, which need to pass LOTS of data traffic before they stabilize and lock in
• Data rates have risen from 2.5 to 25Gbps in about 10 years
• Future designs targeting 400Gbps to 1Tbps
• To accurately simulate multi-gigabit serial links, you need to simulate very large bit streams with very fast and accurate equalization models
TX RX Channel/System
Interconnect
Page 13
13 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Channel Simulation Provides Ultra High Capacity
• Focuses on a single Rx
• Analog channel is
exercised in Spice to
produce an impulse
response
• Impulse response is
convolved with the bit
stream to produce raw
waveforms
• Can simulate millions of
bits in minutes
• Supports AMI models
for EQ
Channel Simulator
Package
Interconnect
System
Interconnect Package
Interconnect
impulse
response
Page 14
14 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Agenda
• Introduction
• Motivation for AMI modeling
• Why channel simulation?
• What is IBIS-AMI?
• Case study > Analog Bits SerDes
Page 15
15 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
AMI > Algorithmic Modeling Interface
• Extension made to IBIS in 2007
• Enables executable, software-based, algorithmic models to work together with traditional IBIS circuit models
• Enables SerDes adaptive equalization algorithms to be modeled and used during channel simulation
Page 16
16 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Motivation for AMI
Package
Interconnect
System
Interconnect Package
Interconnect
FFE
Sampler
Clock
recovery
out
Supplier “A”
Tx
Rx
• The intent of IBIS-AMI is to enable plug-and-play simulation compatibility between SerDes models from different suppliers, in a standard commercial EDA format
Supplier “B”
CTLE
Page 17
17 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
IBIS-AMI Model Sub-Components
• Circuit part − IO buffer stage
− Voltage swing
− Parasitics
− Spice or traditional IBIS format
• Algorithmic part − On-chip
− Equalization functionality
− DLL + AMI file
Page 18
18 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Characterizing the Analog Circuit
• Analog circuit part of channel separated from algorithmic EQ
Tx Rx
Serial Link Data out
FFE DFE/CDR
Package
Interconnect
System
Interconnect Package
Interconnect
Analog Channel
Page 19
19 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
APIs in IBIS-AMI Modeling
• AMI_Init for “one-time
adaptive EQs
• AMI_GetWave for “real-time”
adaptive EQs
AMI_Init -Initialize filter
- Setup Data Structures Model input parameters
Impulse Response Modified Impulse Response
AMI_Close -Free memory etc.
AMI_GetWave -Waveform Processing
-Clock and Data Recovery Continuous waveform
Clock tics
Equalized waveform
Page 20
20 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
IBIS-AMI and Channel Simulation
Channel Simulator
Package
Interconnect
System
Interconnect Package
Interconnect
FFE DFE
Channel Eye @ Slicer
Page 21
21 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Agenda
• Introduction
• Motivation for AMI modeling
• Why channel simulation?
• What is IBIS-AMI?
• Case study > Analog Bits SerDes
Page 22
22 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Case Study > Analog Bits Transmitter
• Tools
• Transmitter equalization
• Channel simulation vs. transistor-level HSpice simulation
• AMI model for equalization vs. transistor-level Spice
Page 23
23 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Cadence‟s SystemSI – Serial Link Analysis
• Provides a comprehensive environment for the accurate
assessment of high speed serial links to ensure robust IC
package and PCB implementations.
Page 24
24 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Cadence‟s Algorithmic Model IP Library
• FFE – Feed Forward Equalizer
• CDR – Clock and Data Recovery
• CTLE – Continuous Time Linear Equalizer • Standard
• Adaptive, with integrated CDR and DFE
• DFE – Decision Feedback Equalizer • Standard
• Non-linear with “lookahead” gain
• AGC – Automatic Gain Control
Custom AMI model development available
Source code available as baseline
Fully IBIS-5.0 compliant
Page 25
25 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Transmitter Equalization - FFE
• FFE stands for Feed
Forward Equalizer
• Typically used in Tx
• Mathematically
− yn = S wi*xi
− Xn – input − Yn – output
Z-1 Z-1
+
w0 w1
xn
yn
Page 26
26 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Test System: PCB=Xaui channel Rx= simple terminator
Wrapped silicon model,
Pre=post=0
Xaui
channel
50 0.25p
Page 27
27 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Characterization Step Response (Tx pre=post=0)
Step Response
Leading pattern
Required for silicon model
Page 28
28 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Channel Simulation vs. Transistor-Level Spice 10 Gbps – PRBS 21
SystemSI
Transistor-Level Spice
Page 29
29 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Test System: PCB=Xaui channel Rx= simple terminator Tx= behavioral Spice circuit + AMI for FFE
Force sum of pre+main+post = 1
amiffe settings
Page 30
30 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Test System Results
Page 31
31 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
SystemSI vs. Transistor-Level Spice with Tx Equalization
SystemSI
HSpice Silicon
Page 32
32 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Case Study > Analog Bits Receiver (Rx)
• Rx is considerably more complex
• Novel Rx architecture – Nonlinear Rx with feedback
– Includes – Automatic gain control (AGC)
– Continuous time equalizer (CTE)
– 1 tap Decision Feedback Equalizer (DFE)
– 63 possible CTE „codes‟
– Automatic adaptation for those codes
– DFE adaptation
Page 33
33 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Rx Block Diagram
Page 34
34 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Rx AMI Generic Architecture
3
4
Note: There is no limit on the number of cascaded blocks
Feed back for adaptation
Page 35
35 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Rx AMI Model Challenges
• Model/map nonlinear CTE (CTNLE) to an AMI model with reasonable performance
• Implement complex CTNLE adaptation scheme
• Integrate Tx and backchannel Tx adaptation – Backchannel adaptation is being proposed as an IBIS standard as
BIRD 147
Page 36
36 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Nonlinear „CTNLE‟
• Map to „piecewise‟ input voltage dependent step responses – step response represent the cte at time „t‟ and voltage v_in(t)
ctnle in out
ctnle ctnle
select
in out
Page 37
37 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Novel „Dynamic‟ Convolution Algorithm with Time Dependent Impulse Response
Vin(t)
r
Vout(t)
Vout(t) = Vin(t) * r
Vin(t)
r{coeff(Vin(t, t_prev)}
Vout(t)
Vout(t) = Vin(t) * r{coeff(Vin(tm t_prev))}
Page 38
38 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
CTNLE Adaptation
N adaptation
bits
CTE
code Vin
Code up/down signal
Generate
Error Signal
Page 39
39 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
AMI Operation -- Input to AMI Model
Page 40
40 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
AMI Operation -- Output of AMI Model
Page 41
41 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
AMI Operation -- DFE Adaptation
-90mV by ~6us
Page 42
42 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
SystemSI vs. Transistor-Level Spice with Rx Equalization
Page 43
43 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Summary
• IBIS-AMI is today‟s standard format for system-level SerDes modeling
• A different type of modeling expertise is required to develop AMI models
• Modeling the adaptive CTNLE functionality in the Analog Bits Rx is the most challenging AMI effort we have undertaken to date
• Transistor-level accuracy can be obtained with high-capacity channel simulation to predict BER using AMI modeling, even for the most complex EQ architectures
Page 44
44 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.