User's Guide - TI.com of this User’s Guide for resistor locations. Table 2. Bootstrap Resistor Designation and Suggested Bootstrap Resistor Values Pin Name Pin Number Strap

DP83822 EVM

User's Guide

Literature Number: SNLU179August 2016

2 SNLU179–August 2016Submit Documentation Feedback

Copyright © 2016, Texas Instruments Incorporated

Table of Contents

Contents

1 Introduction......................................................................................................................... 41.1 Operation – Quick Setup ................................................................................................ 7

2 Board Setup Details ............................................................................................................ 102.1 Block Diagram........................................................................................................... 102.2 Power Supply Options ................................................................................................. 112.3 Serial Management and MAC Interfaces ............................................................................ 142.4 LED Options ............................................................................................................. 152.5 Bootstrap Options/Jumpers ........................................................................................... 162.6 Clock Options ........................................................................................................... 172.7 100BASE-FX Configuration (Fiber)................................................................................... 18

3 Schematic ......................................................................................................................... 193.1 Hardware Schematic ................................................................................................... 193.2 Main Block Schematic.................................................................................................. 203.3 Power Block Schematic................................................................................................ 213.4 Analog Front-End Schematic.......................................................................................... 223.5 Connector and Bootstrap Schematic................................................................................. 23

4 Layout............................................................................................................................... 244.1 Top Overlay ............................................................................................................. 244.2 Top Layer ................................................................................................................ 244.3 Signal Layer 1........................................................................................................... 254.4 Signal Layer 2........................................................................................................... 254.5 Signal Layer 3........................................................................................................... 264.6 Signal Layer 4........................................................................................................... 264.7 Bottom Layer ............................................................................................................ 274.8 Bottom Overlay.......................................................................................................... 274.9 Board Assembly ........................................................................................................ 28

5 Bill of Materials .................................................................................................................. 29

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SNLU179

3SNLU179–August 2016Submit Documentation Feedback


DP83822 EVM

User's GuideSNLU179–August 2016

DP83822 EVM

This User’s Guide details the characteristics, operation, and use of the DP83822 10/100 Mbps IndustrialEthernet PHY. The EVM enables Texas Instruments’ customers to quickly design and market systemsusing the DP83822. This document also includes schematic diagrams, a printed-circuit board layout,board assembly, board marking drawings, and a bill of materials.

Table 1. Terminology

Acronym DefinitionPHY Physical Layer TransceiverMAC Media Access ControllerEEE Energy Efficient EthernetWoL Wake-on-LANSMI Serial Management Interface

MDIO Management Data I/OMDC Management Data ClockSFP Small Form-Factor Pluggable (Fiber Transceiver)MII Media Independent Interface

RMII Reduced Media Independent InterfaceRGMII Reduced Gigabit Media Independent InterfaceSFD Start-of-Frame Detection

CAT5 Category 5 (cable electrical characteristics)AVD Analog Supply Rail

VDDIO Digital Supply RailCT Center Tap Supply RailPD Pull-DownPU Pull-Up


Introduction www.ti.com



DP83822 EVM

1 IntroductionThe DP83822 EVM supports 10/100 Mbps and is compliant to the IEEE 802.3u standard. This referencedesign supports MII, RMII and RGMII MAC interfaces.

The DP83822 EVM includes two onboard status LEDs, optional Fiber SFP connector and cage, andonboard supply through a 5-V micro USB connector. The DP83822 EVM is capable of providing a 125-MHz, 50-MHz or 25-MHz reference clock from an onboard 25-MHz crystal. The EVM includes theCDCE925 programmable 2-PLL VCXO clock synthesizer with 1.8-V to 3.3-V LVCMOS outputs. Serialmanagement interface, MDIO/MDC, is supported and can be used to access PHY registers for additionalfeatures. There are 4-level straps, which allow for system configurations without the need to directlyaccess PHY registers. External power supplies can be connected to each specified voltage rail foradditional system evaluation. The DP83822 supports Wake-on-LAN, Energy Efficient Ethernet(IEEE802.3az), Start-of-Frame Detect IEEE 1588 Time Stamp, and configurable I/O voltages.

Key Features:• IEEE 802.3u Compliant: 100BASE-FX, 100BASE-TX and 10BASE-Te• CDCE925 Programmable 2-PLL VCXO Clock Synthesizer with 1.8 V to 3.3 V• MII, RMII and RGMII MAC interfaces• SFD IEEE 1588 Time Stamp• Two status LEDs

– LED LINK/ACTIVITY– LED SPEED

• Low Power Modes– Energy Efficient Ethernet (IEEE802.3az)– Wake-on-LAN– Active Sleep– Passive Sleep– IEEE Power Down– Deep Power Down

• Variable I/O voltage range: 1.8 V, 2.5 V and 3.3 V• 100BASE-TX error free data transfer over 150 meters on CAT5 cable

The DP83822 EVM has an RJ45 connector (J12) with discrete magnetics and stuffing resistor array forconfigurable bootstraps. Customers are encouraged to use a design similar to the EVM circuit to expeditetheir product development.

http://www.ti.com


www.ti.com Introduction



DP83822 EVM

Figure 1. DP83822 EVM – Top Side

http://www.ti.com





DP83822 EVM

Figure 2. DP83822 EVM - Bottom Side

http://www.ti.com





DP83822 EVM

1.1 Operation – Quick Setup1. Select internal supply by populating the following with jumpers (J6):

(a) Place jumper #1 at ‘AVD INT’ position(b) Place jumper #2 at ‘CT INT’ position(c) Place jumper #3 at ‘VDDIO INT’ position

Figure 3. On-Board Power Supply Configuration

2. Select VDDIO voltage level (R26):• 4.22 kΩ - 3.3 V operation (Default)• 2.56 kΩ - 2.5 V operation• 1.20 kΩ - 1.8 V operation

3. Select AVD voltage level (R19):• 4.22 kΩ - 3.3 V operation (Default)• 1.20 kΩ - 1.8 V operation

http://www.ti.com





DP83822 EVM

4. Select reference clock frequency (J2):• 25 MHz – jumper across pins 1 and 2• 50 MHz – jumper across pins 2 and 3

Figure 4. Reference Clock Selection

5. Place a jumper in the ‘PU’ position for LED LINK/ACT (J10)

Figure 5. LED LINK/ACT Selection

6. Turn ON the PHY by connecting a 5-V micro USB power supply to J57. Plug a CAT5, CAT5E or CAT6 cable into the RJ45 connector (J12)8. Connect the far-end of the Ethernet cable to a link partner9. Connect a MAC interface to J13 and J14• LED Indication

– The AVD LED (D1) and VDDIO LED (D2) will be illuminated if the 5-V supply is connected– Look for the LINK LED (D4) to light up on the DP83822 EVM after the PHY links with a connected

partner

http://www.ti.com





DP83822 EVM

Figure 6. MAC IF Connection and LED Indication

http://www.ti.com


DP83822

DUT

5-V Turret /

USB

VDDIO LDO

1.8-V, 2.5-V, 3.3-V

MDIO / MDC

GPIOs

AVD & CT LDO

1.8-V or 3.3-V

AVD

VDDIO

5-V3.3-V / 2.5-V / 1.8-V

External Supplies

CDCE925

Bootstrap

Resistors /

Jumpers

MAC

MII / RMII / RGMII

Magnetics

RJ45

Capacitive

Isolation

Fiber

Termination

SFPCAT5

Cable

LED LINK /

ACT

LED SPEED

EVM

14 Pin

Header

26 Pin

Header

MII /

RMII /

RGMII

External

Clock

Board Setup Details www.ti.com



DP83822 EVM

2 Board Setup Details

2.1 Block Diagram

Figure 7. DP83822 EVM Block Diagram

http://www.ti.com


www.ti.com Board Setup Details



DP83822 EVM

2.2 Power Supply OptionsThe DP83822 EVM power is supplied by a single 5-V connection. This option uses onboard LDOs toprovide 3.3-V, 2.5-V or 1.8-V rails. Connect 5-V supply to either the USB micro A/B connector (J5) or V+1turret and populate jumpers on J6 as specified in Section 1.1 for onboard supplies. When using the V+1turret, GND1 turret should be used as the ground connection.

Figure 8. Onboard Supply Connection

http://www.ti.com





DP83822 EVM

The DP83822 EVM also supports external supply connections. External supply option bypasses theonboard LDOs and allows for direct connections to each supply rail.

To configure the DP83822 EVM for external supply operation, use the following jumper configuration (J6):• Place jumper #1 at ‘AVD EXT’ position• Place jumper #2 at ‘CT EXT’ position• Place jumper #3 at ‘VDDIO EXT’ position

Figure 9. External Supply Configuration

http://www.ti.com





DP83822 EVM

There are three supply rail turrets for external supply connection. The three turrets are shown in the imagebelow. ‘GND1’ should be used as the ground connection for each of the three supply rails.• ‘External AVD’ – External AVD supply rail• ‘External CT’ – External Center Tap supply rail• ‘External VDDIO’ – External VDDIO supply rail

Figure 10. External Turret Connection

http://www.ti.com





DP83822 EVM

2.3 Serial Management and MAC InterfacesThe DP83822 EVM supports SMI (MDIO/MDC) and MII, RMII and RGMII MAC interfaces. SMI isaccessible though J14. MDIO is located at pin 23 and MDC is located at pin 21. Ground connectionbetween the DP83822 EVM and SMI controller is required for proper operation. DP83822 supports bothclause 22 and clause 45 in the IEEE 802.3 specification. For further SMI support please refer to theEthernet USB2MDIO Application Note for interfacing the MSP430 Launchpad with TI EthernetPHYs.Note: The default PHY_ID is ‘1’. PHY_ID can be changed via bootstrap options found in the datasheet.

MAC interface pins are located on J13 and J14. MII, RMII and RGMII configurations are located in thedatasheet and can be configured by bootstrapping or direct register access through the SMI. Please referto the DP83822 datasheet for specific pin requirements for each MAC interface.

Figure 11. DP83822 EVM MAC IF Connections

http://www.ti.com





DP83822 EVM

2.4 LED OptionsThe DP83822 supports up to three configurable LEDs: Link, Speed and MLED. The DP83822 EVM hastwo onboard LEDs that can be controlled by direct register access using the SMI. LED pins can operateas either current sources (when connected to pull-down) or current sinks (when connected to pull-up).

Figure 12. LED Speed and Link

http://www.ti.com





DP83822 EVM

2.5 Bootstrap Options/JumpersSome DP83822 configurations can be done through bootstrap options. Options can be selected withjumpers or resistor population. Please refer to the datasheet for bootstrap options and schematic/layoutsections of this User’s Guide for resistor locations.

Table 2. Bootstrap Resistor Designation and Suggested Bootstrap Resistor Values

Pin Name Pin Number StrapMode PU Resistor (kΩ) PU Resistor

Designation PD Resistor (kΩ) PD ResistorDesignation

COL 29

1 OPEN

R84

1.96

R882 13 1.963 6.2 1.964 OPEN OPEN

RX_D0 30

1 OPEN

R71

OPEN

R722 10 2.493 5.76 2.494 2.49 OPEN

RX_D1 31

1 OPEN

R75

OPEN

R762 10 2.493 5.76 2.494 2.49 OPEN

RX_D2 32

1 OPEN

R77

OPEN

R782 10 2.493 5.76 2.494 2.49 OPEN

RX_D3 1

1 OPEN

R80

OPEN

R822 10 2.493 5.76 2.494 2.49 OPEN

CRS 27

1 OPEN

R53

1.96

R552 13 1.963 6.2 1.964 OPEN OPEN

RX_ER 28

1 OPEN

R60

1.96

R662 13 1.963 6.2 1.964 OPEN OPEN

RX_DV 26

1 OPEN

R45

OPEN

R482 10 2.493 5.76 2.494 2.49 OPEN

http://www.ti.com





DP83822 EVM

2.6 Clock OptionsThe DP83822 EVM uses the CDCE925 programmable 2-PLL VCXO clock synthesizer. A 25-MHz crystalresonator is connected to the CDCE925, which can then be configured to either a 50-MHz or 25-MHzLVCMOS output in the range of 1.8 V to 3.3 V. The output of the CDCE925 is directly fed into the XI pin ofthe DP83822.

In order to operate with a 25-MHz reference clock, the following modifications are required:• Populate R3 with a 0-Ω resistor• Populate R95 and R96 with 1-kΩ resistors• Remove R4• Place a jumper across pin 1 and pin 2 on J2

In order to operate with a 50-MHz reference clock, the following modifications are required:• Populate R3 with a 0-Ω resistor• Populate R95 and R96 with 1-kΩ resistors• Remove R4• Place a jumper across pin 2 and pin 3 on J2

Table 3. CDCE925 Programmed Clock Setting Selection

S2 S1 S0 Reference Clock Setting0 0 0 25 MHz0 0 1 50 MHz

2.6.1 External ConfigurationAdditionally, the DP83822 EVM has an external reference clock option through an SMA (J1).

The external clock must meet the DP83822 data sheet requirements and to be within 50 MHz or 25 MHzwith ±50ppm tolerance.

The following changes are required to route an external clock to the DP83822:• Populate R4 with a 0-Ω resistor• Populate an SMA at J1• Remove R3

http://www.ti.com





DP83822 EVM

2.7 100BASE-FX Configuration (Fiber)The DP83822 EVM supports 100BASE-FX by use of an SFP transceiver. The DP83822 can be configuredfor 100BASE-FX operation through either bootstrap or SMI register configuration.

To configure the DP83822 EVM for 100BASE-FX operation, the following changes are required:• Remove T2• Remove R34, R35, R28, R29, R30 and R31• Populate C47, C48, C49, C50, C53, C54, C57, C58, C59 and C66• Populate L3 and L4• Populate J15• Populate H1• Populate R36, R41, R42 and R44

Note: It is important to read the termination requirements for the SFP transceiver used. The DP83822EVM allows for custom termination on both receive and transmit paths to ensure support for most SFPtransceivers. Please refer to the schematic/layout for more information regarding the termination network.

Figure 13. SFP Cage and Termination Network

Figure 14. SFP Power Network

http://www.ti.com


FID2FID1 FID3

SV601202

E1

PCB Number:

PCB Rev:

Label Assembly NoteZZ1

This Assembly Note is for PCB labels only

PCB Label

LBL1

Size: 0.65" x 0.20 "

Assembly NoteZZ2

These assemblies are ESD sensitive, ESD precautions shall be observed.

Assembly Note

ZZ3

These assemblies must be clean and free fro m flux and all contaminants. Use of no clean flux is not acceptable.

Assembly NoteZZ4

These assemblies must comply with workmanship standards IPC-A-610 Class 2, unless otherwise specified.

Label Table

Variant Label Text

001 DP83822

002 DP83822F

LOGOPCB

Pb-Free Symbol

LOGOPCB

FCC disclaimer

3V3

RXD_P

RXD_N

TXD_PTXD_N

FX_RD_PFX_RD_N

FX_TD_PFX_TD_N

AFESV601202-001_AFE.SchDoc

AVD

VDDIO

INT_PWDN_N

RESET_N

MDCMDIO

TX_CLK

TX_ENTX_D0TX_D1TX_D2TX_D3

RX_CLK

RX_DV

RX_ERCRS

COLRX_D0RX_D1RX_D2RX_D3

LED_GPIO

LED_0

RXD_N

RXD_P

TXD_NTXD_P

MAINSV601202-001_MAIN_BLOCK.SchDoc

AVD

VDDIO

3V3

LED_0LED_GPIO

PowerSV601202-001_POWER_BLOCK.SchDoc

3V3

FX_TD_PFX_TD_N

FX_RD_N

INT_PWDN_N

RESET_N

MDCMDIO

LED_GPIO

TX_D3TX_D2TX_D1TX_D0TX_EN

TX_CLK

RX_D3RX_D2RX_D1RX_D0

CRSCOL

RX_DV

RX_ERRX_CLK

FX_RD_P

VDDIO

ConnectorsSV601202-001_CONNECTOR.SchDoc

MDC

MDIO

LED_0LED_GPIO

INT_PWDN_N

RESET_N

INT_PWDN_N

RESET_N

MDCMDIO

LED_GPIO

TX_CLKTX_ENTX_D0TX_D1TX_D2

TX_D3

RX_CLKRX_DVCRSRX_ERCOLRX_D0

RX_D1RX_D2RX_D3

TX_D3TX_D2TX_D1

TX_D0TX_ENTX_CLK


CRSCOLRX_DVRX_CLKRX_ER

TXD_PTXD_N

RXD_PRXD_N

FX_TD_PFX_TD_N

FX_RD_PFX_RD_N

LOGOPCB

Texas Instruments

M1 M3 M4 M2

EARTH GND GND

4700pFC69

4700pFC68

SFP_EARTH

Shield1

Shield2

Shield3

Shield4

Shield5

Shield6

Shield 7

Shield 8

Shield9

Shield10

Shield11

Shield12

MH1MH1

MH2MH2

MH3MH3

MH4MH4

MH5MH5

MH6 MH6

MH7 MH7

MH8MH8

H1

U77-A1118-200T

DNP

SFP_EARTHSFP_EARTH

AVD AVD

VDDIO VDDIO

3V3

3V3 3V3VDDIO

LED_0LED_GPIO


www.ti.com Schematic



DP83822 EVM

3 Schematic

3.1 Hardware Schematic

Figure 15. Hardware Schematic

http://www.ti.com


GND

TXD_PTXD_N

RXD_P

RXD_N

RESET_N

INT_PWDN_N

GND

GND

INT_PWDN_N

RESET_N

RESET_N

GND

INT_PWDN_N

MDCMDIO

TX_CLK

TX_D0TX_D1

TX_D2TX_D3

RX_CLK

RX_DV

CRS

RX_ER

COL

RX_D0

RX_D1RX_D2RX_D3

MDCMDIO

TX_CLKTX_EN

RX_D0

TX_D0TX_D1TX_D2TX_D3

RX_CLK

RX_DV

CRS

RX_ER

COL

RX_D1RX_D2RX_D3

TXD_PTXD_N

RXD_PRXD_N

1

2345

J1

DNP

S1

XI

2.21k

R5

2.21kR6

2.21kR9

DNP

2.21kR10

GND

GND

LED_0

LED_GPIO

10µFC27DNP

EXT_CLK

1000pFC17

1000pFC24

100pFC18

100pFC25

0.01µFC16

0.01µFC23

10µFC13

10µFC20

TX_EN

GND

RX_D31

2 3 4 5

J4

22µFC12DNP

LED_GPIO

LED_0

10µFC26DNP

1µFC14DNP

1µFC21DNP

0.1µFC15DNP

0.1µFC22DNP

22µFC19DNP

2.21kR8

DNP

RBIAS

4.87k

Rs1

RX_D3/PHYAD4/CLKOUT1

TX_CLK2

TX_EN3

TX_D04

TX_D15

TX_D26

TX_D37

INT/PWDN8

RD_M9

RD_P10

TD_M11

TD_P12

NC13

AVD3314

NC15

RBIAS 16

LED_0/AN_0/MLED17

RESET 18

MDIO19

MDC20

VDDIO21

XO22

XI23

CLK_O24

RX_CLK25

RX_DV/MII_MODE26

CRS/CRS_DV/LED_CFG27

RX_ER/AMDIX_EN28

COL/PHYAD0/ML ED29

RX_D0/PHYAD130

RX_D1/PHYAD231

RX_D2/PHYAD332

PAD33

U2

DP83822RHBR

VDDIO

VDDIO

AVD

AVD

VDDIOVDDIO

VDDIO

TP1TP2

0

R7DNP

XIN/CLK1

S02

VDD3

VCTR4

GND5

VDDOUT6

Y47

Y58 VDDOUT 9

Y310

Y211

GND 12

Y113

S2/SCL14

S1/SDA 15

XOUT16

U1

CDCE925PWR

25 MHz

134 2

GG Y1GND

12pFC4DNP

12pFC5DNP

GNDGND

18

R3

0R4

DNP

XI

EXT_CLKGND

0.01µFC10

GND

3V3A

1.00kR1

1.00k

R2

+1V8

GND

+1V8

0.01µFC9

GNDGND3V3A

0.01µFC11

GND

GND GND

GND

0.1µFC8

2.2µFC6

2.2µFC7

120 ohm

L2

VDDIO 3V3A

GND

1

2

3

J2

TSW-103-07-T-S

0R92

1.00kR95

1.00k

R94DNP

1.00kR96

1.00k

R93DNP

+1V8 +1V8


Schematic www.ti.com



DP83822 EVM

3.2 Main Block Schematic

Figure 16. Main Block Schematic

http://www.ti.com


GND

SHDN1

IN2

3

OUT4

ADJ5

6

GNDTAB

U4

TL1963AQKTTRQ1

GND

5V_20V

12 Green

D1QTLP630C4TR

12 Green

D2QTLP630C4TR

VDDIO_EXTVDDIO_INT

VDDIO_EXT AVD_EXT 3V3_EXT

J7 J8 J9

V+2

DNP

GND2

DNP

1000pF

C32

100pF

C33

0.01µF

C31

10µFC36

22µFC37DNP

GND

GND

AVD_INT

2.40kR21

4.22k

R19

GND

SHDN1

IN2

3

OUT 4

ADJ 5

6

GNDTAB

U5TL1963AQKTTRQ1

GND

5V_20V

10µFC38

22µFC39DNP

GND

GND

VDDIO_INT

2.40kR27

GND

4.22kR26

470R12

470R13

GND GND

12

43

T1

A2

K1

D3

10µF

C30

4700pF

C28

GNDPWR_CHASSIS

PWR_CHASSIS GND

PWR_CHASSIS

PWR_CHASSIS

1.00M

R11DNP

22µF

C29DNP

5V_20V

1 2

3 4

5 6

7 8

9 10

11 12

J6

V+1

GND1

AVD VDDIO

VDDIO

3V3

AVD

12

Green

D4

QTLP630C4TR

1 2

Green

D5

QTLP630C4TR470

R20

470

R17

GND

LED_0LED_0

12

Green

D6

QTLP630C4TR

1 2

Green

D7

QTLP630C4TR

470

R23

22

11

470

R25

GND

LED_GPIOLED_GPIO

1

2

3

J10

TSW-103-07-G-S

1

2

3

J11

TSW-103-07-G-S

2.49k

R16

2.49k

R18

2.49k

R22

2.49k

R24

VDDIO

VDDIO

AVD_INT3V3_EXTAVD_EXT

AVD_INT

VBUS1

D-2

D+3

ID4

GND5

6 7 8

11

10

9

J50475890001

SHDN1

IN2

3

OUT4

ADJ5

6

GNDTAB

U3TL1963AQKTTRQ1

GND

5V_20V

10µFC34

22µFC35DNP

GND

GND

2.40kR15

GND

1.20kR14

+1V8

AVD:Adjustable Supply

VDDIO:Adjustable Supply

AdjustableSupplies:4.22K for 3.3V

2.56K for 2.5V1.2K for 1.8V





DP83822 EVM

3.3 Power Block Schematic

Figure 17. Power Block Schematic

http://www.ti.com


Cap Isolation

EARTH

EARTH

49.9R39

49.9R40

49.9R37

49.9R38

TXD_P

TXD_N

RXD_P

RXD_N

0.1µF

11 2 2

C47

DNP

Magnetic

1 122

4700pF

C51

1 122

4700pF

C52

DNP

GNDEARTH

EARTH

EARTH

GND

GND

RXD_P

RXD_N

TXD_P

TXD_N

RXD_P

RXD_N

TXD_N

75R34

EARTH

0.1µF

C43

1µF

C42

0.1µF

C45

1µF

C44

GND GND

RXD_CABLE_N

RXD_CABLE_P

TXD_CABLE_N

TXD_CABLE_P

ESD

EARTH

RXD_CABLE_PRXD_CABLE_NTXD_CABLE_N

Termination

RXD_MAG_N

RXD_MAG_P

TXD_MAG_N

TXD_MAG_P

RXD_N

RXD_P

TXD_N

TXD_P

TXD_MAG_P

TXD_MAG_N

GND

1.00M

R43DNP

75R35

0.1µF

11

22

C48

DNP

0.1µF

11

22

C49

DNP

0.1µF

11 2 2

C50

DNP

RXD_MAG_N

RXD_MAG_P

GND

TXD_NTXD_P

RXD_NRXD_P

75R32

75R33

Fiber

RXD_MAG_N

RXD_MAG_P

TXD_MAG_N

TXD_MAG_P

FX_RD_P

FX_TD_N

FX_TD_P

FX_RD_N

FX_RD_P

FX_TD_N

FX_TD_P

GND Coupling

Copper

22

µF

C40DNP

FX_RD_N

0.01µFC46

0.01µF

C41

0

R28

0

R29

0

R30

0

R31

0

R36DNP

0

R41DNP

0

R42DNP

0

R44DNP

D1+1

D1-2

NC6

NC7

NC9

NC10

D2+ 4

D2- 5

GND3

GND8

U6

TPD4E05U06QDQARQ1

DNP

D1+1

D1-2

NC6

NC7

NC9

NC10

D2+ 4

D2- 5

GND3

GND8

U7

TPD4E05U06QDQARQ1

DNP

TXD_CABLE_PTXD_CABLE_NRXD_CABLE_PRXD_CABLE_N

RXD_NRXD_PTXD_NTXD_P

3V3 3V3

3V3

TXD_CABLE_P

2

3

4

1

5

6

7

8

9

10

11

12

J12

1-406541-1

1

2

3

4

5

6

7

89

10

11

12

13

14

15

16

350µH

T2

TXD_P


Schematic www.ti.com



DP83822 EVM

3.4 Analog Front-End Schematic

Figure 18. Analog Front-End Schematic

http://www.ti.com


MAC IF

INT_PWDN_N

CRS

COL

TX_D3TX_D2

TX_D1TX_D0TX_ENTX_CLK

LED_GPIO

RX_ER

RX_CLKRX_DV


MDCMDIORESET_N

MDCMDIORESET_N

INT_PWDN_N

1

3

5

6

4

2

7

9

10

8

12

11

14

13

16

15

18

17

20

19

J15

1367073-1

DNP

Fiber IF

1µH

L3

DNP

1µH

L4

DNP

0.01µFC53DNP

0.01µFC57DNP

10µFC59DNP

0.1µFC54DNP

0.1µFC58DNP

GND

GND

3V3

VCC_R

VCC_T

3V3GND GND

10k

R73DNP

LOS0

R74DNP

LED_GPIO

FX_RD_N

FX_RD_P

FX_TD_N

FX_TD_P

VCC_R

LVPECL Termination

82R85

DNP82R86

DNP82R87

DNP

82R79

DNP

130R89

DNP

22

11

130R90

DNP130R91

DNP

130R81

DNP

GND GND GND

GND

GND

GND

GND GND

FX_RD_P FX_TD_P

FX_TD_N

FX_RD_N

1µFC60DNP

1µFC62DNP

0.1µFC61DNP

0.1µFC63DNP

1µFC64DNP

0.1µFC65DNP

1µFC55DNP

0.1µFC56DNP

4700pF

C66

4700pF

C67

DNP

GNDSFP_EARTH

SFP_EARTH

SFP_EARTH

GND

GND

1.00M

R83DNP

GND Coupling

TX_D3TX_D2TX_D1TX_D0TX_EN

TX_CLK

RX_D3

RX_D2

RX_CLK

RX_D1RX_D0

RX_DV

COLRX_ERCRS

LED_GPIO

FX_TD_N

FX_TD_P

FX_RD_P

FX_RD_N

0

R670

R65

0

R49

0

R57

0

R510

R50

0

R61

0

R63

0

R47

0

R590

R580

R56

0

R54

0

R46

0

R69

0

R62

0

R64

0

R700

R68

0

R52

1 2

3 4

5 6

7 8

9 10

11 12

13 14

J13

TSW-107-07-G-D

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15

17

19

21

23

25

16

18

20

22

24

26

J14

TSW-113-07-G-D

GND

GND

1.96kR55

DNP

GND

GND

GND

GND

GND

GND

GND

10.0kR45

DNP

13.0kR53

DNP

13.0k

R60DNP

1.96kR66

DNP

10.0kR71

DNP

10.0kR75

DNP

10.0k

R77DNP

10.0kR80

DNP

6.2kR84

DNP

1.96kR88

DNP

GND

2.49kR48

DNP

2.49kR72

DNP

2.49kR76

DNP

2.49kR82

DNP

2.49kR78

DNP

VDDIO

3V3

3V3 3V3 3V3

Pull-Up Pins:

COLLED_0CRSRX_ER

Pull-Down Pins:

RX_D0RX_D1RX_D2RX_D3RX_DV





DP83822 EVM

3.5 Connector and Bootstrap Schematic

Figure 19. Connector and Bootstrap Schematic

http://www.ti.com


Layout www.ti.com



DP83822 EVM

4 Layout

4.1 Top Overlay

Figure 20. Top Overlay

4.2 Top Layer

Figure 21. Top Layer

http://www.ti.com


www.ti.com Layout



DP83822 EVM

4.3 Signal Layer 1

Figure 22. Signal Layer 1

4.4 Signal Layer 2


http://www.ti.com


Layout www.ti.com



DP83822 EVM

4.5 Signal Layer 3


4.6 Signal Layer 4


http://www.ti.com


www.ti.com Layout



DP83822 EVM

4.7 Bottom Layer

Figure 26. Bottom Layer

4.8 Bottom Overlay

Figure 27. Bottom Overlay

http://www.ti.com


Layout www.ti.com



DP83822 EVM

4.9 Board Assembly

Figure 28. Top Board Assembly

Figure 29. Bottom Board Assembly

http://www.ti.com


www.ti.com Bill of Materials



DP83822 EVM

5 Bill of Materials

Table 4. Bill of Materials

Part Number ComponentDesignation Description Qty

C0402C120J3GACAUTO C4, C5 CAP, CERM, 12 pF, 25 V, ±5%, C0G/NP0, AEC-Q200Grade 1, 0402 2

GRM155R61C225KE11D C6, C7 CAP, CERM, 2.2 µF, 16 V, ±10%, X5R, 0402 2

GRM155R71C104KA88D

C8, C15, C22,C43, C45, C54,C56, C58, C61,

C63, C65

CAP, CERM, 0.1 µF, 16 V, ±10%, X7R, 0402 11

CGA2B3X7R1H103K050BBC9, C10, C11,C16, C23, C31,

C53, C57

CAP, CERM, 0.01 µF, 50 V, ±10%, X7R, AEC-Q200 Grade1, 0402 8

CGA6P1X7R1C226M250ACC12, C19, C29,C35, C37, C39,

C40

CAP, CERM, 22 µF, 16 V, ±20%, X7R, AEC-Q200 Grade1, 1210 7

CGA6P1X7R1E106M250ACC13, C20, C26,C27, C30, C34,C36, C38, C59

CAP, CERM, 10 µF, 25 V, ±20%, X7R, AEC-Q200 Grade1, 1210 9

C1005X7S1A105K050BCC14, C21, C42,C44, C55, C60,

C62, C64CAP, CERM, 1 µF, 10 V, ±10%, X7S, 0402 8

CGA2B2C0G1H102J050BA C17, C24, C32 CAP, CERM, 1000 pF, 50 V, ±5%, C0G/NP0, AEC-Q200Grade 1, 0402 3

CGA2B2C0G1H101J050BA C18, C25, C33 CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, AEC-Q200Grade 1, 0402 3

1812GC472KAT1A C28, C51, C52,C66, C67 CAP, CERM, 4700 pF, 2000 V, ±10%, X7R, 1812 5

CGA4J3C0G2E103J125AA C41 CAP, CERM, 0.01 µF, 250 V, ±5%, C0G/NP0, AEC-Q200Grade 1, 0805 1

CGA4J3C0G2E103J125AA C46 CAP, CERM, 0.01 µF, 250 V, ±5%, C0G/NP0, AEC-Q200Grade 1, 0805 1

CGA3E2X8R1E104K080AA C47, C48, C49,C50

CAP, CERM, 0.1 µF, 25 V, ±10%, X8R, AEC-Q200 Grade0, 0603 4

08051C472KAT2A C68, C69 CAP, CERM, 4700 pF, 100 V, ±10%, X7R, 0805 2

QTLP630C4TR D1, D2, D4, D5,D6, D7 LED, Green, SMD 6

NRVBA160T3G D3 Diode, Schottky, 60 V, 1 A, AEC-Q101, SMA 1Fiducial FID1, FID2, FID3 Fiducial mark. There is nothing to buy or mount. 3

1502-2 GND1, GND2,V+1, V+2 Terminal, Turret, TH, Double 4

U77-A1118-200T H1 SFP Single Cage 1142-0701-851 J1 Connector, End launch SMA, 50 Ω, SMT 1

TSW-103-07-T-S J2 Header, 2.54 mm, 3x1, Tin, TH 1142-0701-851 J4 Connector, End launch SMA, 50 Ω, SMT 1

0475890001 J5 Connector, Receptacle, Micro-USB Type AB, R/A, BottomMount SMT 1

TSW-106-07-G-D J6 Header, 100mil, 6x2, Gold, TH 11502-2 J7 Terminal, Turret, TH, Double 11502-2 J8 Terminal, Turret, TH, Double 11502-2 J9 Terminal, Turret, TH, Double 1

TSW-103-07-G-S J10, J11 Header, 100mil, 3x1, Gold, TH 21-406541-1 J12 RJ-45, No LED, tab up, R/A, TH 1

TSW-107-07-G-D J13 Header, 100mil, 7x2, Gold, TH 1

http://www.ti.com


Bill of Materials www.ti.com



DP83822 EVM

Table 4. Bill of Materials (continued)


TSW-113-07-G-D J14 Header, 100mil, 13x2, Gold, TH 11367073-1 J15 Receptacle, 0.8mm, 10x2, Gold, R/A, SMT 1

BLM21BD121SN1D L2 Ferrite Bead, 120 Ω at 100 MHz, 0.2 A, 0805 1IFSC0806AZER1R0M01 L3, L4 Inductor, Shielded, Ferrite, 1 µH, 1.6 A, 0.115 Ω, SMD 2

THT-14-423-10 LBL1 Thermal Transfer Printable Labels, 0.650" W x 0.200" H -10,000 per roll 1

CRCW04021K00FKED R1, R2 RES, 1.00 k, 1%, 0.063 W, 0402 2CRCW040218R0JNED R3 RES, 18, 5%, 0.063 W, 0402 1CRCW04020000Z0ED R4 RES, 0, 5%, 0.063 W, 0402 1

TNPW06032K21BEEA R5, R6, R8, R9,R10 RES, 2.21 k, 0.1%, 0.1 W, AEC-Q200 Grade 0, 0603 5

ERJ-1GE0R00C R7 RES, 0, 5%, 0.05 W, 0201 1CRCW12061M00FKEA R11, R43, R83 RES, 1.00 M, 1%, 0.25 W, 1206 3

CRCW0402470RJNED R12, R13, R17,R20, R23, R25 RES, 470, 5%, 0.063 W, 0402 6

RT0603BRD071K2L R14 RES, 1.20 k, 0.1%, 0.1 W, 0603 1ERA-3AEB242V R15, R21, R27 RES, 2.40 k, 0.1%, 0.1 W, AEC-Q200 Grade 0, 0603 3

CRCW04022K49FKEDR16, R18, R22,R24, R48, R72,R76, R78, R82

RES, 2.49 k, 1%, 0.063 W, 0402 9

CRCW06034K22FKEA R19, R26 RES, 4.22 k, 1%, 0.1 W, 0603 2

ERJ-1GE0R00C

R28, R29, R30,R31, R36, R41,R42, R44, R46,R47, R49, R50,R51, R52, R54,R56, R57, R58,R59, R61, R62,R63, R64, R65,R67, R68, R69,

R70

RES, 0, 5%, 0.05 W, 0201 28

CRCW080575R0JNEA R32, R33, R34,R35 RES, 75, 5%, 0.125 W, 0805 4

CRCW040249R9FKED R37, R38, R39,R40 RES, 49.9, 1%, 0.063 W, 0402 4

CRCW040210K0FKED R45, R71, R75,R77, R80 RES, 10.0 k, 1%, 0.063 W, 0402 5

CRCW040213K0FKED R53, R60 RES, 13.0 k, 1%, 0.063 W, 0402 2CRCW04021K96FKED R55, R66, R88 RES, 1.96 k, 1%, 0.063 W, 0402 3

RC0603JR-0710KL R73 RES, 10 k, 5%, 0.1 W, 0603 1RC0402JR-070RL R74 RES, 0, 5%, 0.063 W, 0402 1

CRCW040282R0JNED R79, R85, R86,R87 RES, 82, 5%, 0.063 W, 0402 4

CRCW0402130RJNED R81, R89, R90,R91 RES, 130, 5%, 0.063 W, 0402 4

CRCW04026K20JNED R84 RES, 6.2 k, 5%, 0.063 W, 0402 1ERJ-1GE0R00C R92 RES, 0, 5%, 0.05 W, 0201 1

CRCW02011K00FKED R93, R94, R95,R96 RES, 1.00 k, 1%, 0.05 W, 0201 4

CRCW04024K87FKED Rs1 RES, 4.87 k, 1%, 0.063 W, 0402 1KSR221GLFS S1 Switch, Normally open, 2.3N force, 200k operations, SMD 1

ACM9070-701-2PL T1 Common Mode Filter for Power Line 1HX1188FNLT T2 Transformer, 350 uH, SMT 1

http://www.ti.com


www.ti.com Bill of Materials



DP83822 EVM

Table 4. Bill of Materials (continued)


CDCE925PWR U1PROGRAMMABLE 2-PLL VCXO CLOCK SYNTHESIZER

WITH 1.8-V, 2.5-V and 3.3-V LVCMOS OUTPUTS,PW0016A

1

DP83822RHBR U2 10/100 Ethernet PHY, RHB0032B 1

TL1963AQKTTRQ1 U3, U4, U5Single Output Fast Transient Response LDO, 1.5 A,

Adjustable 1.21 to 20 V Output, 2.1 to 20 V Input, 5-pinDDPAK (KTT), -40 to 125 degC, Green (RoHS & no Sb/Br)

3

TPD4E05U06QDQARQ1 U6, U71, 4, 6 CHANNEL PROTECTION SOLUTION FOR

SUPER-SPEED (UP TO 6 GBPS) INTERFACE,DQA0010A

2

ABM8AIG-25.000MHZ-12-2Z-T3 Y1 Crystal, 25MHz, 12pF, SMD 1

http://www.ti.com


IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of salesupplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI components or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altereddocumentation. Information of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or servicevoids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards whichanticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might causeharm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the useof any TI components in safety-critical applications.In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI componentswhich have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products ApplicationsAudio www.ti.com/audio Automotive and Transportation www.ti.com/automotiveAmplifiers amplifier.ti.com Communications and Telecom www.ti.com/communicationsData Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computersDLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-appsDSP dsp.ti.com Energy and Lighting www.ti.com/energyClocks and Timers www.ti.com/clocks Industrial www.ti.com/industrialInterface interface.ti.com Medical www.ti.com/medicalLogic logic.ti.com Security www.ti.com/securityPower Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defenseMicrocontrollers microcontroller.ti.com Video and Imaging www.ti.com/videoRFID www.ti-rfid.comOMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.comWireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2016, Texas Instruments Incorporated

http://www.ti.com/audio

http://www.ti.com/automotive

http://amplifier.ti.com

http://www.ti.com/communications

http://dataconverter.ti.com

http://www.ti.com/computers

http://www.dlp.com

http://www.ti.com/consumer-apps

http://dsp.ti.com

http://www.ti.com/energy

http://www.ti.com/clocks

http://www.ti.com/industrial

http://interface.ti.com

http://www.ti.com/medical

http://logic.ti.com

http://www.ti.com/security

http://power.ti.com

http://www.ti.com/space-avionics-defense

http://microcontroller.ti.com

http://www.ti.com/video

http://www.ti-rfid.com

http://www.ti.com/omap

http://e2e.ti.com

http://www.ti.com/wirelessconnectivity

User's Guide - TI.com of this User’s Guide for resistor locations. Table 2. Bootstrap Resistor Designation and Suggested Bootstrap Resistor Values Pin Name Pin Number Strap

Documents