user’s guide - AGATA Experimentagata.pd.infn.it/LLP_Carrier/New_ATCA_Carrier_web/Appnotes_And... · 3 Personality Module Mechanicals The dimensions of the Personality Module, and
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5.1.7 Ethernet MAC .................................................................................................................................... 15
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1 Overview The Full Mesh Line Card is intended to serve as a development platform for PICMG 3.x line cards supporting port rates to 10 Gbps. It includes a Virtex-II Pro based FPGA based fabric interface that also includes all PICMG 3.0 defined card and shelf management functionality. Management firmware executes on one of the Virtex-II Pro’s PowerPC processors running an embedded Linux operating system.
The card also includes headers to interface to a user defined Personality Module. This module is used to implement application specific line card processing and external interfaces. IO access for this module can be through the front panel, or Rear Transition Modules (RTMs). The Personality Module also has full access to the PICMG 3.0 Update Channel Interface.
The card implements a 200W power supply and all PICMG 3.0 defined fusing and protection circuitry.
Figure 1: ATCA 4x4 Full-Mesh Line Card Block Diagram
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Table 1 describes the function of each jumper along with the factory settings.
Table 1: Jumper Settings
Reference
Designation Settings Description
1 to 2* Selects the Parallel IV cable header (P115) for JTAG debug. JMPR1 open Selects the Trace header (P109) for JTAG debug. 1 to 2* Powers PM I/O pins with 2.5V for applications such as RapidIO or SPI-4 JMPR2 2 to 3 Powers PM I/O pins with 3.3V for applications such as SPI-3 1 to 2 Powers VTRX on the top MGT bank with 2.5V. JMPR3 2 to 3* Powers VTRX on the top MGT bank with 1.8V. 1 to 2 Powers VTRX on the bottom MGT bank with 2.5V. JMPR4 2 to 3* Powers VTRX on the bottom MGT bank with 1.8V. 1 to 2* Enables the MGT power JMPR5 and 6 open Provides path for MGT current measurement 1 to 2* Enables the 12V supply to the Personality Module (PM) connector. JMPR7 and 8 open Provides path for PM supply current measurement 1 to 2* Enables the 12V supply to the Rear Transition Module (RTM) connector. JMPR9 and 10 open Provides path for RTM supply current measurement 1 to 2* Enables the 2.5V supply JMPR11 and
12 open Provides path for 2.5V supply current measurement 1 to 2* Enables the 1.5V supply JMPR13 and
14 open Provides path for 1.5V supply current measurement 1 to 2 Selects 125MHz MGT reference clock frequency JMPR15 2 to 3 Selects 156.25MHz MGT reference clock frequency
JMPR16 1 to 2* Loops back TDO to TDI when PM is not installed. 1 to 2* Routes the “collision” LED signal from the 10/100 PHY to the front panel
RJ45 JMPR17 2 to 3 Routes the “collision” LED signal from the 10/100 PHY to the Personality Module
1 to 2* Routes the “link” LED signal from the 10/100 PHY to the front panel RJ45 JMPR18 2 to 3 Routes the “link” LED signal from the 10/100 PHY to the Personality Module
JMPR19 See Figure 3
Routes 10/100 Ethernet port to one of the following interfaces: • ATCA Base Interface • Personality Module header J4 • Front panel RJ-45
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5 Fabric Interface FPGA The Fabric Interface FPGA implements not only the data plane functions needed to transfer data across the distributed fabric, but also all management functions defined in the PICMG 3.0 specification. When placed in slots one or two the card is capable of acting as a Shelf Manager. The following sections discuss the control plane and data plane functionality of the FPGA.
5.1 Fabric Interface FPGA Control Plane Section The control plane section of the Fabric Interface FPGA implements management functions for the card. All of these functions are implemented as firmware running on an embedded Linux operating system. The functions that are provided include:
• IPMI agent
• Shelf Manager
• Hardware and software update via ShMC interface
Figure 5 shows a block diagram of the Control Plane section of the Fabric Interface FPGA.
Figure 5: Fabric Interface FPGA Control Plane Section Block Diagram
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5.1.1 405 Processor Cores The Virtex-II Pro FPGA includes two 400 Mhz PowerPC 405 processors. One processor is used to implement management functions as shown in Figure 5. It interfaces to the rest of the management subsystem by way of a 64-bit CoreConnect Processor Local Bus (PLB), and a 32-bit On-Chip Peripheral Bus (OPB). The second PowerPC processor is available for applications specific functions.
5.1.2 PLB Arbiter The PLB Arbiter implements the CoreConnect Processor Local Bus (PLB). It consists of arbitration logic, a watchdog timer, and separate data path logic for address, write data, and read data.
5.1.3 DDR SDRAM Memory Controller The Double Data Rate (DDR) SDRAM memory controller manages 128 MB of DRAM for the PowerPC processor, and is used as the main code and data store for the Linux operating system. The memory is implemented using discrete devices soldered to the board.
5.1.4 BlockRAM (BRAM) Memory Controller The BRAM memory controller manages 32 KB of on-chip SRAM for the PowerPC processor. This memory is used as temporary storage during the boot process.
5.1.5 PLB2OPB Bridge The PLB2OPB Bridge translates PLB transactions into OPB transactions. These transactions are made up of read and write cycles to IO peripherals.
5.1.6 OPB Arbiter The OPB Arbiter implements the On-Chip Peripheral Bus (OPB). It consists of arbitration logic, a watchdog timer, and separate data path logic for address, write data, and read data.
5.1.7 Ethernet MAC The 10/100 Ethernet MAC is used to implement the Shelf Management Controller (ShMC) interface. It interacts with the operating system through a standard network driver, and provides an interface for IP based management traffic. This port can also used for debugging and firmware/hardware updates.
5.1.8 16450 UART The UART is used to implement the RTM serial port interface. It interacts with the operating system through a standard terminal driver. This port can also used for debugging and firmware/hardware updates.
5.1.9 System ACE MPU Interface The System ACE MPU Interface provides a mechanism for the 405 processor to access the MicroDrive in the CompactFlash socket. It interacts with the operating system through a standard block device driver, and enables the use of the drive as a file system under Linux.
5.1.10 I2C Interface Controllers The FPGA includes three I2C interface controllers. Two are used to implement the IPMB interfaces, and the third is used for system monitoring functions.
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5.1.11 General Purpose IO Controller The General Purpose IO (GPIO) controller gives the processor access to IO pins on the FPGA so that they can be read and written under program control. These signals are used to implement the Hardware Address (HA) interface, and the Front Panel Status Interface.
5.1.12 Interrupt Controllers The Interrupt Controller blocks manage the interrupt signals fed to the processor by providing masking, and prioritization capabilities. There are two controllers, one for standard interrupts, and one for critical interrupts. The controller manages interrupts from the Ethernet MAC, the I2C Controllers, and the 16450 UART.
5.1.13 DCR Bridge The DCR Bridge provides a means for the processor to access control registers that are mapped to the CoreConnect DCR bus. This includes registers in the PLB Arbiter, The OPB2PLB and PLB2OPB bridges, and the Interrupt Controllers.
5.2 Fabric Interface FPGA Data Plane Section The Data Plane Section implements a complete, fifteen channel, distributed switch fabric interface. The configuration shipped with the card implements a PICMG 3.1 Ethernet transport, but it can be customized to support other PICMG 3.x transports. Figure 6 shows a block diagram of the Data Plane section of the Fabric Interface FPGA
Figure 6: Fabric Interface FPGA Data Plane Section Block Diagram
5.2.1 Aurora Interface Logic The Aurora Interface is used to transfer packets between the user-defined logic on the Prototyping Module and the PICMG 3.x fabric. The Aurora Interface uses the Fabric Interface MGT signals for connectivity.
Other interfaces can be substituted for this one if desired. One example of an alternative interface is POS-PHY Level 3. In this case the Fabric Interface GPIO signals would be used for connectivity.
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5.2.2 Channel Interfaces & FIFOs The Channel Interfaces implement physical and link layer functions for each channel. In the case of a PICMG 3.1 Ethernet transport, this block consists of a Gigabit Ethernet MAC with a 1000BASE-BX physical layer interface.
5.2.3 Address Mapping Logic The address mapping logic maps destination address information contained in packets entering the switch interface through the Aurora Interface into destination port numbers. This information is then used to direct the packet into the transmit FIFO for the correct channel interface. In the PICMG 3.1 configuration that is shipped with the card this means mapping a 48-bit Ethernet destination address.
6 PICMG Synchronization Clock Interface The Full Mesh Line Card supports a subset of the PICMG 3.0 Synchronization Clock Interface functions. The Synchronization Clock Interface logic is capable of selecting and routing the 19.44 MHz system clock to or from the CLK2A and CLK2B clock busses. Figure 7 shows a block diagram of this logic. The PICMG_REFCLK signals are available to the Personality Module through Fabric Interface GPIO Header 2.
Figure 7: Synchronization Clock Interface Logic
7 Power Supply Subsystem The Power Supply Subsystem consists of fusing, filtering, and protection circuitry as well as DC to DC converters designed to support the power requirements of both the Fabric Interface FPGA and application specific circuitry implemented on the Personality Module and Rear Transition Module. Figure 8 gives an overview of this subsystem.
7.1 VCC3V3_BOOT Power Bus The power supply for the baseboard circuitry consists of the Boot DC to DC converter, and several smaller voltage converters that supply the various levels needed by the base board circuitry.
7.2 VCC12V_MAIN Power Bus Power for application specific circuitry consists of 151 watts of 12V brought out to the Personality Module headers, and RTM connector. Conversion to the voltages required by the application is performed on these cards. During card initialization, the VCC12V_MAIN Power Bus is disabled until the control plane subsystem negotiates the power requirements of the board with the shelf management subsystem.
It is the responsibility of developers of Personality Modules and RTM cards to ensure the following: