US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida1 Muon Track-Finder Trigger Darin Acosta University of Florida June, 2002.

US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida 1

Muon Track-Finder TriggerMuon Track-Finder TriggerMuon Track-Finder TriggerMuon Track-Finder Trigger

Darin Acosta

University of Florida

June, 2002


Muon Track-FindingMuon Track-FindingMuon Track-FindingMuon Track-Finding

• Link trigger primitives into 3D tracks

• Measure pT, , and in non-uniform fringe field

• Send highest quality candidates to Global L1• Partitioned into 60° sectors that align with DT chambers


Strip FE cards

Wire FE cards

Muon Port Card(Rice)

MPC

Sector Receiver/ Processor(U. Florida)

OPTICAL

SR/SP SP

CSC Muon Sorter(Rice)

Global Trigger

DTRPC

FE

FE

Global L1

2 / chamber

3 / port card

3 / sector

4

4

4 4

LCT

Trigger Motherboard

(UCLA)

Wire LCT card

In counting

house

TMB

LCT

RPC Interface Module

RIM

On-Chamber Trigger Primitives

3-D Track-Finding and Measurement

Combination of all 3 Muon Systems

CSC Muon Trigger SchemeCSC Muon Trigger SchemeCSC Muon Trigger SchemeCSC Muon Trigger SchemeEMU Trigger


Scope of CSC Track-FinderScope of CSC Track-FinderScope of CSC Track-FinderScope of CSC Track-Finder

Prototype version tested Fall 2000:

New version (SR/SP combined)Board # units Responsibility

MPC 48 Rice

Sector Receiver

24 UCLA

Sector Processor

12 Florida

Clock and Control Board

6 Rice

CSC Muon Sorter

1 Rice

Crates, Backplanes

6 Florida

DDU readout

1 Florida/Ohio State

Board # units Responsibility

MPC 48 Rice

SR/SP 12 Florida


1 Rice

CSC Muon Sorter

1 Rice

Crates, Backplanes

1 Florida

DDU readout

1 Florida/Ohio State

Baselined with 24 crates, reduced to 6 in 1998, now 1:


Prototype Track Finder TestsPrototype Track Finder TestsPrototype Track Finder TestsPrototype Track Finder TestsFocus during FY 2000 was on producing and

testing prototypes of all Track-Finder components (except the CSC Muon Sorter)

• Sector Processor: UFlorida• Sector Receiver: UCLA• Muon Port Card: Rice• Clock and Control Board: Rice• Channel-Link backplane: UFlorida

Integration tests of the complete system yielded 100% agreement between hardware and software for random and simulated physics events

Port CardF

IFO

FIF

O Sector ReceiverF

IFO

FIF

O Sector Processor F

IFO

DAQ System (VME, Bit3 Controller, PC running Windows NT)

100m Optical Links

Custom Back plane

FIF

OResults included in Trigger TDR


Sector Receiver PrototypeSector Receiver PrototypeSector Receiver PrototypeSector Receiver Prototype

Optical Receivers and

HP Glinks

SRAM LUTs

Front FPGAs Back FPGAs

UCLA

Receives and Receives and formats track formats track segment datasegment data


Extrapolation Units XCV400BG560

Final Selection Unit XCV150BG352

Bunch Crossing Analyzer

XCV50BG256

Track Assemblers 256k x 16 SRAM

Assignment Units XCV50BG256 &

2M x 8 SRAM

Sector Processor PrototypeSector Processor PrototypeSector Processor PrototypeSector Processor Prototype

12 layers

10K vias

17 FPGAs

12 SRAMs

25 buffers

Florida

Links track Links track segments into segments into

3D tracks, 3D tracks, selects best selects best three tracks, three tracks,

measures measures momentummomentum


11stst Track-Finder Crate Tests Track-Finder Crate Tests11stst Track-Finder Crate Tests Track-Finder Crate TestsSector ProcessorSector Processor(Florida)(Florida)

Sector ReceiverSector Receiver(UCLA)(UCLA)

Clock Control Clock Control Board (Rice)Board (Rice)

Bit3 Bit3 VME VME InterfaceInterface

Custom Custom ChannelLinkChannelLinkBackplaneBackplane(Florida)(Florida)

Muon Port CardMuon Port Card(Rice)(Rice)

100m optical 100m optical fibersfibers

Very Very successful, successful, but overall but overall

CSC latency CSC latency was too high --was too high --New design in New design in 2001 improves 2001 improves

latencylatencyPrototype crate for

original six crate design


Single Track-Finder Crate Design with 1.6 Gbit/s optical links

• Reduces processing time from 525 ns (old design) to 175 ns• Total Latency ~ 15 Bx (from input of SR/SP card to output of MS card)

• Crate Power Consumption ~ 1000 W • 16 Optical connections per SR/SP card• Custom Backplane for SR/SP CCB and MS connection

New Track-Finder Crate DesignNew Track-Finder Crate DesignNew Track-Finder Crate DesignNew Track-Finder Crate Design

SR /

SP

SR /

SP

SR /

SP

SR /

SP

SR /

SP

SR /

SP

SR /

SP

SR /

SP

SR /

SP

SR /

SP

SR /

SP

SR /

SP

CC

B

BIT

3 C

ontr

olle

r

SR/SP Card (3 Sector Receivers +

Sector Processor) (60 sector)


Muon Sorter

ToGlobal Trigger

From Trigger Timing & Control

From MPC (chamber 4)



From MPC (chamber 1B)

From MPC (chamber 1A)

To DAQ

MS


CSC Track Finder BackplaneCSC Track Finder BackplaneCSC Track Finder BackplaneCSC Track Finder Backplane

Design Approved Design Approved ––

Technology Technology same as EMU same as EMU

peripheral cratesperipheral crates

Standard VME 64x J1/P1 backplane

Standard VME J2/P2 backplane

Muon sorter

Clock and control

SR

SP

6

SR

SP

5

SR

SP

4

SR

SP

3

SR

SP

2

SR

SP

1

SR

SP

12

SR

SP

11

SR

SP

10

SR

SP

9

SR

SP

8

SR

SP

7

Custom GTLP 6U backplane

Rice

Florida

These SRSP feedthru connectors are for DT information exchange via transition board

GTLP backplane avoids latency penalty of previous Channel-Link backplane (~3BX)


SR/SP 2002 Board LayoutSR/SP 2002 Board LayoutSR/SP 2002 Board LayoutSR/SP 2002 Board Layout

EEPROMPhi Local LUT

Eta Global LUTPhi Global LUT

DC-DC Converter

Indicators

DDU FPGA

TLK2501 Transceiver

Optical Transceiver

VME/CCB FPGA

Main FPGA

PT LUT

EEPROM

Front FPGA

EEPROM

Mezzanine Card

From CCB

To MSTRANSITION BOARD WITH LVDS TRANSCEIVERS

TO/ FROM BARREL


SR/SP 2002 Design StatusSR/SP 2002 Design StatusSR/SP 2002 Design StatusSR/SP 2002 Design Status

Schematics nearly complete:• Sector Receiver Front FPGAs (5 total)

• Choice: XC2V1000-FF896C with 432 user I/Os• Sector Processor Main FPGA

• Choice: XC2V4000-FF1152C with 824 user I/Os• Placed on mezzanine card (design started)• Firmware written in “Verilog++”, validated by simulation

• VME & control interface FPGA• Choice: XC2V250-FG456C with 200 user I/Os

• DAQ Interface FPGA• Choice: XC2V250-FG256C with 172 user I/Os

• SRAM:• 51 SRAM chips (>64MB) for Look-up functionality

Layout to commence soon• Board will be dense! (Merger of 4 boards, but I/O ~same)


New Design Reduces LatencyNew Design Reduces LatencyNew Design Reduces LatencyNew Design Reduces Latency

Optical receivers

Front FPGAs

Lookup tables

Channel link transmitters

Channel link receivers

Bunch crossing analyzer (not implemented)

Extrapolation units

9 Track Assembler units (memory)

Final selection unit 3 best out of 9

Pt precalculation for best 3 muons

Pt assignment (memory)

Sec

tor

Rec

eive

r st

.1

Sec

tor

Rec

eive

r st

.2,3

Sec

tor

Rec

eive

r st

.4

1

4

1

2

3

2

3

3

2

Optical receivers

Front FPGAs

Lookup tables

Bunch crossing analyzer (not implemented)

Extrapolation units

9 Track Assembler units

Final selection unit 3 best out

of 9

Pt precalculation for 9 muons

Pt assignment (memory)

1

0

1

1

1

1

1

1

Output multiplexor

Sec

tor

Pro

cess

or

SR/SP board

Sector Processor FPGA

First prototype dataflow Pre-production prototype data flow

Lat

ency

Lat

ency

Total: 21 BX Total: 7 BX To Muon SorterTo Muon Sorter

From Muon Port CardsFrom Muon Port Cards

To DT


VME J1 CONNECTOR

CUSTOM BACKPLANE

9U * 400 MM BOARD

CONNECTORS TO GMT

LVDS DRIVERS

CCB INTERFACE

SORTERLOGIC

INPUT AND

OUTPUTFIFO

VMEINTERFACE

SP1

SP2

SP3

SP4

SP5

SP6

SP7

SP8

SP9

SP10

SP11

SP12

CABLES TOGLOBAL MUONTRIGGER CRATE

GTLP TRANSCEIVERS

New Muon Sorter Design (Rice)New Muon Sorter Design (Rice)New Muon Sorter Design (Rice)New Muon Sorter Design (Rice)

Reduced to single board -- reduces latency, cost

New:Will use commonXilinx mezzanine cardwith Sector Processor


PIPELINE MUON 1 LUTs

PIPELINE MUON 2

DFF

DFF

SORTER “4 OUT OF 36”

MUON 1

CCB

SP 1

SP 2

DFF

FIFO

FIFO

VME

VME

MUX

MUX

MUX

VME

SP 12

VME

MUON 2

VME

FIFO

..

.

DFF

FIFO

VMEMUX PIPELINE

MUON 3

...

VMEDFF

FIFO

DFF

VME

FIFO

VMEDFF

FIFO

MUON 3

MUON 4

LUTs

VME

LUTs

LUTs

VME

VME

144

CCBINTERFACE

Sorter FPGASorter FPGASorter FPGASorter FPGA


CCB for Track Finder CrateCCB for Track Finder CrateCCB for Track Finder CrateCCB for Track Finder Crate• Same CCB for peripheral (EMU) and Track Finder crates

• 20 sets (main 9U board + Altera-based mezzanine card) have been fabricated so far

• 15 boards are assembled and tested

• 2 boards will be used for Track Finder tests (UF&Rice)

TTCrx mezzanine board


PersonnelPersonnelPersonnelPersonnel

• Professors

• Darin Acosta (Florida), Robert Cousins (UCLA), Paul Padley (Rice)

• Postdocs

• Song Ming Wang (Florida), Slava Valouev (UCLA)

• Students

• Bobby Scurlock (Florida), Jason Mumford (UCLA)

• Engineers

• Alex Madorsky (Florida), Mike Matveev (Rice), Ted Nussbaum (Rice)

• Collaborating engineers (all PNPI)

• Victor Golovtsov, Lev Uvarov


ConclusionsConclusionsConclusionsConclusions

• First Track Finder system prototyped successfully in Fall 2000

• Exact match to CMS OO simulation package

• Second generation pre-production prototype is well underway with significant improvements

• Present and future activities• 2001: R&D on optical links, FPGA logic, memory look-ups, backplane

technology, and DAQ readout • 2002: build the 2nd generation prototype• 2003: test with multiple CSC chambers, cosmic rays and/or structured

beam, tweaks for final design (if necessary)• 2004: full production• 2005: installation

• No trouble expected: all-digital system with off-the-shelf components, well-defined internal and external interfaces, and a stable and capable engineering team

US CMS DOE/NSF Review: June 2002, Darin Acosta, University of Florida1 Muon Track-Finder Trigger Darin Acosta University of Florida June, 2002.

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