July 2008 Rev 1 1/66 UM0527 User manual UPS evaluation board Introduction The UPS evaluation board provides a complete solution addressing the low/medium range UPS segment with 700 V A output power capab ility . The evaluation board, from a hardware and firmware point of view , is ready to support the development of a complete solution. Thanks to the PC software it's possible to monitor all the relevant system parameters using the RS232 interface or the USB. The evaluation board is available for the 120 Vac market and 230 Vac market. The UPS evaluation board is built in offline topology with AVR regulation of the mains boost and buck. The inverter module contains the push-pull DC/DC converter and the DC/AC output full-bridge generating quasi-sine waveform. www.st.com
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July 2008 Rev 1 1/66
UM0527User manual
UPS evaluation board
Introduction
The UPS evaluation board provides a complete solution addressing the low/medium rangeUPS segment with 700 VA output power capability. The evaluation board, from a hardwareand firmware point of view, is ready to support the development of a complete solution.Thanks to the PC software it's possible to monitor all the relevant system parameters usingthe RS232 interface or the USB. The evaluation board is available for the 120 Vac marketand 230 Vac market.
The UPS evaluation board is built in offline topology with AVR regulation of the mains boostand buck. The inverter module contains the push-pull DC/DC converter and the DC/ACoutput full-bridge generating quasi-sine waveform.
The UPS evaluation board is built in offline topology with AVR regulation of the mains boostand buck. The inverter module contains the push-pull DC/DC converter and the DC/ACoutput full-bridge generating quasi-sine waveform. The battery charger module is connectedat the output of the UPS and it also has the function of taking over the reactive power whichis present on the inverter during battery operation with reactive - resistive load.
The microcontroller controls all UPS functions. It monitors the mains parameters in order toensure the proper level of the output voltage. The microcontroller measurement parametersare input/output mains voltage and phase, output inverter voltage, battery voltage, outputcurrent and output power. The UPS has a built-in RS232, joint signals and USB interfaces
(USB for RS232 converter).
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The DC/AC inverter was built in full-bridge topology. The output waveform is a quasi-sinewaveform. The inverter is controlled by the microcontroller across two PWM drivers whichswitch four power transistors. The high-side driver parts are supplied with the bootstrapcircuitry D1, C1 and D2, C2. The diodes D1 and D2 are high-voltage fast-recovery diodes.
Switching off all transistors is achieved with driver internal logic if both INV_A and INV_Bsignals are set high or low. There is no any additional overcurrent protection for bridgetransistors. Drivers are powered from the main UPS supply unit.
two pole separation relays DPNO (RL1) (with 2 mm gap)
two relays DPDT (RL2, RL3)
two pole switching battery/mains relays DPDT (RL4)
two pole output on/off relays DPNO (RL5)
All relay coils are powered from the battery and charger voltage. The current transformer isused for monitoring UPS output current and power. The additional AVR boost/buckautotransformer has two sections: winding and output power 60VA. Relay coils arecontrolled by the microcontroller signals through an additional driver.
1.1.7 RFI/EMI filter
Figure 5. RFI/EMI filter
An additional EMI/RFI filter contains one X-type capacitor and a pair of Y-type capacitors.
L
N
C1204,7nF
AC_IN1
AC_IN2
PE R90200k
M A I N S
RFI/EMI FILTER
RV1
JVR-20N471K
R88200k
R89200k
JVR-20N271K
AC_IN1
AC_IN2
1
J9
6.3x0.8
1
J10
6.3x0.8
1
J11
6.3x0.8
C1194,7nF C108
470nF
BROWN
BLUE
YELLOW/GREEN
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The battery charger is used as a battery charger for the mains mode or as a reactive powerrecirculation circuit for the inverter mode. For both modes the charger output power isaccepted by the battery. The charger power converter is built in quasi-resonant flybackmode based on the controller L6565 with external power switch Q1 and output diode D1.
The PWM controller is powered from the main UPS supply module and from the auxiliarywinding on the flyback transformer. The transformer is designed with the ETD29 core. TheCHOFF signal is used to switch (Q2 and Q3 STP80PF55) charging modes by themicrocontroller. An additional output voltage loop limits open output charger voltage. Thecharger module also contains a battery overvoltage protection circuit with SCR TYN608 andvoltage reference TL431.
Table 3. Battery charger specifications
AC/DC converter 120 Vac version 230 Vac version
Max output voltage 29 Vdc ± 5%
Max output power 50 W
Efficiency >80%
Minimal switching frequency 100kHz ± 10%
Controller U1 L6565
Power switch Q11 STP5NK90Z
Transformer core ETD29
Rectifier diode D1 STPS8H100
Clamp diode D3 STTA106
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1.1.9 Control unit
Figure 7. Control unit
G N D
G N D
C 8 8 2
2 p
F
C 8 9
2 2 p
F Y 1 1 6 M H z
N C 1
O N / O F F
B U Z Z E R
G N D V
C C P U
R X
T X
R S T !
P H A S
E
I N V _ A ! I N V _ B !
B U T T
O N
A C L
A C F !
P W R
_ L
E V
I N P
_ L E
V
A K K
_ L
E V
T X
R X
L 6
4 . 7
u H
L 5
4 . 7
u H
A C I
V C C P U
R 1 1 0
4 . 7
k
G N D
C 1 7
1 0 0 n
F
G N D
V D D
3
R E S
2
V S S 1
U 8
S T M 8 0 9 L
L 4
4 . 7
u H
L 3
4 . 7
u H
G N D
V C C P U
R S T !
R E S E T !
I C C_ C
L K
A C H
V A R E F
V S S A
O U T
_ R E L
R 9 1
1 0 k
R S T !
I C C
_ S E L
G N D
I C C_ D
A T A
I C P p r o g r a m m
i n g C
- F L A S H
1
1
2
2
B 1
B P T
- 1 4
R 1 2 0
2 . 2
k
V C C
A C I
R 1 1 3
3 . 3
k
R 1 1 4
3 . 3 k
C O M
9
1 B
1
1 C
1 6
2 B
2
2 C
1 5
3 B
3
3 C
1 4
4 B
4
4 C
1 3
5 B
5
5 C
1 2
6 B
6
6 C
1 1
7 B
7
7 C
1 0
8
E U 9
U L N 2 0 0 3 D
A C F !
I N V
_ A !
I N V
_ B !
O U T_ R
E L !
I N V
_ A
I N V
_ B
G N D
O U T
_ R E L
A C L !
A C L
A C H
V C C
A C H !
O U T
_ L E V
R 1 1 8
2 . 2
k
R 1 1 9
2 . 2
k
V C C V C C
I C C
_ D A T A
I C C
_ C L K
U P S_ O F F !
L E D R
L E D G
B A T
_ L O W
C H O F F
V C C
1 3 5 7
2 4 6 8
9
1 0
J 2 I D C 1 0
G N D
V C C
V C C
D 9
B A S 1 6
B U T T O N
Y A
R A
G A
R 1 0 9 3 3 0 R
R 1 0
7
3 3 0 R
S W
_ O N P
R 9 2
1 0 k
V C C
R 1 1 1
1 0 0 R
R 1 0 4
3 3 0 R
R 1 0 6
3 3 0 R
R 1 0 8
3 3 0 R
L E D R
L E D G
R 1 0 5
3 3 0 R
L E D Y
O S C 1 O S C 2
O S C 1
O S C 2
I C C _ S E L
V A R E F 1 3
V S S A 1 4
M C O / A I N 8 / P F 0 1 5
B E E P / P F 1 ( H S ) 1 6
O C M P 1 _ A / A I N 1 0 / P F 4 1 8
I C A P 1 _ A / P F 6 ( H S ) 1 9
E X T C L K _ A / P F 7 ( H S ) 2 0
A I N 1 2 / O C M P 2
_ B / P C 0
2 3
A I N 1 3 / O C M P 1
_ B / P C 1
2 4
I C A P 2
_ B / P C 2
2 5
I C A P 1
_ B / P C 3
2 6
I C C D A T A / M I S O / P C 4
2 7
A I N 1 4 / M O S I / P C 5
2 8
I C C C L K / S C K / P C 6
2 9
A I N 1 5 / S S / P C 7
3 0
P A 3 ( H S )
3 1
P A 4 ( H S ) 3 4
P A 6 ( H S ) 3 6
P A 7 ( H S ) 3 7
V p p / I C C S E L 3 8
R E S E T 3 9
V s s _ 2 4 0
O S C 2 4 1
O S C 1 4 2
V d d _ 2 4 3
P E 0 / T D O 4 4
P E 1 / R D I
1
P B 0
2
P B 3
5
P B 4 ( H S )
6
P D 0 / A I N 0
7
P D 1 / A I N 1
8
P B 1
3
P B 2
4
P D 2 / A I N 2
9
P D 3 / A I N 3
1 0
P D 4 / A I N 4
1 1
P D 5 / A I N 5 1 2
P F 2 ( H S ) 1 7
V d d _ 0 2 1
V s s _ 0 2 2
V d d
_ 1
3 2
V s s_
1
3 3
P A 5 ( H S ) 3 5
U 2 9
S T 7 2 F 3 2 4 B J 6 T 6
L E D Y
V D C D C
V C C P
U
G N D
G N D V C C P U
V C C P U
G N D
V A R E F V S S A
U S B_ I N !
S H D
T X D
R X D
I N V
_ A
I N V
_ B
A C L !
A C H !
A C F
O U T
_ R E L !
S W
_ O N P
B A T
_ L O W
U P S
_ O F F !
P H A S E
P W R
_ L E V
A K K
_ L E V
O U T
_ L E V
I N P
_ L E V
V D C D C
C H O F F
U S B
_ I N !
B A T
_ L O
W
U P S
_ O F F !
P H A S E
P W R
_ L E
V
A K K
_ L E
V
O U T
_ L E
V
I N P
_ L E V
V D C D C
C H O F F
U S B
_ I N !
S H D
S H D
1 3 5 7
2 4 6 8
9
1 0
J 1 I D C 1 0
G N D
V C C
R 3 8
1 k
R 3 7 1 k
S
1
Q
2
W
3
V S S
4
V C C
8
H O L D
7
C
6
D
5
U 1 0
M 9 5 0 2 0 W M N 6 P
M O S I
M O S I
I C C
_ C L K
S C K
I C C
_ D A T A
G N D
M I S O
V C C P U
V C C P U
R 3 9
4 . 7
k
R E S E T !
H O L D !
C S !
A C F 1 !
R 9 3
1 0 k
N C 1
G N D
A C I !
A C I !
B U Z Z E R
G N D
G N D
C S ! P
H A S E
I N V
_ B !
I N V
_ A !
U P S
_ O F F !
A K K
_ L E V
G N D
C 4 8
1 0 0 n F
C 3 7
1 n F
C 3 8
1 n
F
G N D
O N / O F F
R S T !
U S B
_ I N !
I C C_ C
L K
I C C_ S
E L
I C C_ D
A T A
B U T T O N
R X
T X
M O S I
G N D
G N D
G N D
G N D
G N D
G N D C
7 0
1 0 n F
C 7 1
1 0 n
F
C 7 3
1 n F
C 7 4
1 0 n F
C 7 6
1 0 n
F
C 7 7
1 0 n F
G N D
G N D
G N D
G N D
C 5 1
1 0 0 p F
C 5 2
1 0 0 p F
C 5 3
1 0 0 p F
C 5 4
1 0 0 p F
C 5 5
1 0 0 p F
C 5 6
1 0 0 p F G N D
G N D
G N D
V C C P U
C 1 6
1 0 0 n
F
O N / O F F
1 2 0 V a c M o d e l
2 3 0 V a c M o d e l
G N D
T X D
R X D
V C C P U
V C C
G N D
G N D
V C C
V C C P U
Q 1 5
M M B T A 4 2
R 8 6
4 . 7
k
R 8 7
1 0 k
G N D
A C F !
A C F !
A C F 1 !
A C F 1 !
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The control unit contains the main microcontroller ST72F324J6T6 - in the TQFP 44 10x10package with an ICP connector for programming, a reset STM809, a buffer ULN2003A fordriving signals and an external EEPROM with SPI interface. Analog signals are measuredwith an internal 10-bit A/D converter. Digital inputs / outputs are used to control internal and
external UPS signals. A thermistor is used to monitor internal UPS temperature.
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Referring to Figure 10 , the measurements are defined as follows:
a) Output current. Input voltage measurement unit is built as a differential amplifierwith a 2.5 V offset (LM324). The output signal from the amplifier is connected tothe A/D converter in the microcontroller.
b) Battery voltage. The input voltage phase unit works as a comparator (LM324) andcontains information about the sign of the input voltage waveform.
c) Inverter output voltage. Output current unit is built as a differential amplifier with2.5 V offset (LM324). The output signal from the amplifier is connected to the A/Dconverter in the microcontroller.
d) Input voltage. The inverter output voltage is monitored through the voltage dividerand connected to the microcontroller A/D converter input.
e) Input voltage phase. The battery voltage measurement uses a resistive voltagedivider and the next A/D converter input of the microcontroller.
1.1.13 Battery overcurrent protection
Figure 11. Battery overcurrent protection
The battery overcurrent protection is given by a fuse.
1.1.14 Mains protection
The mains is protected by an automatic fuse mounted in an enclosure. If tr ipping occurs, thefuse can be reset by the UPS user.
1.1.15 UPS modes
F2
3,15A 250V
VAKK
VBAT
GND
1
J12
1
J16
VAKK
VBAT
GND
Table 4. UPS modes
Mains
mode
Boost
mode
Buck
mode
Inverter
mode
Standby
mode
Standbycharge
mode
OFF
mode
UPS input On On On Off Off On Off
UPS output On/off On/off On/off On Off Off Off
Battery charger On On On Off(1) Off On Off
Inverter Off Off Off On Off Off Off
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1.1.17 Signals functions table
VDCDC PD5 12 ADC analog inputConverter DC/DC output voltage
measurement signal
TX PE0 44 SCI transmit data out RS-232C TxD signal
RX PE1 1 SCI receive data in RS-232C RxD signal
CHOFF PF0 15 digital output/active high Battery charging mode control signal
BUZZER PF1 16 digital output/active high Buzzer signal
ACI PF2 17 digital output/active high Mains relay control signal
ON/OFF PF4 18 digital output/active high Power supply VDD on/off
TERM Active Active Active Active Active Active Inactive
CHOFF Active Active Active H L Active Inactive
BUZZER Active Active Active Active Active Active Inactive
ON/OFF H H H H H H L
BUTTON Active Active Active Active Active Active Active
LEDR Active Active Active Active Active Active Inactive
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1.1.18 Detailed description of mechanics
The standard enclosure dimensions are as follows:
Main PCB:
– Dimensions: 230 x 160 mm
– Type: double-sided GE (glass - epoxy), FR4 with SMOBC
LEDs and button PCB:
– Dimensions: 80 x 25 mm
– Type: single-sided GE (glass - epoxy), FR4 with SMOBC
LEDG Active Active Active Active Active Active Inactive
LEDY Active Active Active Active Active Active Inactive
TX Active Active Active Active Active Active Inactive
RX Active Active Active Active Active Active Inactive
USB_IN! H or L H or L H or L H or L H or L H or L L
BAT_LOW L L L H or L H or L L L
UPS_OFF! H or L H or L H or L H or L H H L
MOSI Active Active Active Active Active Active Inactive
ICC_SEL L L L L L L Active(1)
ICC_DATA/ MISO
L/ Active L/ Active L/ Active L/ Active L/ Active L/ Active Active(1) / Inactive
ICC_CLK/
SCKL/ Active L/ Active L/ Active L/ Active L/ Active L/ Active
Active(1) /
Inactive
PHASE Active Active Active Active Active Active Inactive
INP_LEV Active Active Active Active Active Active Inactive
OUT_LEV Inactive Inactive Inactive Active Inactive Inactive Inactive
PWR_LEV Active Active Active Active Inactive Inactive Inactive
1. Programming microcontroller only
H - high level +5 Vdc
L - low level 0 Vdc
Active - active signal
Inactive - inactive signal
Table 6. Signals functions table (continued)
Mains
mode
Boost
modeBuck mode
Inverter
mode
Standby
mode
Standby
charge modeOff mode
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1.2.3 System architecture
1.2.4 Main loop
The UPS works in 7 modes:
– Inverter mode - if the mains voltage is lower than 167 VAC RMS(87 for USversion) or higher than 286 VAC RMS(153 for US version) the inverter is switchedon. At outputs INV_B and INV_A, a PWM signal 50 Hz (60 for US version) with40% or less duty cycles (depends on DC/DC output voltage) is generated. Ininverter mode the ACF signal is switched on. If the mains voltage returns to thecorrect value (167 - 286 VAC or 87 - 153 VAC for US version), the PWM signal is
SDA Shutdown type: 0 – output, 1 - system
ST1 Battery condition (0 – good, 1 – weak, 2 - replace), battery status (0 –normal, 1 – low, 2 - depleted), battery voltage (V/10), battery current (A/10)
ST2 Input num lines (1), mains frequency (Hz/10), mains voltage (V/10)
Query (3 characters) Response (values separated by commas)
ATR Auto restart: 0 - disabled or 1 - enabled
SDA Shutdown type: 0 – output, 1 - system
PSDShutdown after delay (if parameter > 0: second to shutdown, if parameter =
-1: cancel shutdown)
RWD Reboot with duration (parameter – seconds to startup after shutdown)
STD Startup after delay (parameter – seconds to startup)
TST Battery test: 1 – test or -1 – cancel test
Table 10. Additionally UPS support order not defined in SEC protocol
Query (3 chars) Response (values separated by commas)
ASHAuto shutdown: 0 – disabled, 1 – enabled or poll. UPS is shut down when output
current is less than or equal to 100 mA.
Table 8. Poll commands
Query (3 characters) Response (values separated by commas)
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synchronized with the mains, the ACF! signal is set to low and the inverter isswitched off.
– Mains mode - in this mode the battery charger is switched on and the UPS issupplied from the mains. The inverter is switched off (INV_A and INV_B are in low
state), and ACF! is high.– Buck mode - in this mode the battery charger is switched on and the UPS is
supplied from the mains. The ACH signal is switched on, the inverter is switchedoff, ACF! is high and the ACL signal is in low state.
– Boost mode - in this mode the battery charger is switched on and the UPS issupplied from the mains. The ACL signal is switched on, the inverter is switchedoff, ACF! is high and the ACH signal is in low state.
– Standby mode - in this mode the battery charger is switched off and the UPS issupplied from the battery. ACH and ACL are in low state, ACF! is low, CHOFF ishigh, and the inverter is switched off.
– Standby charge mode - the UPS is in this state when the mains is lower than thelow level boost mode. ACH and ACL are in low state, ACF! is high, CHOFF is low,and the inverter is switched off.
– OFF mode - the UPS in this mode is totally switched off. This state is availably onlyin battery mode after pressing the on/off key longer than 4 seconds.
Additionally the UPS tests the battery. The battery test is done by switching to the invertermode. During the test the MCU measures UPS output load and battery voltage. If thebattery voltage during the test falls below the limit, the battery is failing. The value of the limitdepends on time and load current. The test can be forced by the user with a PC. The batterycondition can by checked after switching to the inverter mode without forcing the test. A loadis necessary to test the battery.
Table 11. Signal state in different modes
Work mode INV_A INV_B ACH ACL ACF! CHOFF SHD
Inverter mode
50 Hz (60 for US
version) PWM
signal (less than
40% duty cycle)
50 Hz (60 for US
version) PWM
signal (less than
40% duty cycle)
L L L L
Signal is switched to
L after rising edge
INV_A or INV_B and
switched to H before
falling edge INV_A
or INV_B.
Mains mode L L L L H
Depends on
battery
voltage
H
Buck mode L L L H H H
Boost mode L L H L H H
Standby mode L L L L L H H
Standby charge
modeL L L L H
Depends on
battery
voltage
H
Off mode L L L L H L L
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Figure 12. Main flowchart
1.2.5 ADCThe ADC thread measures values as described below:
Mains voltage - the voltage measured at INP_LEV is needed for calculating thefollowing values:
– RMS - true RMS main voltage which determines the working mode of the UPS:mains mode, buck mode, boost mode or inverter mode. This value is calculated forone period of input voltage.
– SAMPLE - actual sample voltage which is the value needed for calculating RMS.Additionally this value is needed to compare with the predicted value of the mains
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Figure 14. DC/AC inverter
D C
/ A C I N V E R T E R
H V D C
G N D
D 1
S M B Y T 0 1
V D D
R 1 2
1 0 k
R 1 1
1 0 k
R 7
1 0 0 R
C 1
1 0 u F
/ 2 5 V
R 1 4
1 0 k
R 1 3
1 0 k
L I N
1
H I N
2
V C C
3
G N D 4
L V G
5
V O
6
H V G
7
V B
8
U 1
L 6 3 8 7 D
Q 1
S T P 1 2 N M
5 0
Q 2
S T P 1 2 N M 5 0
Q 4
S T P 1 2 N M 5 0
Q 3
S T P 1 2 N M 5 0
D 2
S M B Y T 0 1
V D D
C 2
1 0 u F
/ 2 5 V
L I N
1
H I N
2
V C C
3
G N D 4
L V G
5
V O
6
H V G
7
V B
8
U 2
L 6 3 8 7 D
I N V
_ B
I N V
_ A
I N V
_ A
I N V
_ B
I N V
_ O U T 2
I N V
_ O U T 1
R 1 1 0 0 R
R 2
1 0 0 R
C 8
1 0 0 n
F
C 1 0
1 0 0 n F
C 9 1
0 0 n F
C 1 1
1 0 0 n F
G N
D
G N
D
G N D
G N D
R 3
0 R
D 3
B A S 1 6
R 8
1 0 0 R
R 4
5 1 R
D 4
B A S 1 6
R 1 0 1
0 0 R R
6
5 1 R
D 7
B A S 1 6
R 9 1
0 0 R
R 5
0 R
D 6 B
A S 1 6
Z D 1
S M 6 T 1 8 A
D 5
B A S 1 6
Z D 2
S M 6 T 1 8 A
D 8
B A S 1 6
S T P 2 2 N S 2 5 Z
S T P 2 2 N S 2 5 Z
S T P 2 2 N S 2 5 Z
S T P 2 2 N S 2 5 Z
R A D 1
H e a t s i n
k
R A D 3
H e a t s i n
k
R A D 2
H e a t s i n
k
R A D 4
H e a t s i n
k
C 4
1 0 u
F / 3 5 V
C 3
1 0 u F
/ 3 5 V
I N V
_ A
I N V
_ B
I N V
_ A
I N V
_ B
I N V _ O U T 1
I N V _ O U T 2
1 2 0 V a
c M o
d e l
2 3 0 V a
c M o
d e l
H V D C
G N D G
N D
H V D C
V D D
V D D
R 1 7 3
4 7 R
R 1 6 4 1 0 R
D 4 7
S T T H 1 L 0 6 A
D 4 8
S T T H 1 L 0 6 A
R 1 7 4
4 7 R
R 1 7 2
1 0 R
C 3 6
1 0 0 p
F
G N D
C 3 5
1 0 0 p
F
G N D
C 3 9
1 0 0 p
F
C 4 0
1 0 0 p F
G N D
G N D
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Figure 17. Power switches
1 J 8 6 .
3 x
0 . 8
1 J 7 6 .
3 x
0 . 8
1
2
3
4
L 8
1 : 1 0 0 0
I O U T _ 2
I O U T _ 1
R L 5
R M 8 4
- 2 0 2 2
- 2 5
- 1 0 2 4
R L 2
R M 8 5 - 2 0 1 1
- 2 5 - 1
0 2 4
R L 3
R M 8 5
- 2 0 1 1
- 2 5 - 1
0 2 4
1 J 5
6 . 3
x 0
. 8 1
J 4
6 . 3
x 0
. 8
D 1 2
B A S 1 6
D 3 4
B Z V 5 5 C 2 0
D 3 3
B Z V 5 5 C 2 0
D 1 1 B
A S 1 6
V P P
V P P
V P P
A C L !
A C H !
D 3 5
B Z V 5 5 C 2 0
D 1 4 B
A S 1 6
O U T
_ R E L !
R L 4
R M 8 4
- 2 0 1 2
- 2 5
- 1 0 2 4
I N V _ O U T 1
I N V _ O U T 2
1 J 6
6 . 3
x 0
. 8
D 1 3
B A S 1 6
D 3 6
B Z V 5 5 C 7 5 V
P P
D 1 0
B A S 1 6
D 3 1
B Z V 5 5 C 1 0
V P P
A C F
O
U T P U T
I O U T
_ 2
I O U T
_ 1
O U T
_ R E
L !
A C H !
A C L !
A C F
A V R
A C
_ 1
A C
_ 2
A C
_ I N 1
A C
_ I N 2
R L 1
S C L
- 1 - H - D
P N O
A C I !
A C I !
D 3 2
B Z V 5 5 C 1 0
1 2 0 V a c
M o
d e l
2 3 0 V a c
M o
d e l
I N V
_ O U T 2
I N V
_ O U T 1
A C
_ I N 2
A C
_ I N 1
V P P
G N D
G N D
V P P
A C
_ 1
A C
_ 2
t R T 1
J N R 1 5 S 7
0 L
t
R T 2
J N R 1 5 S 7 0 L
J N R 1 5 S 2 R 5 M
J N R 1 5 S 2 R 5 M
D 4 9
B Z V 5 5 C 7 5
B L A C K
W H I T E
R E D
B R O W N
B L U E
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Figure 18. AC/DC battery charger
A C / D C B A T T E R Y C H
A R G E R
G N D
R 9 4
1 0 k
C 1 0 1
1 0 0 0 u F / 5 0 V
G N D
D 3 8
S T P S 8 H 1 0 0 D
D 1 6
B A S 1 6
G N D
C 9 9
1 n F 5 0 0 V
R 6 4 1 0 R
R 1 6
1 0 k
G N
D
C 2 0 1 0 0 n F
G N
D
L 1 1
1 0 u H / 3 A
C 1 9
1 0 0 n F
G N D
+ V O
U T
G N D
1 4
1 2
1 0
6 7 3 2
9
`
8 1 1
1 3
T 1
T I 5 0 / 3 0 v 0 2
R 2 0
1 0 0 k
V D D
F 1
1 , 2
5 A
C 9 6
1 0 0 n F X 2
V F F
3
V D D 8
Z C D 5
V F B 1
C O M P 2
G D
7
C S
4
G N D 6
U 1 1
L 6 5 6 5
G N D
G N D
R 1 3 4
1 6 k
R 1 3 2
7 5 0 k
R 1 3 5
4 3 k
R 9 5
1 0 k
G N D
R 1 3 8 3 3 k
V B A T M A X +
2 8
. 2 V
6 1
8
7
2 3
U 1 2
T L 4 3 1 C D
R 1 3 6
3 9 k
R 1 1 5
3 . 3
k
R 5 7
2 2 k
G N D
R 1 3 9
5 . 6
k
R 1 4 0
1 8 0 R
Q 1 2
B C 8 5 7 B
O v e r v o l t a g e P r o t e c t i o n 3 2 V
T H 1
T Y N 6 0 8
G N D
2
1
3
4
B R 1
K B U 6 0 5
C o n t r o l v o l t a g e o u t p u t
C u r r e n t M o d e C h a r g i n g
V o l t a g e M o d e
C h a r g i n g
P o u t ( m a x ) = 5 0 W
C h a r g e r O u t p u t
V B A T
R 1 2 9 1 0 R
G N D
G N D
Q 1 1
S T P 5 N K 9 0 Z
R 1 3 3 3 3 R R 1 5 1 0 k
G N D
C H O F F
V B A T M I N + 2 6
. 8 V
R 1 2 3
1 0 0 k
D 3 7
S T T H 1 R 0 6
R 1 2 7
1 2 0 k 3 W
C 9 7
6 8 0 p F 1 6 0 0 V
A C
_ 2
A C
_ 1
Q 1 0
S T P 8 0 P F 5 5
U 6
P D T C 1 1 4 E T
+ V O U T
Z D 3
B Z X 8 4 C 1 2
C 1 0 0
1 0 0 u F / 5 0 V
G N D
R A D 1 1
H e a t s i n k
2 A
R 1 3 1
7 5 0 k
R 1 3 0
7 5 0 k
G
N D
R 6 3
1 0 R
R 1 2 4
1 0 0 k
R 1 2 5
1 0 0 k
R 1 2 6
1 0 0 k
G N D
C 9 8
4 7 u F / 5 0 V
C 2 1 1 0 0 n F
G N D
G N D
C 1 0 2
1 0 0 0 u F / 5 0 V
R 1 2 2 1 0 0 k
G N D
R 6 5 1 0 R
R 1 2 8
1 2 0 k 3 W
R A D 1 2
H e a t s i n k
R 1 3 7
0 . 6 8 R 2 W
L 9
1 0 u H / 3 A
L 1 0
1 0 u H / 3 A
C 1 8 1 0 0 n F
C 4 9
1 n F
C 7 9
1 0 n F
C 9 5
4 7 n F X 2
1 2 0 V a c
M o
d e l
2 3 0 V a c
M o
d e l
C H O F F
A C
_ 1
A C
_ 2
D 1 5
B A S 1 6
D 1 7
B A S 1 6
Q 9
S T P 8 0 P F 5 5
V B A T
G N D
+ V O U T
G N D
+ V O U T
V D D
V D D
R 5 2
4 . 7
R 3 W
C 4 4
4 7 n F X
2
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Figure 19. PC interface stage
C O M C
1 0 3
2 2 u F / 3 5 V
V +
C O M
R 1 2 1
2 . 2
k
C 1 0 9
2 . 2
u F / 5 0 V
T R I G
2
Q
3
R
4
C V o l t
5
T H R
6
D I S
7
V C C 8
G N D 1
U 1 4
T S 5 5 5 C D T
C O M
C 2 5 1
0 0 n F
C 2 3
1 0 0 n F
C 5
1 0 u F / 3 5 V
C 2 2
1 0 0 n F
R 9 7 1
0 k
R 4 1
4 . 7
k
V -
D 1 8
B A S 1 6
C O M
C O M
V P C
V P C
O F F
O F F
1 6 2 7 3 8 4 9 5
J 1 4
U 2 1
P C 8 1
7 C
U 1 9
P C 8 1 7 C
U 2 0
P C 8 1 7 C
D 1 9
B A S 1 6
R 4 5
4 . 7
k
R 1 4 8
2 . 4
k
R 1 4 7
8 2 0 R
B T L
A C F L
O F F
R 1 4 6
4 . 7
k
R 1 4 5
4 . 7
k
R 4 8
4 . 7
k
U 2 2
P C 8 1
7 C
U 2 3
P C 8 1 7 C
R 1 1 2
1 0 0 R
R 9 9
2 0 k
R 1 4 4
2 . 2
k
R 1 4 9 6
. 8 k
D 2 0
B A S 1 6
R 1 4 2
3 . 3
k V
- V +
T X D 1
R X D 1
C O M
V C C
V C C
G N D
V C C
C O M
C O M
C O M
V +
V +
V C C
C O M
V P C
B A T
_ L O W
A C F 1 !
U P S
_ O F
F !
R X D
T X D
Q 1 3
B C 8 4 6 B
Q 1 4
B C 8 5 7 B
G N D
A C F 1 !
B A T
_ L O W
U P S
_ O F F !
R X D
T X D
G N D
T x D
_ U S B
G N D 1
G N D 1
C 9 2
2 2 p F
C 9 1
2 2 p F
Y 2
2 4 M H z
U S B D M
G N D 1
1 2 3 4
J 1 3 U
S B - B
G N D 1
C 2 4
1 0 0 n F
R 4 3
4 . 7
k
G N D 1
T x D
_ U S B
U S B
R x D
_ U S B
O S C O U T
O S C I N
R S T
_ U S B
U S B D P
U S B V C C
+ 5 V
_ U S B
O S C O U T
O S C I N
+ 5 V
_ U S B
U S B D M
U S B D P
I C C C L K
I C C D A T A
V P P
_ U S B
C 6
1 0 u F / 3 5 V
I C C D A T A
I C C C L K
R S T
_ U S B
V P P
_ U S B
G N D 1
+ 5 V
_ U S B
I C C D A T A
I C C C L K
R 9 8
1 0 k
V P P
_ U S B
G N D 1
U S B V C C
R 1 4 1
1 . 5
k
U S B
S o c k e t
C 5 7
1 0 0 p F
C 5 8 1 0 0 p F
C 8 0
1 0 n F G
N D 1
R S T
_ U S B
R x D
_ U S B
I C P
R X D 1
T X D 1
A C F L
B T L
O F F
U 1 7
P C 8 1 7 C
U 1 8
P C 8 1 7 C
R 4 4
4
. 7 k
R 1 4 3
4 . 3
k
+ 5 V
_ U S B
G N D 1
G N D
R 4 7
4 . 7
k
V C C
U 1 6
P C 8 1 7 C
R 4 2
4 . 7
k G N D 1
+ 5 V
_ U S B
R 4 6
4 . 7
k
G N D
V C C
G N D
G N D
+ 5 V
_ U S B
I N H
6
A D D R A
1 1
A D D R C
9
A 1
1 2
A 2
1 3
B 1
2
B 2
1
C 1
5
C 2
3
C
4
A
1 4
B
1 5
V C C 1 6
V S S 8
A D D R B
1 0
V E E 7
U 2 4
M 7 4 H C 4 0 5 3 R M 1 3 T R
V C C
U S B
_ I N !
G N D 1
G N D 1
D 4 0
B A
T 5 4 S
D 3 9
B A T 5 4 C
D 4 1
B A T 5 4 A
V c c 1
1
V c c 2
8
O u t 1
7
I n 1
2
I n 2
3
G n d 1
4
O u t 2
6
G n d 2
5
U 1 3 U S B 6 B 1
D a t a P r o t e c t i o n
C 2 6
1 0 0 n F
G N D
C 5 9
1 0 0 p F
C 6 0
1 0 0 p F
G N D 1
G N D 1
C 1 0 6
1 0 0 n F
G N D 1
+ 5 V
_ U S B
G N D 1
G N D 1
V C C
1 3 5 7
2 4 6 8
9
1 0
J 1 5
I D C 1 0
1 2 0 V a c M o d e l
2 3 0 V a c M o d e l
U S B
_ I N !
V C C
G N D
G N D
V C C
N C 1 0
N C 9
N C 8
N C 4
N C 5
N C 6
N C 7
R 1 6 5
1 0 k
G N D 1 R
1 6 6
1 0 k
G N D 1 R
1 6 7
1 0 k
G N D 1 R
1 6 8
1 0 k
G N D 1 R
1 6 9
1 0 k
G N D 1 R
1 7 0
1 0 k
G N D 1 R
1 7 1
1 0 k
G N D 1
N C 1 0
N C 9
N C 8
N C 4
N C 5
N C 6
N C 7
V S S
4
U S B D M
2 3
U S B D P
2 2
R E S E T
7
O S C I N
3
O S C O U T
2
P A 7
1 4
P B 6
8
P A 5
1 5
P A 4
1 6
P B 3
1 0
P B 2
1 1
P B 1
1 2
P B 0
1 3
V D D
1
P A 1
1 9
P A 0
2 0
U S B V C C
2 4
V P P
9
P C 0
6
V S S A
2 1
P C 1
5
P A 3
1 7
P A 2
1 8
U 1 5
S T 7 2 F 6 3 B E 2 M 1 S O 2 4
G N D 1
N C 1 1
N C 1 2
N C 1 3
R 8 5
1 0 k
G N D 1 R
8 4
1 0 k
G N D 1 R
4 0
1 0 k
G N D 1
N C 1 1
N C 1 2
N C 1 3
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Figure 21. Measurement stages
R155
1k
R158
20R
D23
BAS16
VCC
C84
10nF
GND
R156
47.5k
R157
47.5k
C117
1.5nF
R150
6.8k
GND
C118
1.5nF
R151
6.8k
R50
4.7k
R51
4.7k VCC
IOUT_1
IOUT_2
PWR_LEV
OUTPUTCURRENT
10
98
U28C
LM324 10R
IOUT_1
IOUT_2
120Vac Model230Vac Model
PWR_LEV
VCC
GNDGND
VCC
R15920k
R25100k
GND GND
VBATVCC
BATTERYVOLTAGE
D24BAS16
AKK_LEV
C63
10uF/50V
1
AKK_LEV
VCC
GNDGND
VCC
VBATVBAT
R83
200k
R82
200k
R81
200k
R80
200k
OUT_LEV
AC_2
AC_1
INVERTER OUTPUTVOLTAGE
R16082k
GND
C8510nF
GND
R1612.4k
GND
100k 100k
100k 100k
2k
AC_1
AC_2
OUT_LEV
120Vac230Vac
GNDGND
R154
1k
D22
BAS16
VCC
C83
10nF
GND
R21
100k
R22100k
C115
1.5nF
R23
22k
GND C116
1.5nF
R24
22k
R100
10k
R101
10k VCC
INP_LEVAC_IN1
AC_IN2
INPUTVOLTAGE
R77
750k
R76
750k
R79
750k
R78
750k R492k
12
1314
U28D
LM324
360k 360k
360k 360k
AC_IN1
AC_IN2
INP_LEV
120Vac Model230Vac Model
R26 1k
R2710k
R10210k
VCC
D46
BAT54
R162
1M
INPUTVOLTAGE PHASE
R10310k
GND
PHASE
R11710k
GND
VDD
VDD
GND
C7
10uF/35VC31
100nF
GND
3
21
4
1 1
U28A
LM324
5
67
U28B
LM324 GND
PHASE
VCC
GNDGND
VCC
VDDVDD
R1762k
GND
GND
GND
VCC
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2.2 Layout
Figure 24. Top view
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2.3 Assembly description
2.3.1 General
Table 17. UPS components
Model
Type 120 Vac version 230 Vac version
Case UPS Ares 700/1000
Power cord 3 x 1.0 mm2
Control panel UPS 500 rack
Battery VRLA type 2 x 7,2 Ah/12 V
AVR transformer AVR 700/ST/120/1 AVR 700/ST/230/1
Switch/fuse ETA 3120-F35G-P7M1-D04X -12 A ETA 3120-F35G-P7M1-D04X -6 A
Output wires Twisted 2x1.0 mm2, 30 cm long
Ground wire 1x1.0 mm2, 30 cm long
Ferrite toroidal core Richco RT250-150-120
Battery fuse 40 A
Motherboard ver. 020
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2.3.2 Electrical
The schematic of the electrical connections is shown in Figure 26 .
Figure 26. Electrical connections
2.3.3 Mechanical
The UPS case with assembled front and power cord.
Figure 27. Mechanical view
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Figure 28. UPS with assembled rear outlets
Figure 29. UPS with front button and indicators
Figure 30. UPS with batteries and battery fuse
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Figure 34. UPS with motherboard
Figure 35. UPS fully assembled
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2.5 Signalization description
2.5.1 Indicators
2.5.2 Sound alarms
2.6 Bill of material
2.6.1 Bill of material for 120 Vac version
Table 25. Indicators
Green LED
(mains)
Yellow LED
(battery)
Red LED
(failure/overload)
Mains mode Solid on Off Off
Battery mode OffSolid on
Flash On (BATLOW)Off
Buck/boost mode Flash on Off Off
Battery charging Solid on Flash on Off
Overload (mains) Solid on Off Flash on
Overload ( battery) Off Solid On Flash on
Self test Solid on Solid on Off
Fault ( mains) Solid on Off Solid on
Fault (battery) Off Solid on Solid on
Standby mode Off OffFlash on
(one per 2 sec.)
Table 26. Sound alarms
State Beeper alarm sequence
Inverter mode 1 beep with 1 s. interval by 15 s. and after this 1 beep with 15 s. interval
Overload 1 beep with 0.3 s. interval
BATLOW continuous signal
State Beeper alarm sequence
Inverter mode 1 beep with 1 s. interval by 15 s. and after this 1 beep with 15 s. interval
Table 27. Bill of material for 120 Vac version
Part type Designator Manufacturer Qty Ordering code
Table 28. Bill of material for 230 Vac version (continued)
Part type Designator Manufacturer Qty Ordering code
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4 Revision history
Battery recharge Two recharge steps Two recharge steps
First step Constant current(Imax=2.16 A, Vmax=28.2 Vdc)
Constant current(Imax=2.16 A, Vmax=28.2 Vdc)
Second stepHysteresis constant voltage
V=27.3 Vdc ± 0.5 Vdc
Hysteresis constant voltage
V=27.3 Vdc ± 0.5 Vdc
Table 29. Technical specifications (continued)
Parameters 120 V/60 Hz model 230 V/50 Hz model
Table 30. Document revision history
Date Revision Changes
18-Jul-2008 1 Initial release
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UM0527
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