University of SSouthern CCalifornia of SSouthern CCalifornia School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #05&6 Spring, 2004 (Due 03/09/2004)

UUUniversity of SSSouthern CCC alifornia School Of Engineering

Department Of Electrical Engineering

EE 348: Homework Assignment #05&6 Spring, 2004 (Due 03/09/2004) Choma

Problem #18: In Fig. (18ia), the small signal representation of common source amplifier

with resistively feedback is depicted. Also, in Fig.(18b), the aforementioned small signal model has been transformed in more compact model. In subsequent lines, this transformation shall be proven. What is more, Vg is the small signal gate voltage, which is specified at the input (IN) port, with respect to ground. Vos is the small signal output voltage with respect to ground.

(a) (b) Fig. (P18i)

( )

gme1 g 2

2 ssg g

ss b1 2

b

V =V +V

V =-IR gmI= V gmeV

1+R gm 1+I=gmV gmbVgmb= gm

λ

λ

=+

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Since I is dependent only to the small signal gate voltage, it can be represented by only one dependent current generator with effective transconductance as it is depicted in Fig. (18ib).

(a). Based one previous finding, we can go ahead plug the ohm-meter into the input port find the voltage to current ratio which in turn will yield input resistance. The topology will look like Fig.(18ii).

x g x f lin

x x g l x f x l

V =V V R RR

V =(I -gmeV )R +I R I 1 gmeR

+= =

+

Fig.(18ii)

EE 348 University of Southern California J. Choma, Jr.

Homework #05&6 Spring Semester, 2004

(b). The very similar method will be applied as in the previous part with an exception of that

we remove load and put the ohmmeter to output port and turn off the signal source. Hence,

x g

f sx xx g out

f s x s

s xg

f s

V =V

R RV VI =gmeV + R

R R I 1 gmeRR V

VR R

+

= =+ +

=

+

Fig.(18iii)

(c).By equating either Rin or Rout to RS we can get required design condition for Rf. Thus,

2ff

R RR R gmeR

1 gmeR+

= =+

(d). If we carefully examine Fig.(18ia,b), we can see that input port will have half of the signal voltage: for the circuit is match terminated. In other words, the power supply sees an input resistance equal to the power supply resistance, therefore; by the voltage division rule, one can see that input port will be equal to half of the signal voltage. (Maximum power transfer!) Having stated this:

( )( )

sg

l fos

g os os s l fg

f l

VV =

R 1 gmeR2 VV V V V 2 R RgmeV

R R

−

=− += +

è

( )( )

l fos

s l f

osl

s2f

R 1-gmeRV=

V 2 R +RV 1-gmeR

R =RV 2

R =gmeR

=

Problem #19: Since M1 and M2 share the same gate and sources, also are identical in all

senses, they will carry the same drain currents. This concludes that M1, M2, M3, and M4 of Fig. (19) have the same drain current but not necessarily the same gate to source voltage. Furthermore, since M1, M2, and M3 are identical inclusive of their gate aspect ratios, and they will share the same gate to source voltage.



M1

M3

M2

M4

+Vdd

IQ

Vref

Rout

Fig. (P19)

( )2GS1 TH Q

D2 D4 Q

GS1 GS2

Kn WV -V =I

I =I =I2 LV V

=

&

( )

( )

2GS1 TH

2GS3 TH

GS3 G3 S3 G3 G1

S3 G2

Kn1 V -V

2 =1Kn

1 V -V2

V V V V 2VV V

= − ==

( )

( )

2GS1 TH

GS4 G1 TH2

GS4 TH

GS4 G4 S4 G3 REF REF TH

Kn4 V -V

2 =1 V 2V -VKn

1 V -V2

V V V V V V V

=

= − = − =



Problem #20:

M1

M2R

M3

M4 M5

+Vdd

Iout

Rout

Fig. (P20)

Since M4 and M5 are identical inclusive of their gate aspect ratio, also have the same gate to source voltage they will carry the same drain current. In addition, Iout will be k times larger than drain current of M2 and M5, as M2 and M3 have the same gate to source voltage difference and are identical except that M3 have k times larger gate aspect ratio.

( )

( )

( )

?G1 G2

D2 D5 D4 D1

2 G2 THG1 G2 TH D2GS2 TH

2GS1 TH

2G2 THG2 TH G2 TH

D2 out2 2

V -VI =I =I =I =

RV -VKn W V V k V ( k 1) I ( k 1)k V -V R2 L =1

Kn W V -V2 L

V -V Kn W ( k 1) 2( k 1) k V -V V -V

WR 2 L k Kn RL

( k 1) 2 2( k 1)I I

W Wk Kn R Kn RL L

= − − = −

−− = =

− −= ⇒ =



Problem #21: (a). When we try to find the output resistance of this system, we will observe that at the gate

of M3 there can be zero signal : For the gate of M3 isolates itself from the rest of the circuit and we apply signal to the drain of M3 , that is, ohmmeter signal. There can not be any trace of the signal at the gate of M3 at low frequencies. This deduces zero AC voltage at the gate. We also know source has zero voltage already, therefore there will not be any current generated by gate to source voltage (gmVgs=0). Furthermore, since bulk is connected to source, there will not be any bulk induced current (gmbVbs=0). Hence, when we put the ohm meter into the drain of M3, we will only observe channel resistance. As a result, by inspection, the output resistance is the channel resistance of M3!

(b). The same argument can be carried out as the part (a); as for the gates of M1 and M3 will

have zero AC signal on them. Moreover, when we put an ohm-meter into the node where VREF is located we will see two parallel resistances. One is looking into the drain of M2 , and the other is looking into the source of M4. So we can find these two resistances separately, and their parallel expressed form will be the output resistance. Also, we can extrapolate what we found in part (a). That is since we looked into the drain of M3, that finding should hold for all MOSFETS whose sources, gates, and bulks are at AC ground. That is to say looking into the drain of M2 we will see the channel resistance of M2 (rO2). Let’s find the resistance looking into source of M4 (This finding should also hold for all MOSFETs whose drain coupled to power supply directly!).

Fig.(21)

1 2 x

xx 4 1 4 2 x 4 source

x 4 4 4 44 b4 4

V =V VV 1 1

I =-gm V -gmb V V goI gm gmb gm

gmb = gmR

goλ

= −

+ = = ≈+ +

è out 2 source4

1R =ro //R

gm≈



Problem #22: This is a common source amplifier with a diode connected NMOS active load. So we can separately find the active resistance of NMOS and then continue to our analysis.

Fig.(22i)

1 2 x xLeff

x L 1 L 2 x L x L L L

V =V V V 1 1I =-gm V -gmb V V go I gm gmb gmL

Rgo

= − = = ≈

+ + +

The, the small signal representation of common source amplifier will collapse to the following:

Fig. (22ii)

(a)

1 s NTHTH N Leff N

TH N s Leff N s L

TH Leff NL

V =V gmVA =- =gm R //ro

V =-gm V R //ro V gm

1R =R //ro

gm

≈

≈



To find, the RTH we need to put an ohm-meter at the node of VTH and turn off Vs, and hence, by inspection, RTH becomes RLeff//roN. In here, VTH is the Thevenin voltage seen by capacitive load and also low frequency gain of the circuit.

(b) LTH L Leff N L

L

C=R C =R //ro C

gmτ ≈

(c) Using the voltage division in Thevenin equivalent circuit, one can arrive at ensuing result:

N

N Leff N L

l

L

gm-gm R //ro gm

Av(s)=C1+s 1 s

gmτ

≈ −+

(d)

( )

L3

TH L L

2

NN

L NL2

TH L LTH L

gm1 1= =

R C C

gmgm 1gm gmgm

1R C C1 R C

dB

U

U

ωτ

ωω

= ≈

−

= ⇒ = ≈+

Problem #23:

This circuit is also a common source amplifier with an exception of the load. In this configuration, the load is an active PMOS load. In order to find, the effective resistance of this load, we will plug the ohm-meter into the drain of MOSFET, this will, by inspection, give us the channel resistance; Thus, Leff PR =ro . The analys is will be the same as of problem#22.

(a) 1 s NN N TH Leff N P N

N N s s

V =V IG =- =gm R =R //ro ro //ro

I =-gm V V

=

(b) TH L Leff N L N P L=R C =R //ro C ro //ro Cτ =

(c) N Leff N N P N

l P N

-gm R //ro gm ro //roAv(s)=

1+s 1 sC ro //roτ= −

+



(d)

( )( )

3TH L L P N

2N P NN P N N

2P N L L

TH L

1 1 1= =

R C C ro //ro

gm ro //ro 1gm ro //ro gm1

ro //ro C C1 R C

dB

U

U

ωτ

ωω

=

−= ⇒ = ≈

+

Problem #24: The topology is a source follower or common drain circuit and its small signal equivalent

without the capacitive load is as follows:

Fig.(24)

(a)

{ }( )

( )

1 s THTH 1 2 1

2 TH THs 2 1 1 1

TH 1 1 1 2 2 1

TH source 2 source1 1 1

TH1

V =V VV gmro //ro

V V A =- =- 1V 1 ro //ro gm 1

V = gm V +gm V ro //ro

1R =R //ro where R

gm 1 go

1R

gm

b

b

λ

λ

−

= − ≈ −+ +

=+ +

≈

(b) LTH L source 2 L

1

C=R C =R //ro C

gmτ ≈

(c) ( )1 2 1

2 1 1 1

L

1

gm ro //ro1 ro //ro g m 1 1

( )C1 1

gm

bAv ss s

λτ

+ += ≈

+ +



(d) Since the gain is never greater than one, it is futile to try find a unity gain frequency!

13

TH L L

gm1 1=

R C CdBωτ

= ≈

Problem #25:

In order to transform, the given topology into its small signal equivalent, first, one needs to short the output. The output shorted small signal is as the subsequent:

Fig.(25)

(a) ( )

( ) ( )( )

1 2

N N 1 N 2 N NN N bN

N bN N

N N bNNN s s i

s N N bN

V =V =-V1

I =gm V gmb V - go V V=- Igo +gm 1+

gmb = gm

go +gm 1+IV= I I R A = 1

I go +gm 1+ gs

λλ

λλ

+

− = ≈+

To find the output resistance, we will use the ohmmeter method at the output port. Thus, we can simply utilize preceding equations in which, the output will be Vx in stead of zero, IN=Ix, and Is will be zero Thus,

( )1 2 x s

xx N 1 N 2 x N s N s N N s N N

xN bN N

V =V =-V=-I RV

I =gm V gmb V V - V go R o R o gm (1 ) R o gmI

gmb = gmN bNR r r rλ

λ

+ + = = + + + ≈



(b) [ ]N L s N s N N L s N N L=R C = R o R o gm (1 ) C R o gm CbNr r rτ λ+ + + ≈

(c) Since at low frequency the capacitive load will be open circuit, there will be infinitely large resistance looking from the input port. The reason for this is, there is no path from output to ground, and hence ohm-meter current will be forced to zero. This renders infinitely large resistance.

(d) s N NR o gm1

os Ni

s

V RA r

I sτ= − ≈

+

(e)

( )( )

3N L L s N N

2

2L L

L

1 1 1=

R C C R o gm

11 ohm

C C1 C

dB

i Ni N iU

NU N

r

A RA R ARR

ωτ

ωω

= ≈

−= ⇒ = ≈

+

Problem #26: Since M1 has k times smaller gate aspect ratio than M2 and M3, gm3=gm2=kgm1.Before writing current gain in terms of k and other parameters , lets find the gain expression in terms of only circuit parameters. First, we must draw small signal equivalent circuit. That is,

Fig.(26)

The diode connected M2 transistor will have an effective resistance as we found in problem#22 with a difference which is in here source and bulk is connected to each other. This renders that there will be no bulk induced current. Thus,

diode4 4 4

1 1R

gm gmgo= ≈

+



Also,

( )[ ]

{ }[ ] [ ]

l diode

1 1 11 s 1 l diode 1 1

1 s 1 1

1 2

l 3 1 3 2 l l l diode 3 1 3l

s 3 diode 1 1 3 d1 s 1 l diode 1 1

V=IR

V V VV I R//ro I R 1 gm R//ro

V I gmV R//ro

V V and V V

I gm V +gmb V I R I R go R//rogmII gm R 1 gm R//ro gmb RV I R//ro I R 1 gmR//ro

+ −

+

−

= − = − +

= − = = −

= + − − =+ += − + ( )iode 3 l diodego R +R+

[ ] ( )1 3 3l

s 3 diode 1 1 3 diode 3 l diode 1

R//rogm RgmII gm R 1 gm R//ro gmb R go R +R 1 gm R

k= ≈ ≈+ + + +

In order to find the bandwidth, we must first find the resistance seen by the capacitance. Once this is found, the bandwidth will be one over the time constant. T do so, we can simply utilize the previous analysis. Hence,

( ) [ ]

{ }[ ] [ ]

l diode

1 x1 x 1 l diode 1 1

x x 1 1

1 2

l 3 1 3 2 l l l diode 3 1 3l

x 3 diode 1 1 3 diode1 x 1 l diode 1 1

V = I R

V V VV I R//ro I R 1 gmR//ro

V I g m V R//ro

V V and V V

I gm V + g m b V I R I R go R//rogmII gm R 1 gmR//ro gmb RV I R//ro I R 1 gm R//ro

−

= − = − += − = = −

= + − − = + += − + ( )

( )( )

[ ] ( )

IA

3 l diode

diode x I 3 diode 3 diode 3 l diode1

x x 1 1 3 diode 1 1 3 diode 3 l diode 1

1

1 1

go R +R

V=R I A gm R gmb R go R +R RR//ro

V I g m V R//ro gm R 1 gmR//ro gmb R go R +R 1 g m R

gmR 11 gm R gm

c

c

R

R BC

+

+ + = ≈= − + + + +

= ≈ ⇒ =+

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University of SSouthern CCalifornia of SSouthern CCalifornia School Of Engineering Department Of Electrical Engineering EE 348: Homework Assignment #05&6 Spring, 2004 (Due 03/09/2004)

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