University of Michigan Electrical Engineering and Computer Science 1 Polymorphic Pipeline Array: A Flexible Multicore Accelerator with Virtualized Execution for Mobile Multimedia Applications Hyunchul Park 1 , Yongjun Park 2 , Scott Mahlke 2 December 12, 2009 Texas Instruments Inc. 1 University of Michigan, Ann Arbor 2
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University of Michigan Electrical Engineering and Computer Science 1 Polymorphic Pipeline Array: A Flexible Multicore Accelerator with Virtualized Execution.
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University of MichiganElectrical Engineering and Computer Science1
Polymorphic Pipeline Array: A Flexible Multicore Accelerator with Virtualized Execution
for Mobile Multimedia Applications
Hyunchul Park1, Yongjun Park2, Scott Mahlke2
December 12, 2009
Texas Instruments Inc.1
University of Michigan, Ann Arbor 2
University of MichiganElectrical Engineering and Computer Science
ARM9 ARM11 TI C6x Core2Duo0
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• Multimedia applications have high performance, cost, energy demands– High-quality video– Flash animation
• Clear need for application and domain-specific hardware
Introduction
24 fps min.
Fram
es/s
ecMPEG-4 Decoder
Cell-phone battery life(hours)
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energyperformance
University of MichiganElectrical Engineering and Computer Science
Convergence of Functionalities
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Anatomy of iPhone
HD TV decoder
Video Recording
Video Editing
3D Rendering
4G Wireless
Advanced Image
Processing
Convergence of functionalities demands a flexible solutionApplications have different characteristics
University of MichiganElectrical Engineering and Computer Science
ASIC Alternatives
General PurposeProcessors
DSPs
Efficiency, Performance
Fle
xibi
lity
ASICs
Domain specificEfficiency
Somewhat programmable
What’s the right way to support multimedia applications ?
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University of MichiganElectrical Engineering and Computer Science5
Coarse-Grained Reconfigurable Architecture (CGRA)
• Array of PEs connected in a mesh-like interconnect• High throughput, low cost/power with distributed hardware• High flexibility with dynamic reconfiguration• Morphosys, SiliconHive, ADRES
University of MichiganElectrical Engineering and Computer Science
• Need a flexible execution model– Exploiting both types of parallelism– Resource allocation based on computation requirement– Dynamically adapt to computation variance
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University of MichiganElectrical Engineering and Computer Science
Polymorphic Pipeline Array
• Multi-core accelerator : each 2x2 array becomes a processor• Cores can be combined to form a larger logical core• Exploit both coarse-grain and fine-grain pipeline parallelism• No dynamic routing logic: all communications statically generated
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Core Core Core Core
Core Core Core Core
Logical Core
Logical Core
Logical Core
University of MichiganElectrical Engineering and Computer Science
Execution Model
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• Pipeline outermost loop
ST 0 ST 1 ST 2 ST 3
ST 0
ST 1
ST 2
ST 3
University of MichiganElectrical Engineering and Computer Science