Page 1 Copyright UCB & Morgan Kaufmann ECE568/Koren Part.2 .1 Adapted from UCB and other sources Israel Koren UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Computer Architecture ECE 568/668 Part 2 Pipelining - 1 Copyright UCB & Morgan Kaufmann ECE568/Koren Part.2 .2 Adapted from UCB and other sources Instruction Execution - Pipelines ♦ Execute billions of instructions, so throughput is what matters ♦ What is desirable in instruction sets for pipelining? • Variable length instructions vs. all instructions same length? • Memory operands part of any operation vs. memory operands only in loads or stores? • Register operand in various places in instruction format vs. registers located in same place? ♦ Conclusion: RISC is easier to pipeline
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Page 1
Copyright UCB & Morgan Kaufmann ECE568/Koren Part.2 .1Adapted from UCB and other sources
Israel Koren
UNIVERSITY OF MASSACHUSETTSDept. of Electrical & Computer Engineering
Computer Architecture ECE 568/668
Part 2
Pipelining - 1
Copyright UCB & Morgan Kaufmann ECE568/Koren Part.2 .2Adapted from UCB and other sources
Instruction Execution - Pipelines
♦ Execute billions of instructions, so throughput is what matters
♦ What is desirable in instruction sets for pipelining?• Variable length instructions vs.
all instructions same length?
• Memory operands part of any operation vs. memory operands only in loads or stores?
• Register operand in various places in instruction format vs. registers located in same place?
♦ Conclusion: RISC is easier to pipeline
Page 2
Copyright UCB & Morgan Kaufmann ECE568/Koren Part.2 .3Adapted from UCB and other sources
Copyright UCB & Morgan Kaufmann ECE568/Koren Part.2 .22Adapted from UCB and other sources
Instruction pipelines are not ideal♦ Instructions interact with each other in pipeline ♦ Hazards prevent next instruction from executing during its
designated clock cycle• Structural hazards: An instruction in the pipeline may need
a resource being used by a previous instruction in the pipeline (e.g., address calculation for one instruction using the same adder used for addition in another instruction)
• Data hazards: Instruction depends on (data) result of prior instruction still in the pipeline:
• Control hazards: Branches and jumps• Interrupts/exceptions
♦ Issues: • How to detect?• How to minimize the penalty?
A B + C
D A * B
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Copyright UCB & Morgan Kaufmann ECE568/Koren Part.2 .23Adapted from UCB and other sources