Universal Engine Fuel System Controller High Speed Digital Systems Lab Summer 2009/10 Instructor: Mony Orbach Students : Eytan Scemama Zahi Marziano Zahi.

Universal Engine Fuel Universal Engine Fuel System ControllerSystem Controller

High Speed Digital Systems LabHigh Speed Digital Systems Lab

Summer 2009/10Summer 2009/10

Instructor: Mony OrbachInstructor: Mony OrbachStudents : Eytan ScemamaStudents : Eytan Scemama

Zahi MarzianoZahi Marziano

o Introduction:o Backgroundo Goalso Enviroment

o Project Designo Testing

Background

o Every engine has a system to control the fuel injection and ignition spark timing and distribution

o In modern engines there is a need for complex computations in a short response time

o Those systems are designed for a specific engine

o Those systems are based on outdated technologies that do not always provide the required efficiency

Project RequirementsProject Requirementso Introduction to benzine engine functionality o Studying fuel injection and ignition spark timing

algorithmso Designing the engine controllero Learning VHDL and The Quartus environment o VHDL implementation of the design o Simulating the design (Testbench)o Introduction with Altera’s DE/2 evaluation kit

and program the FPGAo Implementation of an interface between the

signal generator and the DE/2 kito Testing The design using signal generator

System FeaturesSystem Featureso Supports a wide range of engine types:

o Different number of cylinderso Different engine sizeso Engines with or without a distributoro Different fuel injector sizes

o Modular – can be easily modifed and upgraded by adding components (sensors, calculation units, tables, etc.)

o Chip based, parallel computations – enabling faster response times (using 100KHz clock)

o Higher resolution tables with interpolation unit for more accurate results

o Taking into consideration various sensor systems for enhanced engine efficiency (power, fuel consumption, etc.)

Engine CycleEngine Cycle

The Engine Cycle:The Engine Cycle:

1.1. IntakeIntake

2.2. CompressionCompression

3.3. Combustion (Work) Combustion (Work)

4.4. Exhaust Exhaust

Fuel And Spark TimingFuel And Spark Timing

TDCCYL#1 - work

CYL#2 - exhaust

CYL#3 - injection

CYL#4 – compression

PulseWidthCalcUnit

SparkAdvanceCalcUnit

STATEMACHINE

Sensors SparkPulse

FuelInjectionPulses

CylinderSelect[0..N]

Crank Unit

RPM

RPM

RPM

First State ID

Pulse Width

Spark Advance

Top Level ViewTop Level View

Fuel CalculationFuel Calculation

Pulse Width Calculation

AFR Table

Required Fuel Calculation

RPM

MAP Sensor

Air DensityCalculator

Air Temp Sensor

Cylinder Displacement

Cylinders Number

Injector Flow Rate

Interpolation

VE Table Interpolation

Gamma Enrich Calculation

Injector Open Time

AccelerationCalculator

Throttle Position Sensor Acceleration Enrichment

TableInterpolation

O2 Loop Table

Interpolation

Warmup Table

InterpolationCLT Sensor

O2 Sensor

Air Correction

Barometric Correction

PW

Pulse Divide

Converter

Converter

Converter

Converter

Converter

Ignition Advance Ignition Advance CalculationCalculation

Total Advance Calculation

Ignition Table

Cold Advance Table

Interpolation

Advance Offset

Interpolation

RPM

MAP Sensor

adv_degign_table

cold_adv_deg

adv_offset

CLT Sensor

Converter

Converter

Converter

Crank SensorCrank Sensor

oFuncionality:Funcionality:o Identify the first cylinderIdentify the first cylindero Calculate RPM and cycle timeCalculate RPM and cycle time

oComponents:Components:o Filter – 8 samples including derivativeFilter – 8 samples including derivativeo First cylider ID – compares 3 time deltasFirst cylider ID – compares 3 time deltaso Cycle time – calculate time between 1Cycle time – calculate time between 1stst

cylinder ID eventscylinder ID eventso Calculate RPM – using the calculated Calculate RPM – using the calculated

cycle timecycle time

Arithmetic UnitsArithmetic UnitsoCalculated using fixed pointCalculated using fixed point

oAltera’s MegaWizard functions - for Altera’s MegaWizard functions - for optimized efficiency optimized efficiency

oNew results ready every clock cycle New results ready every clock cycle (100KHz)(100KHz)

oResults are sampled by the state machine Results are sampled by the state machine every engine cycle (approx. 10 ms)every engine cycle (approx. 10 ms)

oIf needed, the calculations can be If needed, the calculations can be accelerated (using faster clock)accelerated (using faster clock)

oIf needed, the calculations can be more If needed, the calculations can be more accurate (shifting the floating point position)accurate (shifting the floating point position)

Memory TablesMemory Tables

o Tables content calculated off-line

o Resolution X3 from known tables

o Address pointer calculated from A/D input (linear conversion between values)

o Outputs are calculated using interpolation from 4 neighbor cells

State MachineState Machineo Wakes up at idle state

o Begins cycle after receiving two sequential signals from the crank unit

o The states describe the different positions of the flywheel

o Flywheel positions define which cylinder receive the spark and which one receives the fuel injection

o Handles engines with/without distributor

o Different state machine for engine family

Testing Environment

o Design implemented on DE/2 programmable chip

o Using signal generator to produce inputs

o Physical interface – two GPIO plugs on the DE/2 board (72 available pins)

o Pins functionality:o 8 pins for outputo 8x8 pins for A/D inputs simulation

Time Table(1)o 23/09/09:

o Study benzine engine functionality - Completedo study fuel injection and ignition spark timing

algorithms - Completedo Designing the engine controller - Completedo Learning VHDL and The Quartus environment –

Completedo VHDL implementation of the design – 81.6%

Completedo Simulating the design (Testbench) – every unit

tested separatelyo Introduction with Altera’s DE/2 evaluation kit and

program the FPGA – completed

Time Table(2)

o 27/09/09 - Finish the VHDL implementation

o 24/10/09 - Simulate the whole code + debugging – one week duration

o 1/11/09 - Implementation of an interface between the signal generator and the DE/2 kit – one week duration

o 10/11/09 - Testing The design using signal generator – one week duration