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UNIT -3GENERICS AND
CONFIGURATIONSSUBPROGRAMS AND
PACKAGES
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GENERICS AND CONFIGURATIONS
Genericsuseful to pass certain types of information into a designdescription from its environment
. Examples - rise and fall delays, size of interface ports
example of a generic N-input and gate isentity AND_GATE isgeneric (N: NATURAL);port (A: in BIT_VECTOR(1 to N); Z: out BIT);
end AND_GATE;architecture GENERIC_EX of AND_GATE isbeginprocess (A)
variable AND_OUT: BIT;begin
AND_OUT := '1';for K in 1 to N loop
AND_OUT := AND_OUT and A(K);end loop;Z
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the size of the input port has been modeled as a generic
value may be specified in the entity declaration for an entity
entity NAND_GATE isgeneric (M: INTEGER := 2); -- M models the number of inputs.port (A: in BIT_VECTOR(M downto 1); Z: out BIT);end NAND_GATE;
Two other alternate ways - in a component declaration and in a component
instantiation .
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Why Configurations?
1. used to bind an architecture body to its entity declaration.
specify multiple views for a single entity. use any one for simulation
2. used to bind a component with an entity
For example, a declaration for a component used in a design may be
component OR2port (A, B: in BIT; Z: out BIT);end component;
and the entities that the above component may possibly be bound toare
entity OR_GENERIC isport (N: out BIT; L, M: in BIT):end OR_GENERIC;
entity OR_HS isport (X, Y: in BIT; Z: out BIT);
end OR_HS;
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Default Configurations
used for models that do not contain any blocks or components toconfigure. specifies
the configuration namethe entity being configuredthe architecture to be used for the entity
Syntax :-
Configurationconfig_nameofentity_nameisforarchitecture_nameend for;Endconfig_name;
Example two default configurations shown by configurations
big_countand small_count:
LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;ENTITY counter ISPORT(load, clear, clk : IN std_logic;
data_in : IN INTEGER;data_out : OUT INTEGER);
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ARCHITECTURE count_255 OF counter ISBEGIN
PROCESS(clk)VARIABLE count : INTEGER := 0;BEGIN
IF clear = 1 THENcount := 0;ELSIF load = 1 THEN
count := data_in;ELSE
IF (clkEVENT) AND (clk = 1) AND
(clkLAST_VALUE = 0) THENIF (count = 255) THENcount := 0;
ELSEcount := count + 1;
END IF;END IF;
END IF;data_out
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ARCHITECTURE count_64k OF counter ISBEGIN
PROCESS(clk)VARIABLE count : INTEGER := 0;
BEGIN
IF clear = 1 THENcount := 0;ELSIF load = 1 THEN
count := data_in;ELSE
IF (clkEVENT) AND (clk = 1) AND
(clkLAST_VALUE = 0) THENIF (count = 65535) THENcount := 0;
ELSEcount := count + 1;
END IF;END IF;
END IF;data_out
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CONFIGURATION small_count OF counter ISFOR count_255END FOR;
END small_count;
CONFIGURATION big_count OF counter ISFOR count_64kEND FOR;
END big_count;
This example shows how two different architectures for a counterentity can be configured using two default configurations
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Component Configurations architectures that contain instantiated components are configured
example - simple 2 to 4 decoder
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Two different styles can be used for writing a component configurationfor an entity.
Lower-Level Configurations
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Entity-Architecture Pair Configuration
i i fi i
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Generics in Configurationsspecifies a timing mode to run the simulation in the decoderexample
G i V l S ifi i i A hi
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Generic Value Specification in Architecture
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Bl k C fi ti
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Block Configurations
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Configuration cpu_con of cpu is
For fragment
For reg_array
For all : int_reg use entitywork.int_reg(behave);
End for;
End for;
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ArchitectureConfigurations
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SUBPROGRAMS AND PACKAGES
Subprogram a sequential algorithm that performs a certain computation andexecutes in zero simulation time
typical format for a subprogram body is
subprogram-specification issubprogram-item-declarationsbegin
subprogram-statements -- Same as sequential-statements.end [ subprogram-name ];
There are two kinds of subprograms:1. Functions2. Procedures
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Functions
used to describe frequently used sequential algorithms that return a single value
general syntax function-name (parameter-list)returnreturn-type
Ex :-function LARGEST (TOTAL_NO: INTEGER; SET: PATTERN)return REAL is
-- PATTERN is defined to be atype of 1-D array of-- floating-point values, elsewhere.variable RETURN_VALUE: REAL := 0.0;beginfor K in 1 to TOTAL_NO loopifSET(K) > RETURN_VALUE thenRETURN_VALUE := SET(K);
end if;end loop;return RETURN_VALUE;end LARGEST;
Procedures
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Procedures
allow decomposition of large behaviors into modular sections
syntaxprocedureprocedure-name (parameter-list )
example - It describes the behavior of an arithmetic logic unit.
type OP_CODE is (ADD, SUB, MUL, DIV, LT, LE, EQ);. . .procedure ARITH_UNIT (A, B: in INTEGER; OP: in OP_CODE;Z: out INTEGER; ZCOMP: out BOOLEAN) is
begincase OP iswhen ADD=>Z:=A+B;when SUB=>Z:=A-B;when MUL=>Z:=A*B;when DIV => Z := A/B;when LT => ZCOMP := A < B;
when LE => ZCOMP := A ZCOMP := A = B;end case;end ARITH_UNIT;
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Declarations
describes the interface for the subprogram.
Two examples of procedure and function declarations are.procedure ARITH_UNIT (A, B: in INTEGER; OP: in OP_CODE;
Z: out INTEGER; ZCOMP; out BOOLEAN);
function VRISE (signal CLOCK_NAME: BIT) return BOOLEAN;
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Package Declaration
syntax of a package declaration is
packagepackage-nameispackage-item-declarations "> These may be:- subprogram declarations ~ type declarations- subtype declarations- constant declarations- signal declarations- file declarations- alias declarations- component declarations- attribute declarations- attribute specifications- disconnection specifications- use clauses
end [package-name ] ;
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An example of a package declaration is.
package SYNTH_PACKisconstant LOW2HIGH: TIME := 20ns:type ALU_OP is (ADD, SUB, MUL, DIV, EQL);
attribute PIPELINE: BOOLEAN;type MVL is ('U', '0', '1', 'Z');type MVL_VECTOR is array (NATURAL range ) of MVL;subtype MY_ALU_OP is ALU_OP range ADD to DIV;component NAND2port (A, B: in MVL; C: out MVL);
end component;end SYNTH_PACK;
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Package Body
contains the behavior of the subprograms and the values of thedeferred constants declared in a package declaration. I may contain other declarations syntax
package bodypackage-nameispackage-body-item-daclarations "> These are:
- subprogram bodies -- complete constant declarations- subprogram declarations- type and subtype declarations- file and alias declarations- use clausesend [package-name ];
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Consider the following package declaration.
use WORK.SYNTH_PACK.all:package PROGRAM_PACK isconstant PROP_DELAY: TIME; -A deferred constant.function"and" (L, R: MVL) return MVL;procedure LOAD (signal ARRAY_NAME: inout MVL_VECTOR;START_BIT, STOP_BIT, INT_VALUE: in INTEGER);end PROGRAM_PACK;
Package body ispackage body PROGRAM_PACKisconstant PROP_DELAY: TIME := 15ns;
function "and" (L, R: MVL) return MVL isbegin
return TABLE_AND(L, R);end "and";
procedure LOAD (signal ARRAY_NAME: inout MVL_VECTOR;
START_BIT, STOP_BIT, INT_VALUE: in INTEGER) is-- Local declarations here.begin-- Procedure behavior here.end LOAD;
end PROGRAM_PACK;
Use Clause
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Use Clause
There are two main forms of the use clause.uselibrary-name. primafy-unit-name ; --Form 1.uselibrary-name. primafy-unit-name. Item ; --Form 2
The first form of the use clause allows the specified primary unit name from thespecified design library to be referenced in a design description. For example,
Library CMOS;use CMOS.NOR2;configuration.... . . use entity NOR2( . . . );
end;
The second form of the use clause makes the item declared in the primary unitvisible and the item can, therefore, be referenced within the following design unit.For example,
library ATTLIB;
use ATTLIB.SYNTH_PACK.MVL;-- MVL is a type declared in SYNTH_PACK package.-- The package, SYNTH_PACK, is stored in the ATTLIB design library.entity NAND2 isport (A, B: in MVL; ...)...
Predefined package standard
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Predefined package standard
contains the definitions for the predefined types and functions of thelanguage. A source code listing of this package follows.
package STANDARD is-- Predefined enumeration types:type BOOLEAN is (FALSE, TRUE);type BIT is ('0', '1');type CHARACTER is (NUL, SOH, STX, ETX, EOT, ENQ, ACK,
BEL, BS, HT, LF, VT, FF, CR,SO, SI, DLE, DCI, DC2, DC3, DC4,NAK, SYN, ETB, CAN, EM, SUB, ESC,FSP, GSP, RSP, USP,' ' , ' ! ', ' ', ' # ', ' $ ', ' % ', ' & ',
' ', ' (' , ' ) ', ' * ', ' + ', ' , ', ' - ',' . ', ' / ', ' 0 ', ' 1 ', ' 2 ', ' 3 ', ' 4 ',' 5 ', ' 6 ', ' 7 ', ' 8 ', ' 9', ' : ', ' ; ',' < ', ' = ', ' > ', ' ? ',
' @ ' ' A ' ' B ' ' C ' ' D ' ' E ' ' F '
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@ , A , B , C , D , E , F ,' G ', ' H ', ' I ', ' J ', ' K ', ' L ', ' M ',' N ', ' O ', ' P ', ' Q ', ' R ', ' S ', ' T ',' U ', ' V ', ' W ', ' X ', ' Y ', ' Z ', ' [ ',' \ ', ' ] ', ' ', ' _ ',
' ` ', ' a ', ' b ', ' c ', ' d ', ' e ', ' f ',' g ', ' h ', ' i ', ' j ', ' k ', ' l ', ' m ',' n ', ' o ', ' p ', ' q ', ' r ', ' s ', ' t ',' u ', ' v ', ' w ', ' x ', ' y ', ' z ', ' { ',' | ', ' } ', ' ~ ', DEL);
type SEVERITY_LEVEL is (NOTE, WARNING,ERROR, FAILURE);
-- Predefined numeric types:type INTEGER is rangeimplementation_defined;type REAL is rangeimplementation_defined;
- Predefined type TIME:
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Predefined type TIME:type TIME is rangeimplementation_definedunitsfs; -- femtosecondps = 1000 fs; -- picosecondns = 1000 ps; -- nanosecondus = 1000 ns; -- microsecondms = 1000 us; -- microsecondsec = 1000 ms; -- secondsmin = 60 sees; -- minuteshr = 60 min; -- hoursend units;-- Function that returns the current simulation time:function NOW return TIME;-- Predefined numeric subtypes:subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;- Predefined array types:type STRING is array (POSITIVE range ) ofCHARACTER;type BIT_VECTOR is array (NATURAL range ) ofBIT;end STANDARD;
Design Libraries
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Design Libraries
compiled VHDL description is stored in a design library
design library is an area of storage in the file system of the host environment
Each design library has a logical name with which it is referenced inside a VHDLdescription
A typical compilation process.
Design File
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Design File
ASCII file containing the VHDL sourcecontain one or more design units, where a design unit is one of the following:
entity declaration, architecture body,
configuration declaration, package declaration, package body.
Design units are further classified as1. Primaryunits: allow items to be exported out of the design unit. They are
a. entity declaration: The items declared in an entity declaration are
implicitly visible within the associated architecture bodies.
b.package declaration: Items declared within a package declaration canbe exported to other design units using context clauses.
c. configuration declaration.
2. Secondaryunits: These units do not allow items declared within them to beexported out of the design unit, that is, these items cannot be referenced in otherdesign units. These are
a. architecture body: A signal declared in an architecture body, for example,cannot be referenced in other design units.
b package body