Unit 7 Unit 7 Multi-Level Gate Multi-Level Gate Circuits / Circuits / NAND and NOR Gates NAND and NOR Gates Ku-Yaw Chang Ku-Yaw Chang [email protected][email protected]Assistant Professor, Department of Assistant Professor, Department of Computer Science and Information Engineering Computer Science and Information Engineering Da-Yeh University Da-Yeh University
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Unit 7 Multi-Level Gate Circuits / NAND and NOR Gates
Unit 7 Multi-Level Gate Circuits / NAND and NOR Gates. Ku-Yaw Chang [email protected] Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University. Objectives. - PowerPoint PPT Presentation
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Unit 7Unit 7Multi-Level Gate Circuits / Multi-Level Gate Circuits /
Assistant Professor, Department of Assistant Professor, Department of Computer Science and Information EngineeringComputer Science and Information Engineering
Da-Yeh UniversityDa-Yeh University
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ObjectivesObjectives
Design a minimal two-level or multi-level Design a minimal two-level or multi-level circuit of AND and OR gates to realize a circuit of AND and OR gates to realize a given function.given function.
Design or analyze a two-level gate circuit Design or analyze a two-level gate circuit using any one of the eight basic forms.using any one of the eight basic forms.
Design or analyze a multi-level NAND-Design or analyze a multi-level NAND-gate or NOR-gate circuit.gate or NOR-gate circuit.
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ObjectivesObjectives
Convert circuits of AND and OR gates to Convert circuits of AND and OR gates to circuits of NAND gates or NOR gates, and circuits of NAND gates or NOR gates, and conversely, by adding or deleting inversion conversely, by adding or deleting inversion bubbles.bubbles.
Design a minimal two-level, multiple-Design a minimal two-level, multiple-output AND-OR, OR-AND, NAND-NAND, output AND-OR, OR-AND, NAND-NAND, or NAND-NOR circuit using Karnaugh or NAND-NOR circuit using Karnaugh maps.maps.
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OutlineOutline
7.1 Multi-Level Gate Circuits7.1 Multi-Level Gate Circuits7.27.2 NAND and NOR GatesNAND and NOR Gates7.37.3 Design of Two-Level Circuits Using NANDDesign of Two-Level Circuits Using NAND and NOR Gates and NOR Gates7.47.4 Design of Multi-Level NAND and NOR GateDesign of Multi-Level NAND and NOR Gate Circuits Circuits7.57.5 Circuit Conversion Using Alternative GateCircuit Conversion Using Alternative Gate Symbols Symbols7.67.6 Design of Two-Level, Multiple-OutputDesign of Two-Level, Multiple-Output Circuits Circuits7.77.7 Multiple-Output NAND and NOR CircuitsMultiple-Output NAND and NOR Circuits
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LevelLevel Maximum number of gates cascaded in series Maximum number of gates cascaded in series
between a circuit input and the outputbetween a circuit input and the output
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Four-Level Realization of ZFour-Level Realization of Z
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TerminologyTerminology
AND-OR circuitAND-OR circuit A two-level circuit composed of a level of AND A two-level circuit composed of a level of AND
gates followed by an OR gate at the outputgates followed by an OR gate at the output
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TerminologyTerminology
OR-AND circuitOR-AND circuit A two-level circuit composed of a level of OR gates A two-level circuit composed of a level of OR gates
followed by an AND gate at the outputfollowed by an AND gate at the output
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TerminologyTerminology
OR-AND-OR circuitOR-AND-OR circuit A three-level circuit composed of a level of OR A three-level circuit composed of a level of OR
gates followed by a level of AND gates followed by gates followed by a level of AND gates followed by an OR gate at the outputan OR gate at the output
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TerminologyTerminology
Circuit of AND and OR gatesCircuit of AND and OR gates No particular ordering of the gatesNo particular ordering of the gates The output gate may be either AND or OR.The output gate may be either AND or OR.
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Trade-offTrade-off
Number ofNumber of GatesGates Gate inputsGate inputs LevelsLevels
Gate delayGate delay
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Example 7-1Example 7-1
Z = (AB+C) (D+E+FG) + HZ = (AB+C) (D+E+FG) + H
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Example 7-1Example 7-1
Partially multiplying outPartially multiplying out
Z = (AB+C) (D+E+FG) + HZ = (AB+C) (D+E+FG) + H
= (AB+C) [ = (AB+C) [(D+E)(D+E)+FG] + H+FG] + H
= = AB(D+E) + C(D+E) + ABFG + CFGAB(D+E) + C(D+E) + ABFG + CFG + H + H
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Example 7-1Example 7-1
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Example 7-1Example 7-1
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ProblemProblem
Find a circuit of AND and OR gates to Find a circuit of AND and OR gates to realizerealize
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SolutionSolution
This leads directly to a two-level AND-OR gate This leads directly to a two-level AND-OR gate circuit f = a’c’d + bc’d + bcd’ + acd’circuit f = a’c’d + bc’d + bcd’ + acd’
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SolutionSolution
FactoringFactoring
f = a’c’d + bc’d + bcd’ + acd’ f = a’c’d + bc’d + bcd’ + acd’
yieldsyields
f = c’d (a’ + b) + cd’(a + b) f = c’d (a’ + b) + cd’(a + b)
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SolutionSolution
This leads directly to a three-level OR-AND-OR This leads directly to a three-level OR-AND-OR gate circuitgate circuit
f = c’d (a’ + b) + cd’(a + b)f = c’d (a’ + b) + cd’(a + b)
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SolutionSolution
Both solutions have an OR gate at the Both solutions have an OR gate at the outputoutput Sum of productsSum of products Using 1s on the Karnaugh mapUsing 1s on the Karnaugh map
How about having an AND gate at the How about having an AND gate at the output?output? Product of sumsProduct of sums Using 0s on the Karnaugh mapUsing 0s on the Karnaugh map
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SolutionSolution
Secondly, simplify f by using a Karnaugh mapSecondly, simplify f by using a Karnaugh map(considering 0s)(considering 0s)
f’ = c’d’ + ab’c’ +f’ = c’d’ + ab’c’ + cd + a’b’c cd + a’b’c