UNIT-5(DMA)

Prepared by: Mrs SARIKA NATRAJ

MICRO-PROCESSOR

UNIT-5DMA & 8237 Controller

Mrs. SARIKA SACHDEVA

10/1/2010

DMA

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Direct Memory Access and DMA-controlled I/O

DMA(DIRECT MEMORY ACCESS) This technique allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit..DMA Controller “ A DMA controller is a device usually peripheral to processor that is programmed to perform sequence of data transfers on behalf of the CPU ”.A DMA controller can directly access memory and is used to transfer data from

1. One memory location to another2. An I/O device to memory3. Memory to I/0 device.

Basic DMA operationA DMA controller manages several DMA channels ,each of which is programmed by processor to perform a sequence of these DMA transfers.Each channel consists of some internal registers as

(i) Source & destination address register(Base address & current address)(ii) Transfer count register(Base word count & current word count)(iii) Control & status register

DMA controller works in two modeA) Slave mode(idle cycle)B) Master mode(Active cycle)

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When DMA does not operate

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When DMA operates

Slave mode (idle cycle): In slave mode, DMA controller is accessed by the CPU,which

programs the DMA controller’s internal registers to set up DMA transfers.

When the DMA controller sees a DMA request DREQ signal, it sends the bus request (HRQ or HOLD) signal to the processor.

The HOLD input has a higher priority than the INTR or NMI interrupt inputs

Processor completes the current bus cycle and then sends the BUS grant signal(HLDA) to the DMA controller, indicating that processor has release its control over system bus and has connected DMA controller to the buses.

Master mode(Active cycle): In Bus Master mode, the DMA controller acquires system bus from

the CPU to perform DMA transfer.This process sometimes referred to as CYCLE STEALING mode.

Once DMA has acquired control over system bus, it asserts an acknowledgement (DACK) signal to the I/O device requesting for DMA service .

Once requesting peripheral gets acknowledgment, Data to be transferred is uploaded on data bus by peripheral.

In this way, A DMA controller temporarily borrows the address bus , data bus, and control bus from the microprocessor and transfers thedata bytes directly between an I/O port and a series of memory locations. Whereas Processor can continue to work on any task which does not require bus access.

Once DMA operations have been completed, the controller release the bus by asserting the bus release signal to processor.

Processor acknowledge the bus release signal & resumes its bus cycles from the point it left off.

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The 8237 DMA controller

The 8237 direct memory access controller is designed to improve the data transfer rate in systems.

Features:

The 8237 is a four-channel device that is compatible to the 8086/8088 microprocessors.

can be expanded to include any number of DMA channel inputs. Each channel is capable of addressing a full 64K-byte section of memory

and can transfer up to 64K bytes with a single programming. Memory to Memory transfer End of process (EOP) i/p for terminating transfers. Independent auto-initialization of all channels. Address increment or decrement Enable/disable control of DMA requests.

Functional Description:

8237 contains three basic blocks of control logic:-

1. Timing control Block2. Program command control block3. Priority encoder block

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1. Timing control Block: This block generates internal timing & external control signals for 8237. This block derives internal timing from the clock i/p.

2. Program control block: This block decodes various commands given to 8237 by the processor prior to servicing a DMA request.It also decodes the mode control word used to select the type of DMA (DMA read ,write ,verify) during the servicing.

3. Priority Encoder block: This block resolves the priority contention between DMA channels requesting service simultaneously.

Operation of 8237: The 8237 is designed to operate in two major cycles as

a) Idle cycle b) Active cycle

a) Idle Cycle: In this cycle, 8237 will sample the DREQ line to determine if any channel is requesting a DMA service. The device will also sample chip select signal( CS ) .

If CS is low & HLDA is also low ,then 8237 controller enters in the program condition.

The CPU can now change or inspect internal parts of DMA controller by reading from or writing to the internal registers.

Address lines Ao-A3 are the inputs to device & select which register will be read or written.

IOR & IOW are used to select read & write operations. Due to number & size of internal register , an internal flip-flop is

used to generate an additional bit of address.b) Active Cycle: When the 8237 is in Idle cycle & a non-masked channels

are requested for DMA service by external peripheral via DREQ signal , the 8237 will o/p an HRQ(HOLD) signal to the processor .Processor completes the currents bus cycle and then loose control over buses and gives control to 8237 ,which is indicated by high HLDA signal.Hence DMA enters in the Active cycle.In this cycle, DMA service will take place in one of the four modes(discussed in later section):i) Single transfer mode

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ii) Block transfer modeiii) Demand transfer modeiv) Cascade transfer mode

In DMA active cycle, there can be three transfer types as a. DMA read cycle: In this transfer type, data moves from

memory to I/O device by activating MEMR & IOW operation.

b. DMA write cycle: In this transfer type, data moves from I/O device to memory by activating MEMW & IOR operation.

c. DMA verify cycle: In this cycle , data is not transferred b/w memory & I/O device. It is used by the peripheral device to verify the data that has been recently transferred.Verify mode is not permitted during memory to memory operation.

When the data transfer is completed , the 8237 removes the HOLD request signal to processor & release bus by generating TC signal indicated by low EOP pin.

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8237 PIN description:

DREQo-DREQ3(DMA request): Used by peripheral to request a DMA transfer for a particular DMA channel.

DACK0- DACK3(DMA channel acknowledge): It is used to notify the requesting peripheral has been granted for DMA cycle.

HRQ (Hold request): This output pin is used by 8237 to request processor to get control over system bus .

HLDA (Hold acknowledge) : This active high Signal is for indicating the 8237 controller that the microprocessor has relinquished control of the address, data and control buses.

AEN (Address enable): Enables the DMA address latch connected to the 8237 and disable any buffers in the system connected to the Microprocessor. (Use to take the control of the address bus from the μP).

ADSTB (Address strobe): Functions as ALE to latch address during the DMA transfer.

EOP (End of process): This is bi-directional active low pin. This pin goes low automatically, when data transfer is complete (works as o/p strobe). This Pin also allows an external low signal to terminate an active DMA service (works as an i/p strobe).

IOR (I/O read): In slave mode, used as an input strobe to read contents of 8237 internal registers by CPU and In master mode, used as an output strobe to read data from the I/O device.

IOW (I/O write): In slave mode , used as an input strobe to write data to the 8237 and In master made, used as an output strobe to write data to the port during a DMA read cycle.

MEMW (Memory write): It is used as an output strobe by 8237 to write data in the selected memory location during a DMA write cycle.

MEMR (Memory read): It is used as an output strobe by 8237 to read data from the selected memory location during a DMA read cycle or memory to memory transfer operation.

READY: This signal is ignored in slave mode.Whereas in Master mode, this signal can be used to extend the memory read & write pulses from the 8237 to accommodate slow memory or I/O device.

CS(Chip Select): In slave mode, this signal is generated by address decoder to select chip. This signal allows communication b/w CPU & 8237.In Master mode, this signal is ignored.

CLK (clock input) :In slave mode, this signal is ignored.

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Whereas, In master mode, this signal controls all internal & external DMA operations.

RESET: This is an active high signal which clears the command, status, request, and temporary registers, the mode register counter.

Following a RESET, the controller is in an idle cycle. A0-A3 (Address bidirectional): The four least significant address lines

are bi-directional. In Idle cycle, these act as inputs & are used by 8237 to address the control registers to be loaded or read.In active cycle, these act as o/p & provide 4-bits of address.

A4-A7(Address): These four MSB address lines are o/ps & provides four bits of address. These lines are enabled during DMA service.

DB0 – DB7(DATA bus): These are bidirectional & connected to the system data bus. In slave mode, these lines are used to transfer data between CPU & 8237’s internal registers. In master mode, the most significant 8-bits of address are o/p onto the data bus to be strobed into an external latch by ADSTB.

NC (Not connected):This pin is not connected & should not be tested for continuity.

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8237 Internal registers

1. Current address register: Each channel has CAR which is used to hold the 16-bit memory address used for the DMA transfer.

The address is automatically incremented or decremented after each transfer.The register is written or read by the processor in successive 8-bits. It mayalso be reinitialized back to its original value by an auto-initialization featureof 8237.

2. Current Word register: Each channel has a 16-bit current word count register. This register determines the number of transfers to be performed. The word count is decremented after each transfer. When the value in the register goes from 0000H to FFFF H, a TC(terminal count) will be generated.

3. Base address & Base word count register: Each channel has a pair of base address & base word count register. These 16-bit register store the original value of their associated current registers. During auto-initialization these values are used to restore the current registers to their original values.

4. Command Registers: This 8-bit register controls the operation of 8237.It is programmed by the processor in program condition & is cleared by RESET or Master CLEAR instruction.

5. Mode Register: This register programs the mode of operation for a channel.

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6. Request Register: This is used to request a DMA transfer via software, which is very useful in memory-to-memory transfers.

Each channel has a request bit associated with it in the request register.

Each register bit is set or reset separately under software control or is cleared upon generation of a TC or external EOP signal. Entire register is cleared by a RESET.

7. Mask Register: Each channel has associated with it a mask bit, which can be set to disable incoming DREQ. Each mask bit is set when its associated channel produces an EOP.

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Each bit of 4-bit mask register may also be set or cleared separately under software control.

8. Status Register: The status register is available to be read out of the 8237 by the processor. It contains information about the status of the device at this point.This information includes which channel have reached a terminal count & which channels have pending DMA requests.

Bit 0-3 are set every time , a TC is reached by the channel or an external EOP is applied.

Bit 4-7 are set whenever their corresponding channel is requesting for service.

9. Temporary Register: Temporary register is used to hold data during memory to memory transfer. After the completion of transfer, the last word moved can be read by the processor in the program condition.“The temporary register always contains the last byte transferred in the previous memory to memory operation, unless cleared by RESET.

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DMA TRANSFER MODES:

i) Single transfer mode: In this mode ,the device is programmed to make one transfer only. The word count register will be decremented & rolls over from 0000 H to FFFF h, a TC will cause an auto-initialilize if the channel has been programmed to do so.

ii) Block transfer mode: In block transfer mode ,device can make number of transfers as programmed in word count register. The DMA transfer is continued until a TC ,caused by word count going from 0000 H to FFFF h, or an external EOP is encountered.This mode is used when 8237 needs to transfer a block of data.

iii) Demand transfer mode: In this mode, device is programmed to continue making transfers until a TC or an external EOP is encountered or until DREQ goes inactive. Thus ,transfer may continue until the I/O device has exhausted its data capacity.

iv) Cascade transfer mode: This mode is used to cascade more than one 8237 together for simple system expansion.The HRQ & HLDA signals from additional 8237 are connected to the DREQ & DACK signals of a channel of initial 8237 IC.

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8237 TRANSFER TYPES OR Operating modes:

1. Memory to Memory operation: To perform block moves of data from one memory address space to another address space with a minimum of program effort & time , the 8237 includes a memory to memory transfer feature.

Programming a bit in the command register selects channel 0 and 1 to operate as memory to memory transfer channels.

The transfer is initiated by setting the software DREQ for channel 0.

The channel 0 current address register is source for the address used & is decremented in the normal manner.

The data byte read from memory is stored in the 8237 internal temporary register.

The channel 1 writes data from the temporary register to memory using address in its current address register.

The channel 1 current word count is decremented. When the word count of channel 1 goes to FFFF H , a TC is

generated causing an EOP o/p terminating the service.2. Priority:

a) Fixed priority: It fixes the channels in priority order based upon the descending value of their number. Channel 0 has been assigned with highest priority whereas Channel 3 has been assigned with lowest priority.

b) Rotating priority: With rotating priority, any device requesting DMA service is guaranteed to be recognized after no more than three higher priority services have occurred.This prevents any one channel from monopolizing the system.

3. Auto-initialization: By programming a bit in the mode register, a channel may be set up as an auto-initialize channel.During auto-initialization, the original values of the current address & current word count register are automatically restored from the base address & base word count register of that channel following EOP. The mask bit is zero, when the channel is auto-initialized.Following auto-initialization, the channel is ready to perform another DMA service , without CPU intervention, as soon as a valid DREQ is detected.

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4. Compressed Timing: In order to achieve greater throughput where system characteristics permit, the 8237 can compress the transfer time to two clock cycles.

5. Extended Write Mode: Micro-computer allows use of various types of memory & I/O devices with different access time.If a device cannot be accessed within a specific amount of time, it returns an indication to 8237 that causes 8237 to insert one or more wait states in its internal sequencing.

Software commandsThere are 3 software commands used to control the operation of the 8237.1. Clear the first/last (F/L) flip-flop2. Master clear - Disable all DMA channels3. Clear mask register - Enables all DMA channels

Note:

In Architecture, we are supposed to describe functional description as well as all internal registers.

In description of 8237 in 10-15 marks, we are supposed to describe Features, functional description as well as Operation. As well as draw the pin diagram & architecture.

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UNIT-5(DMA)

Documents

mrs sarika

priority encoder

direct memory

selected memory

base address

word count

active high

current address