Unit 5 assembly language programming

UNIT 5 – Assembly Language Programming

-By

Prof. K. U. Sharma

8086 Input/output & 8255 PPI

Contents:

1. Mapping Schemes

Memory Mapped I/O

I/O Mapped I/O

2. Bus Cycle & Time States

Minimum Mode and Maximum Mode Bus Cycles

3. Intel 8255 PPI

I/O Mode

BSR Mode

4. Programming with 8255

4/1/2014 Prof. K. U. Sharma, PRMCEAM, Contact: [email protected], 9096996329

8086’s I/O:

An i/o addressing capacity of 8086 is of 16-bit, so total i/o’s that can be

addressed by the microprocessor are 216 = 64kb.

In I/O addressing there is no role of segment registers.

An I/O can be mapped in two ways

1. Memory Mapped I/O

2. I/O Mapped I/O


1. Memory Mapped I/O:

Whenever the addresses of I/O’s are inserted in the span of memory, then

the scheme is called memory mapped I/O.

Advantage: There is no need of separate hardware & software to implement

this scheme.

Disadvantage: Due to insertion of I/O’s, memory space is reduced.

Memory I/O

1 MB


2. Memory Mapped I/O:

Whenever I/O’s are treated separately from the span of memory, the

scheme is called I/O mapped I/O or isolated I/O.

Advantage: Full memory space & I/O space is utilized.

Disadvantage: Separate hardware & software is required to implement this

scheme.

Memory

1 MB

I/O

64 KB


Inst Related to the Above Schemes:

Intel 8086 provides the following two inst for implementing his schemes:

1. IN

2. OUT

1. IN:

1. IN PORTADD (8);

Example:

IN AL, 09; (09) (AL)

In the above inst, the 8 bit content of PORTADD is copied to AL register.

Here the address of port is directly given hence this inst involves direct

addressing mode.

4/1/2014

Prof. K. U. Sharma, PRMCEAM, Contact: [email protected], 9096996329

2. IN AX, PORTADD (8);

Example:

IN AX, 09;

(09) (AL) and

(0A) (AH)

This inst follows direct addressing mode.

3. IN AL, [DX];

((DX)) (AL)

In the above inst, the address of 16 bit is indirectly specified through DX

register; the 8 bit contents of that port address will be copied to the AL

register. This inst involves register indirect addressing mode.


4. IN AX, [DX];

((DX)) (AL)

((DX+1)) (AH)

Register Indirect Addressing mode.

2. OUT:

1. OUT PORTADD AL;

Example:

OUT 09, AL; (AL) (09)


2. OUT PORTADD, AX;

Example:

OUT CD, AX; (AL) (CD) and

(AH) (CE)

In the above inst the content of AL register is copied to the content of port

whose address is directly mentioned inside the inst whereas the content of

AH register is copied to (port add + 1).

3. OUT [DX], AL;

(AL) ((DX))

4. OUT [DX], AX;

(AL) ((DX))

(AH) ((DX)+1)

4/1/2014


Intel 8255 (Programmable Peripheral Interface)

Features of 8255:

It is widely used as a programmable peripheral interface, compatible with all

microprocessors.

It has 3 ports, each of 8 bit namely: Port A, Port B and Port C

These ports can be taken in two groups of 12 bits as Group A (GA) and Group B (GB).

Where GA is strict combination of port A + PCU whereas GB is a combination of port B

+ PCL

The 8255 IC can operate in 2 different modes namely

1. Basic I/O mode

2. BSR (bit set reset) mode

Out of these two modes, BSR mode can only work on Pc, whereas Basic I/O mode is

further divided into mode 0, mode 1 and mode 2

Out of these three modes M0 & M1 can operate on GA & GB both whereas M2 can

operate on only GA. 4/1/2014



Control Register Types:

There are 2 types of control registers; one for basic i/o mode and one for BSR

mode.

Depending upon the address lines A0 & A1, the selection of different ports is made

as follows:

Data bus buffer is of 8 bits, which is used to interface with microprocessor for

handling 8 bit data.

The read/write is responsible for read write operations.

The CS signal is generated by the microprocessor using address decoding logic.

A1 A0 Selection

0 0 PA

0 1 PB

1 0 PC

1 1 CWR


CWR for Basic I/O:


Example: Write CWR format for PA as input port, PCL as output port, PCU as

input port and PB as output port with mode 0 .

Answer: 98H



CWR for BSR Mode:

The range defined for BSR is from 0 to 7F and for basic I/O is from 80H to

FF.

Example: Write a BSR CWR value to set PC3 & PC6 of 8255

Answer:

1. 07H

2. 0DH


Modes of Basic I/O:

There are 3 basic types of different i/o modes listed as

1. Mode 0

2. Mode 1

3. Mode 2

MODE 0: (Simple i/o or Basic i/o without Handshaking)

In this mode, any of the port can be used as input or output port depending upon the

bit setting in control register. Also called as default mode.

In this mode, there are no handshakes signals, handshakes signals are those which

are used to check the device status before making the actual data transfer.


MODE 1: (Strobed i/o with Handshakes)

This mode is also called as strobed i/o with unidirectional handshakes, both GA and

GB can operate in this mode either together or individually.

Here each group will use 8 bit for actual data transfer whereas bits of PC are used

for handshake signals.

Case 1: When PA & PB are acting as I/P ports


When PA & PB are operating as input ports, there are various handshake

signals described:

1. STB: The strobe input signal is given by standard input devices, which

when goes low indicates that the data is ready with source device & it is

ready to strobe or load in to respective port.

2. IBF (Input Buffer Full): Once the data is available inside port, this signal

goes high indicating input buffer full.

3. INTR: This is an output signal which is used to interrupt the

microprocessor for requesting it to read the data. Once data is read by the

microprocessor then the IBF signal goes low.


Case 2: When PA & PB are acting as O/P ports

4/1/2014


• When PA & PB is acting as output port then following handshakes signals

are used:

1. INTR: It is an interrupt request made to the microprocessor demanding

for data from microprocessor.

2. OBF: This is an active low output buffer full signal which indicates that

respective port available with the 8-bit data in it.

3. ACK: This is an active low acknowledgment input signal given by the

destination device making sure that the data which is transferred by 8255

is being received by destination.


MODE 2: (Bidirectional strobed I/O with handshake)


• This mode is called as bidirectional strobed I/O with handshake. It is

applicable on GA only.

• In the above figure OBF & ACK are used for output operation & STB and

IBF will be used for input operation.

Problem:

1. Write a program for reading the data from PA & PB. AND this data & put

the ANDING result in PC.


Answer:

Assuming an address of CWR as F6H, hence the addresses of different

ports will F4H, F2H and F0H for port C , B, A respectively.

Defining the CWR = 92H

Mov AL, 92H

OUT F6, AL ; Initializing the CWR

IN AL, F0H ; Reading data from PA

Mov BL, AL

IN AL, F2H ; Reading data from PB

AND AL, BL ;

OUT F4, AL ; Writing the result to PC

HLT


Program:

1. PPI is configured so that PA is an output port, both ports B and C are input ports, and

all three ports are set up for mode 0 operation. Write a program that will input the data

at ports B and C, find the difference (port C) – (port B), and output this difference to

port A.

2. Data are to be read in from two byte wide input ports at addresses AA and A9 and then

output as a word to a word wide output port at address B000. Write a sequence of inst

to perform this i/o operations.

3. What control word must be written into the control register of the 8255 such that port A

is configured for bidirectional operation and port B is set up with mode 1 outputs.

4. Write a sequence of inst that will input the contents of the input port at i/o address B0H

and jump to the beginning of a service routine identified by the label ACTIVE INPUT

if the LSB of the data is 1.


Answers:

1. Assuming the addresses of the ports as

Port A = 30H; Port B = 32H; Port C = 34H

IN AL, 32H ; Reading port B

Mov BL, AL ; Saving the data

IN AL, 34H ; Reading port C

SUB AL, BL ; subtract B from C

OUT 30H, AL ; write to port A


Answers:

2. IN AL, 0AAH ;

Mov AH, AL ;

IN AL, 0A9H ;

Mov DX, 0B000H

OUT DX, AX

HLT

3. CWR = C4H

4/1/2014


Answers:

4. Mov DX, 00B0H ; set port address

IN AL, DX ; receive data

TEST AL, 1 ; test LSB port

JNZ NEXT ; jump to next inst if LSB is 0

JMP ACTIVE INPUT ; jump to this routine when LSB is 1.


Bus Timing

• The 8086/8088 microprocessors use the memory and I/O in periods called

bus cycles.

• Each bus cycle consists of 4 clock cycles.

• Thus for 8086 running at 5MHz it would take 800ns for a complete bus

cycle.

• Each read or write operation takes 1 bus cycles.


Read Timing


31

During T 1 :

The address is placed on the Address/Data

bus.

Control signals M/ IO , ALE and DT/ R

specify memory or I/O, latch the address

onto the address bus and set the direction of

data transfer on data bus.

32

During T 2 :

•8086 issues the RD or WR signal,

DEN , and, for a write, the data.

DEN enables the memory

or I/O device to receive the

data for writes and the 8086

to receive the data for reads.

33

During T 3 :

•This cycle is provided to allow memory to access data.

•READY is sampled at the end of T 2 .

If low, T 3 becomes a wait state.

Otherwise, the data bus is sampled at the end of T 3 .

34

During T 4 :

All bus signals are deactivated, in preparation for next bus cycle.

Data is sampled for reads, writes occur for writes.

35

Write Timing

Unit 5 assembly language programming

Engineering

basic io mode

memory io

ppi io mode bsr mode

simple io

isolated io

al al dx

modes of basic io

dx dx al dx