UNIT-4 PERIPHERAL INTERFACING · (8255 PPI) • PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its outside world such as ADC, DAC, keyboard

UNIT-4 PERIPHERAL INTERFACING

By: ATIFA AQUEEL

Electronics Engg. Section University Women’s Polytechnic, Amu

Programmable Peripheral Interface (8255 PPI)

• PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with its outside world such as ADC, DAC, keyboard etc.

• We can program it according to the given condition. It can be used with almost any microprocessor.

• The block diagram of Intel 8255 PPI is shown in figure. • It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and

PORT C. We can assign different ports as input or output functions. • Port C is further divided into two 4-bit ports i.e. Port C lower (PC3-PC0)

and Port C upper (PC7-PC4). • Port C can work in either BSR (bit set reset) mode or in mode 0 of input-

output mode of 8255. • Port B can work in either mode 0 or in mode 1 of input-output mode. • Port A can work either in mode 0, mode 1 or mode 2 of input-output mode.

Block Diagram (8255 PPI)

• It has two control groups, control group A and control group B. • Control group A consist of port A and port C upper. Control group B

consists of port C lower and port B. • The data bus buffer is used to interface the internal data bus of 8255 to the

system data bus by reading and writing operations • Read/write control logic accepts the input from the address bus and issues

commands to the individual group blocks. also issues appropriate enabling signals to access the required data/control words/status words.

• Depending upon the value if 𝐶𝐶𝐶𝐶, A1 and A0 we can select different ports in different modes as input-output function or BSR. This is done by writing a suitable word in control register (control word D0-D7).

Schematic diagram

𝑪𝑪𝑪𝑪

𝑹𝑹𝑹𝑹

WR

• D7-D0 (Data bus): These are bidirectional, tri-state data bus lines are connected to the system data bus. They are used to transfer data and control word from microprocessor (8085) to 8255 or receive data or status word from 8255 to the 8085.

• PA0-PA7 (Port A): These are 8 Bit bidirectional I/O pins used to send data to output device and to receive data from input device. It functions as an 8 Bit data output latch/buffer when used in output mode and as an 8 Bit data input latch/buffer when used in input mode.

• PB0-PB7 (Port B) : These are 8 Bit bidirectional I/O pins used to send data to output device and to receive data from input device. It functions as an 8 Bit data output latch/buffer when used in output mode and as an 8 Bit data input latch/buffer when used in input mode.

• PC0-PC7 (Port C) : These are 8 bit bidirectional I/O pins divided into two groups PCL (PC3-PC) and PCU (PC7- PC4).these groups can individually transfer data in or out when programmed for simple I/O, and used as handshake signals when programmed for handshake or bidirectional modes.

• 𝑹𝑹𝑹𝑹: When this pin is low, the CPU can read data in the ports or the status word through the data bus buffer.

• 𝑾𝑾𝑹𝑹: When this pin is low, the CPU can write data on the ports or in the control register through the data bus buffer.

• 𝑪𝑪𝑪𝑪: This pin can be enabled for data transfer operation between the CPU and 8255.

• RESET: This pin is used to reset 8255.i.e control register gets cleared and all the ports are set to the input mode.

• A0-A1 (Address bus): The selection of input port and control word register is done by using A0 and A1 pins in conjunction with 𝑅𝑅𝑅𝑅and 𝑊𝑊𝑅𝑅 pins.

Operating Modes Of 8255 • There are two main operational modes of 8255: 1. Input/output mode, 2. Bit set/reset mode (BSR Mode). • Input-Output mode –

If MSB of control word (D7) is 1, PPI works in input-output mode. I/O mode again classified into three types

1. Mode 0, 2. Mode 1, 3. Mode 2.

Mode 0 (Simple Input/Output) • In this mode, the ports can be used for simple input/output operations

without handshaking. • If both port A and B are initialized in mode 0, the two halves of port C can

be either used together as an additional 8-bit port, or they can be used as individual 4-bit ports.

• Since the two halves of port C are independent, they may be used such that one-half is initialized as an input port while the other half is initialized as an output port.

• The mode 0 has following features: • O/p are latched. • I/p are buffered not latched. • Port do not have handshake or interrupt capability.

Mode 1 (Handshake I/O mode or Strobbed I/O mode.)

• In this mode either port A or port B can work as simple input port or simple output port, and port C bits are used for handshake signals before actual data transmission

• In this mode six pins of port C are used for handshaking or as control bits as shown on fig.

• For port B in this mode (irrespective of whether is acting as an input port or output port), PC0, PC1 and PC2 pins function as handshake lines.

• If port A is operated as input, PC3, PC4 and PC5 pins are used as handshake lines.

• The remaining pins of port C i.e. PC6 and PC7can be used either input or output.

• If port A is operated as output, PC3, PC6 and PC7 pins are used as handshake lines.

• The remaining pins of port C i.e. PC4 and PC5 can be used either input or output.

Mode 1: Input Mode 1: Output

Mode 2 (Strobbed bidirectional mode) • Only group A can be initialized in this mode. • Port A can be used for bidirectional handshake data transfer. This means

that data can be input or output on the same eight lines (PA0 - PA7). • Five pins of port C i.e. PC3 - PC7 are used as handshake lines for port A. • The remaining pins of port C (PC0 - PC2) can be used as simple

input/output lines if port B is initialized in mode 0 or handshake for Port B if port B is initialized in mode 1.

PC1 PC2

I/O Modes of 8255

CONTROL WORD • 8255 ports can be programmed to act either as an input port or an output

port. • For programming the ports of 8255 a control word is formed. • Control word is written in control word register which is present within

8255. • No read operation of the control word register is allowed. • The control word bits corresponding to particular port is set or reset

according to the requirements whether it is to be made input or output port. • To program 8255 a user must know how to write the control word.. • The method to write the control word is shown on next slide

Control Word Format in I/O Mode

• This mode is selected when the most significant bit (D7) in the control register is 1.

• It has three modes: • Mode 0: Simple Input/output. • Mode 1 : Handshake or strobbed I/O • Mode 2: Bidirectional I/O

• Bit Set Reset (BSR) mode – This mode is used to set or reset the bits of port C only, and selected when the most significant bit (D7) in the control register is 0. Control register is given below.

• This mode affects only one bit of port C at a time because, as user set the bit, it remains set until and unless user changes it. User needs to load the bit pattern in control register to change the bit.

• The bits in this mode doesn’t affect the functionality of I/O mode.

Control Word Format in BSR Mode

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

Numericals 1. Find the control word for the register arrangement of the ports of

intel 8255 for mode 0 operation. • Port A: Input, Port B: Input, • Port CU: Input, Port CL: Input Solution: 2. Write control word for mode 1 Output. Solution:

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 1 1 0 1 1

Bit No. Control Word Bits = 9BH

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 0 0 1 0 0

Bit No. Control Word Bits = A4H

3. Make control word for the following configuration of the ports of Intel 8255 for mode 1 operation. • PORT A-INPUT • PORT B-OUTPUT • Remaining pins of port C upper- INPUT

4. Write a program to initialize 8255 in the configuration below.(assume address of the CW register as 23H). (1) Port A: output with handshake (2) Port B: input with handshake (3) Port CL: output (4)Port CU: input

PROGRAM: MVI A,AEH ; LOAD CONTROL WORD OUT 23H ; SEND CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 1 1 1 0 X

Bit No. Control Word Bits

D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 0 1 1 1 0

Bit No. Control Word Bits= AEH

8257- DMA CONTROLLER • DMA stands for Direct Memory Access. • It is designed by Intel to transfer data at the fastest rate. • It allows the device to transfer the data directly to/from memory without

any interference of the CPU. • DMA transfer is hardware controlled I/O transfer scheme. • In programmed controlled I/O, status or interrupt driven I/O the speed of

transfer is slow mainly because instructions need to be decoded and then executed for the transfer.

• DMA transfer is software independent and hence much faster. • A device known as DMA controller (DMAC) is responsible for DMA

transfer. • Using a DMA controller, the device requests the CPU to hold its data,

address and control bus, so the device is free to transfer data directly to/from the memory.

• The DMA data transfer is initiated only after receiving HLDA signal from the CPU.

Block Diagram 8257-DMA Controller

Features of 8257 • Intel 8257 is a programmable 4-channel DMA controller, so it can be used to

provide DMA to four I/O devices and their request priorities are determined internally.

• Each channel has one 16 bit address register (to store the starting address for the transfer) and one 14 bit count register (to store the number of bytes to be transferred)

• The remaining two msbs of the count register give the type of DMA operation:

• Each channel can transfer data up to 64kb. • Each channel can be programmed independently.

S.No. Bit 15 Bit 14 Type of DMA operation

1 0 0 Verify or Initialize DMA cycle 2 0 1 Write DMA cycle 3 1 0 Read DMA cycle 4 1 1 Invalid (Don’t care)

Features of 8257 • Each channel can independently perform read transfer, write transfer and

verify transfer operations. • It generates MARK signal to the peripheral device that 128 bytes have been

transferred. • DMAC is a 40 pin IC. • The process of data transfer from the peripheral to the memory under the

DMA controller can be classified in two modes i.e. Master mode and Slave mode.

SLAVE MODE: In this mode the DMA controller is treated as a peripheral and performs the following steps: • The microprocessor selects the DMA controller chip through 𝐶𝐶𝐶𝐶 • Microprocessor initializes the DMAC by giving the starting address to the

16 bit address register and number of bytes to be transferred to the 14 bit count register with the help of control signals 𝐼𝐼𝐼𝐼𝑅𝑅 and 𝐼𝐼𝐼𝐼𝑊𝑊.

MASTER MODE: After initialization the 8257 enters in master mode and continuously checking the DMA request from the peripheral and perform the following steps:

• When the I/O device is ready for data transfer, it sends a DMA request signal to the DMAC through DREQ line.

• The DMA in turn sends a request signal to the µP through the HOLD line. • The µP finishes the current machine cycle and releases the system bus

(disconnected from it) and acknowledge the I/O device by sending a signal through HLDA line.

• After receiving the HLDA signal the DMA controller acknowledge the I/O device by sending a low signal on 𝑅𝑅𝐷𝐷𝐶𝐶𝐷𝐷. In the mean time the 8257 make use of AEN and ADSTB signals to take control over buses. After that the DMA transfer begins.

• After every byte is transferred, the address register is incremented and the count register decremented.

• This continues till the count reaches zero (Terminal Count=1). Now the DMA transfer is completed.

• At the end of the transfer, the system bus is released by the DMAC by making the HOLD=0. Then µP takes control over the system buses and continues its operation.

8257 Pin Description • DRQ0−DRQ3: These are the four individual channel DMA request inputs,

which are used by the peripheral devices for using DMA services. • DACK0 − DACK3: These are the active-low DMA acknowledge lines,

which updates the requesting peripheral about the status of their request by the CPU.

• Do − D7: These are bidirectional, data lines which are used to interface the system bus with the internal data bus of DMA controller.

• IOR: It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal registers of 8257 in the Slave mode. In the master mode, it is used to read data from the peripheral devices during a memory write cycle.

• IOW: It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master mode, it is used to load the data to the peripheral devices during DMA memory read cycle.

• CLK: It is a clock frequency signal which is required for the internal operation of 8257

• RESET: This signal is used to RESET the DMA controller by disabling all the DMA channels.

• Ao - A3: These are the four least significant address lines. In the slave mode, they act as an input, which selects one of the registers to be read or written. In the master mode, they are the four least significant memory address output lines generated by 8257.

• CS: It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from 8257. In the master mode, it disables the read/write operations to/from 8257.

• A4 - A7: These are the higher nibble of the lower byte address generated by DMA in the master mode.

• READY: It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.

• HRQ: This signal is used to receive the hold request signal from the output device. In the slave mode, it is connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the CPU.

• HLDA: It is the hold acknowledgement signal which indicates the DMA controller that the bus has been granted to the requesting peripheral by the CPU when it is set to 1.

• MEMR: It is the low memory read signal, which is used to read the data from the addressed memory locations during DMA read cycles.

• MEMW: It is the active-low three state signal which is used to write the data to the addressed memory location during DMA write operation.

• ADSTB: This signal is used to convert the higher byte of the memory address generated by the DMA controller into the latches.

• AEN: This signal is used to disable the address bus/data bus. • TC: It stands for ‘Terminal Count’, which indicates the present DMA cycle

to the present peripheral devices. • MARK: The mark will be activated after each 128 cycles or integral

multiples of it from the beginning. It indicates the current DMA cycle is the 128th cycle since the previous MARK output to the selected peripheral device.

• Vcc: It is the power signal which is required for the operation of the circuit.