Prepared By: U.Rajkanna, AP/EIE Page 1 UNIT – 4 8051 MICROCONTROLLER Architecture - Addressing modes and Instruction Sets – Interrupt structure – Timer –I/O ports – Serial communication. MICROCONTROLLERS VS MICROPROCESSORS MICROPROCESSOR: ❖ A CPU built into a single VLSI chip is called a microprocessor. ❖ It is a general-purpose device and additional external circuitry is added to make it a microcomputer. ❖ The microprocessor contains arithmetic and logic unit (ALU), Instruction decoder and control unit, Instruction register, Program counter (PC), clock circuit (internal or external), reset circuit (internal or external) and registers. ❖ But the microprocessor has no on chip I/O Ports, Timers, Memory etc. ❖ For example, Intel 8085 is an 8-bit microprocessor and Intel 8086/8088 a 16-bit microprocessor. ❖ The block diagram of the Microprocessor is shown in Fig.4.1 MICROCONTROLLER: ❖ A microcontroller is a highly integrated single chip, which consists of on chip CPU (Central Processing Unit), RAM (Random Access Memory), EPROM/PROM/ROM (Erasable Programmable Read Only Memory), I/O (input/output) – serial and parallel, timers, interrupt controller. ❖ For example, Intel 8051 is 8-bit microcontroller and Intel 8096 is 16-bit microcontroller. ❖ The block diagram of Microcontroller is shown in Fig.4.2. Fig.4.1 Block diagram of a Microprocessor Fig.4.2 Block Diagram of a Microcontroller
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UNIT 4 8051 MICROCONTROLLER Interrupt structure Timer ...timers, interrupt controller. For example, Intel 8051 is 8-bit microcontroller and Intel 8096 is 16-bit microcontroller. The
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Solution: We convert the value from hex to binary. From Figure 9-3 we have: (a) TMOD = 00000001, mode 1 of timer 0 is selected. (b) TMOD = 00100000, mode 2 of timer 1 is selected. (c) TMOD = 00010010, mode 2 of timer 0, and mode 1 of timer 1 are
❖ Find the timer’s clock frequency and its period for various 8051-based system,
with the crystal frequency 11.0592 MHz when C/T bit of TMOD is 0.
Solution:
(1/12 )× 11.0529 MHz = 921.6 MHz;
T = 1/921.6 kHz = 1.085 us selected.
❖ Write a program to create square wave of 50% duty cycle (with equal portions high
and low) on the P1.5 bit use Timer 0 to generate the time delay.
BACK: JNB TF1,BACK ;Stay until timer rolls over CLR TR1 ;Stop timer 1 CPL P1.5 ;Complement P1.5 to get Hi, Lo CLR TF1 ;Clear timer flag 1 SJMP AGAIN ;Reload timer
❖ Write a program segment that uses timer 1 in mode 2 to toggle P1.0 once
whenever the counter reaches a count of 100. Assume the timer clock is taken
from external source P3.5 (T1).
The TMOD value is 60H The initialization value to be loaded into TH1 is 256 - 100 = 156 = 9CH
BACK: JNB TF1,BACK ;Keep doing it if TF = 0 CPL P1.0 ;Toggle port bit CLR TF1 ;Clear timer overflow flag SJMP BACK ;Keep doing it
SERIAL COMMUNICATION:
Baud Rate: ❖ The 8051 transfers and receives data serially at many different baud rates. ❖ The baud rate in the 8051 is programmable. ❖ This is done with the help of Timer 1. ❖ The relationship between the crystal frequency and the baud rate is
o For XTAL = 11.0592 MHz, the machine cycle frequency is 921.6kHz o The UART circuitry divides the machine cycle frequency of 921.6kHz by 32 once
more before it is used by Timer 1 to set the baud rate. Therefore it gives 28,800Hz.
o When Timer 1 is used to set the baud rate it must be programmed in mode 2, i.e., 8-bit, auto reload.
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o To get baud rates compatible with the PC, TH1 should be loaded with the values shown in the following table by assuming XTAL=11.0592MHz.
Table 4.8: Baud Rate Value For TH1
Baud Rate TH1 (Decimal) TH1 (Hex)
9600 -3 FD
4800 -6 FA
2400 -12 F4
1200 -24 E8
SBUF Register ❖ SBUF is an 8-bit register used solely for serial communication in the 8051. ❖ For a byte of data to be transferred via the TxD line, it must be placed in the SBUF
register. ❖ Similarly, SBUF holds the byte of data when it is received by the RxD line. ❖ SBUF can be accesed like any other registers in the 8051
MOV SBUF, #‘D’ MOV SBUF, A MOV A, SBUF
❖ The moment a byte is written into SBUF, it is framed with the start and stop bits and transferred serially via the TxD pin
❖ Similarly when the bits are received serially via RxD, the 8051 deframes it by eliminating the start and stop bits, making a byte out of the data received, and then placing it in the SBUF
SCON Register: ❖ The SCON register is an 8-bit register used to program the start bit, stop bit and data
bits of data framing, among other things.
❖ SM0,SM1: o These two bits determines the framing of data by the specifying the number of
bits per character, and the start and stop bits. o They take the following combinations
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Table 4.9: Serial Mode Operation
SM0 SM1
0 0 Serial Mode 0
0 1 Serial Mode 1, 8-bit data,1 start bit, 1 stop bit
1 0 Serial Mode 2
1 1 Serial Mode 3
o Serial Mode 0, 2 and 3 are not commonly used nowadays. o Serial Mode 1 is compatible with the COM port of IBM/PC’s o Serial Mode 1, allows the baud rate to be variable and is set by Timer 1 of the
8051 o In Serial Mode 1, for each character a total of 10 bits are transferred
❖ SM2 o This bit enables the multiprocessing capability of the 8051 by assigning ‘SM2=1’. o If ‘SM2=0’ multiprocessing capability is disabled.
❖ REN: (Receiver Enable) o When the REN bit is high, it allows the 8051 to receive data on the RxD pin o If we want the 8051 to bit transfer and receive the data, REN must be set to 1 o By making REN=0, the receiver is disabled o Instruction to set and Clear REN is
SETB SCON.4 CLR SCON.4
❖ TB8: (Transfer Bit 8) o It is used for serial mode 2 and 3. o If this is not used assign TB8 as 0
❖ RB8 (Receive Bit 8) o In serial mode 1, this bit gets a copy of the stop bit when 8-bit data is received. o This bit is rarely used anymore, it is assigned as 0
❖ TI (Transmit Interrupt) o When 8051 finishes the transfer of the 8-bit character, it raises the TI flag to
indicate that it is ready to transfer another byte. o The TI bit is raised at the beginning of the stop bit.
❖ RI (Receive Interrupt) o When the 8051 receives data serially via RxD, it gets rid of the start and stop bits
and places the byte in the SBUF register. o Then it raises the RI flag bit to indicate that a byte has been received and should
be picked up before it is lost. o RI is raised halfway through the stop bit.
Program to Transfer Data Serially: 1. The TMOD register is loaded with the value 20H, indicating the use of Timer 1 in
mode 2 to set baud rate 2. The TH1 is loaded with the value to set the baud rate for serial data transfer 3. The SCON register is loaded with the value 50H, indicating Serial Mode 1 4. TR1 is set to start Timer 1 5. TI is cleared by the ‘CLR TI’ instruction 6. The character byte to be transferred serially is written into the SBUF register 7. The TI flag bit is monitored with the instruction ‘JNB TI, XX’ 8. To Transfer next character goto Step 5
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Program to Receive Data Serially: 1. The TMOD register is loaded with the value 20H, indicating the use of Timer 1 in
mode 2 to set baud rate 2. The TH1 is loaded with the value to set the baud rate for serial data transfer 3. The SCON register is loaded with the value 50H, indicating Serial Mode 1 and
receive enable is turned ON 4. TR1 is set to start Timer 1 5. RI is cleared by the ‘CLR RI’ instruction 6. The RI flag bit is monitored with the instruction ‘JNB RI, XX’ 7. When RI is raised, SBUF has the byte 8. To Receive next character goto Step 5
Doubling the Baud Rate: ❖ Use a higher frequency crystal ❖ Change bit in the PCON register, shown below
PCON Register
7 6 5 4 3 2 1 0
SMOD - - - GF1 GF0 PD IDL
❖ Baud Rate Calculation for SMOD (Serial Mode) = 0
Machine Cycle Frequency = 𝐶𝑟𝑦𝑠𝑡𝑎𝑙 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
12∗32
❖ Baud Rate Calculation for SMOD (Serial Mode) = 1
Machine Cycle Frequency = 𝐶𝑟𝑦𝑠𝑡𝑎𝑙 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
12∗16
Table 4.10: Baud Rate Comparison For SMOD=0 Vs SMOD=1
TH1 (Decimal) TH1 (Hex) SMOD = 0 SMOD = 1
-3 FD 9600 19200
-6 FA 4800 9600
-12 F4 2400 4800
-24 E8 1200 2400
Example
❖ Write a program to transfer a letter ‘Y’ serially at 9600 baud continuously, and also to send a letter ‘N’ through Port 0, which is connected to a display device.
MOV TMOD,#20H MOV TH1,#-3 MOV SCON, #50H SETB TR1
YY: MOV SBUF,#’Y’ XX: JNB TI, XX
CLR TI MOV P0, #’N’
SJMP YY
❖ Write a program to receive the data which has been sent in serial form and send it out to port 0 in parallel form. Also save the data at RAM location 60H.
MOV TMOD,#20H MOV TH1,#-3
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MOV SCON, #50H SETB TR1 CLR RI
XX: JNB RI, XX MOV A, SBUF
MOV P0, A MOV 60H, A
INTERRUPT
Interrupts Vs Polling: ❖ A single microcontroller can serve several devices. There are two ways to do that:
o Interrupts
o Polling
❖ In the interrupt method, whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.
❖ Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and
serves the device.
❖ The program associated with the interrupt is called the interrupt service routine (ISR) or
interrupt handler.
❖ In polling, the microcontroller continuously monitors the status of a given device; when
the status condition is met, it performs the service.
❖ After that it moves on to monitor the next device until each one is serviced.
❖ Although polling can monitor the stats of several devices and serve each of them as
certain conditions are met, it is not an efficient use of the microcontroller.
❖ The advantage of interrupts is that the microcontroller can serve many devices; each
device can get the attention of the microcontroller based on the priority assigned to it.
❖ The polling method cannot assign priority since it checks all devices in a round-robin
fashion.
❖ In interrupt method, interrupts can be masked which is not possible in polling method.
❖ Polling method wastes microcontroller’s time by polling devices.
Interrupt Service Routine: ❖ For every interrupt there must be an ISR or Interrupt Handler
❖ When an interrupt is invoked, the microcontroller runs the ISR.
❖ For every interrupt, there is a fixed location in memory that holds the address of its ISR
❖ The group of memory locations set aside to hold the addresses of ISRs is called the
interrupt vector table, shown in table 4.12.
Steps in executing an interrupt Upon activation of an interrupt, the microcontroller goes through the following steps.
1. It finishes the instruction it is executing and saves the address of the next instruction
(PC) on the stack
2. It also saves the current status of all interrupts internally
3. It jumps to a fixed location in memory called the interrupt vector table that holds the
address of the interrupt service routine
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4. The microcontroller gets the address of the ISR from the interrupt vector table and jumps
to it. It starts to execute the interrupt service subroutine until it reaches the last
instruction of the subroutine, which is RETI
5. Upon executing the RETI instruction, the microcontroller returns to the place where it
was interrupted. First it gets the PC address from the stack by popping the two bytes of
the stack into PC. Then it starts to execute from the address.
Interrupt Sources ❖ The 8051 architecture can handle interrupts from 5 sources.
❖ These are:
o Two external interrupt lines,
o Two timers
o Serial interface
❖ Each one of these is assigned an interrupt vector address. This is quite similar to the
RST interrupt vectors in the case of 8085.
❖ External Interrupts o Port P3 of 8051 is a multi-function port.
o Different lines of this port carry out functions which are additional to data input-
output on the port.
o Lines P3.2 and P3.3 can be used as interrupt inputs.
o Interrupts will be caused by a ‘LOW’ level, or a negative edge on these lines.
o Half of the special function register TCON is used for setting the conditions for
causing interrupts from external sources. This register is bit addressable.
SFR TCON at byte address 88H
Table 4.11: TCON Register Description
BIT Symbol Functions
3 IE1 External interrupt 1 Edge flag.
Not related to timer operations
2 IT1
External interrupt1 signal type control bit.
Set to 1 by program to Enable external interrupt 1 to be
triggered by a falling edge signal. (Edge Sensitive)
Set to 0 by program to enable a low level signal on external
interrupt 1 to generate an interrupt. (Level Sensitive)
1 IE0 External interrupt 0 Edge flag.
Not related to timer operations.
0 IT0
External interrupt 0 signal type control bit.
Set to 1 by program to Enable external interrupt 0 to be
triggered by a falling edge signal. (Edge Sensitive)
Set to 0 by program to enable a low level signal on external
interrupt 0 to generate an interrupt. (Level Sensitive)
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o If the flag is 1, the selected type of event (edge or level) has occurred on the
corresponding interrupt line.
❖ Internal Interrupts o Internally generated interrupts can be from either timer, or from the serial
interface.
o The serial interface causes interrupts due to a receive event (RI) or due to a
transmit event (TI).
o The receive event occurs when the input buffer of the serial line (SBUF in) is full
and a byte needs to be read from it.
o The transmit event indicates that a byte has been sent a new byte can be written
to output buffer of the serial line (SBUF out).
o 8051 timers always count up. When their count rolls over from the maximum
count to 0000, they set the corresponding timer flag TF1 or TF0 in TCON.
o Counters run only while their run flag (TR1 or TR0) is set by the user program.
o When the run flag is cleared, the count stops incrementing.
o The 8051 can be setup so that an interrupt occurs whenever TF1 or TF0 is set.
❖ Enabling Interrupts o At power-up, all interrupts are disabled.
o Suppose Timer 0 is started. When it times out, TF0 in the special function
register TCON will be set.
o However, this will not cause an interrupt.
o To enable interrupts, a number of steps need to be taken.
o Interrupts are enabled in a manner which is quite similar to the 8085.
o There is an interrupt enable special function register IE at byte address A8H.
o This register is bit addressable. (The assembler gives special mnemonics to
each bit address.)
SFR Interrupt Enable (IE) Register
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❖ Interrupt Vectors o When an interrupt occurs, the updated PC is pushed on the stack and is loaded
with the vector address corresponding to the interrupt.
o The following table 4.12 gives the vector addresses.
o The order of entries in the table is also the order in which the 8051 will poll these
in case of multiple interrupts
Table 4.12: Interrupt and Vector Address
Interrupt Source Vector Address
External Interrupt 0 0003H
Timer 0 Overflow 000BH
External Interrupt 1 0013H
Timer 1 Overflow 001BH
Serial Interface 0023H
o 8051 starts executing from address 0000H at power-up or reset.
o The first 3 bytes are typically used for placing a long jump instruction to start of
the code area.
o The interrupt vectors start from 0003 and are separated by 8 bytes from each
other.
o Many simple interrupt handlers can be accommodated in this space.
o Otherwise, jump instructions (to handler locations) need to be placed at the
vector addresses.
o This is quite similar to the RST handlers for 8085.
o Thus, to enable interrupts from T0, we have to do
SetB EA ;(or SetB IE.7) to enable interrupts
SetB ET0 ;(or SetB IE.1) to enable interrupts from T0
o After this, whenever T0 overflows, TF0 will be set (in SFR TCON), the currently
running program will be interrupted, its PC value will be put on the stack (PC-L
first, PC-H after – because the stack grows upwards in 8051), and PC will be
loaded with 000B H.
o The interrupt handler for T0 should be placed here, and it should end with the
instruction: RETI
❖ Interrupt Priorities o 8051 has two levels of interrupt priorities:
▪ High or Low.
o When 8051 is powered up, the priorities are assigned according to the table 4.13.
Table 4.13 8051/52 Interrupt Priority Upon Reset
Highest to Lowest Priority
External Interrupt 0 INT0
Timer Interrupt 0 TF0
External Interrupt 1 INT1
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Timer Interrupt 1 TF1
Serial Communication RI + TI
Timer 2 (8052 only) TF2
o Setting Interrupt Priority
▪ By assigning priorities, the order of multiple interrupts can be controlled
and serviced.
▪ Priorities are set by bits in a special function register called IP (Interrupt
Priority), which is at the byte address B8H.
▪ This register is also bit addressable.
▪ The assembler defines special names for bits of this register.
SFR IP Register at byte address B8H
❖ Notice that the bits are in the polling order of interrupts.
❖ A ‘1’ in a bit position assigns a high priority to the corresponding source of interrupts and
‘0’ gives it a low priority.
❖ In case of multiple interrupts, the following rules apply:
o While a low priority interrupt handler is running, if a high priority interrupt arrives,
the handler will be interrupted and the high priority handler will run. When the
high priority handler does ‘RETI’, the low priority handler will resume. When this
handler does ‘RETI’, control is passed back to the main program.
o If a high priority interrupt is running, it cannot be interrupted by any other source
– even if it is a high priority interrupt which is higher in polling order.
o A low-priority interrupt handler will be invoked only if no other interrupt is already
executing. Again, the low priority interrupt cannot preempt another low priority
interrupt, even if the later one is higher in polling order.
o If two interrupts occur at the same time, the interrupt with higher priority will
execute first. If both interrupts are of the same priority, the interrupt which is
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higher in polling sequence will be executed first. This is the only context in which
the polling sequence matters.
Serial Interrupts ❖ Serial interrupts are handled somewhat differently from the timers.
❖ There are independent interrupt flags for reception and transmission of serial data,
called RI and TI.
❖ RI indicates that a byte has been received and is available for reading in the input buffer.
❖ TI indicates that the previous byte has been sent serially and a new byte can be written
to the serial port.
❖ A serial interrupt occurs if either of these flags is set. (Of course the serial interrupt must
be enabled for this to occur).
❖ The interrupt service routine should check which of these events caused the interrupt.
❖ This can be done by examining the flags.
❖ Either or both of the flag might be set, requiring a read from or write to the serial buffer
SBUF (or both).
❖ Recall that the input and output buffers are distinct but are located at the same address.
❖ A read from this address reads the input buffer while a write to the same address writes
to the output buffer.
❖ The RI and TI flags are not automatically cleared when an interrupt is serviced.
❖ Therefore, the interrupt service routine must clear them before returning.
❖ Here is an example handler for serial interrupts:
❖ Write a program in which the 8051 reads data from P1 and writes it to P2
continuously while giving a copy of it to the serial COM port to be transferred
serially. Assume that XTAL=11.0592MHz. Set the baud rate at 9600.